Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 25, 1997 – Re vised July 29, 1997
CY2305 and CY2309 as PCI and SDRAM Buffers
Introduction to Cypress Zero Delay Buffer s
What is a Zero Delay Buffer?
A zero delay b uffer is a de vice that can fan out 1 clock signal
into multiple clock signals with zero delay and ver y low skew
between the outputs. This device is well suited as a buffer for
PCI or SDRAM due to its zero input to out put delay and very
low output to output skew.
A simplified diagram of the CY2308 zero delay buffer is shown
in Figure 1. The CY2308 is built using a PLL that uses a ref-
erence input and a feedback input. The feedback loop is
closed by driving the feedback input (FBK) from one of the
outputs. The phase detector in the PLL adjusts the output
frequency of the VCO so that the two inputs have no phase
difference. Since an output is one of the inputs to the PLL,
zero phase difference is maintained from REF to the output
driving FBK. Now if all outputs are uniformly loaded, zero
phase difference will be maintained from REF to all outputs.
This is a simple zero delay buffer. Introducing additional de-
vices (e.g., dividers) between the output and FBK can give
rise to some innovative applications for the PLL, and for fur-
ther information on these refer to the Cypress Application
Note “CY2308 Zero Delay Buffer”. Since many bufferi ng ap-
pli cations require only a simple closur e of t he feedbac k loop,
Cypress has designed zero delay buffers with Internal Feed-
back Loops: the CY2305 and CY2309.
What are the CY2305 and CY2309?
Cypres s h as d esigned z ero de la y b u ff er s especial ly suited f or
use with PCI or SDRAM buffering. The CY2305 and CY2309
have been designed with the feedback path integrated for
simpler system design. A simplified block diagram of the
CY2309 zero delay buffer is shown Figur e 2. Thi s zero delay
buffer uses a input/output pad on CLKOUT so that the feed-
back signal can be sensed direc tly from the output itself.
Drive Capabi li ty
The CY2305 and CY2309 have high drive outputs designed
to meet the JEDEC SDRAM specifications of 30 pF capaci-
tance on each DIMM clock input.
Since the typi cal CMOS input is 7 pF and the CY2305/0 9 are
designed to dri ve up to 30 pF; thi s m eans that up to 4 CMOS
inputs can be driven from a single output of a CY2305/09.
How ever t he ou tput loadi ng o n the CY2305/ 09 mu st be equal
on all outputs to maintain zer o delay from the input .
Power Down
The CY2305 and CY2309 ha ve a un ique power-down mode:
if t he in put r ef ere nce is st oppe d, th e part au tomati call y enter s
a shutdown state, shutting down the PLL and three-stating the
output s. Whe n the part is i n shutdo wn mode i t dra ws less than
50 µA, and can come out of shutdown mode with the PLL
locked in les s than 1 m s. This power down mode can also be
entered by three-stating the input refere nce dri ver and allow-
ing the internal pull-down to pull the input LOW (the input
does not have to go LO W, it only has to stop).
5 Volt to 3.3 Volt Level Shifting
The CY2305 and CY2309 can ac t as a 5-volt to 3.3-volt lev el
shifter. The reference input pad is 5-volt signal-compatible.
Since many system components still operate at 5 volts, this
feature provides the capability to generate multiple 3.3-volt
clocks from a single 5-volt reference clock. This 5-volt sig-
nal-compatibility is only available on the reference pad; the
other i nput pads on the CY2309 are not 5-volt com patible.
Figure 1. Simplified Block Diagr am of CY2308
VCO
REF CLKA1
CLKA2
CLKA3
CLKA4
FBK
Loop
Filter
Phase
Detector PLL MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4
Figure 2. Simplified Block Di agram of CY2309
VCO
REF CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
Loop
Filter
Phase
Detector PLL MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
2
Lead or Lag Adjustments
To adjust the lead or lag of the outputs on the CY2305 or
CY2309, one must understand the relationships between
REF and CLKOUT, and the relationship between CLKOUT
and t he ot her out puts . To under sta nd the r elat ionshi p , f irst w e
need to understand a few properties of the CY2305 and
CY2309 Phase Loc ke d Loops. The PLL senses the phase of
the CLKOUT pin at a threshold of Vdd/2 and compares it to
the REF pi n at the s ame Vdd/ 2 thres hold. All the ou tputs s tart
thei r tr ansit ion at the same t ime (i ncludi ng CLK O UT). Ch ang-
ing the l oad on an output changes its rise time and ther efore
how long it takes the output to get to the Vdd/2 threshold.
Using these properties to our advantage, w e can then adjust
the time when the outputs reach the Vdd/2 threshold relative
to when the REF input reac hes the Vdd/2 threshold. The CLK-
OUT output however cannot be adjusted: it will always have
zero delay from the REF input at Vdd/2. The outputs can be
advanced by loading the CLKOUT out put more heavily than
the ot her outputs or can be dela y ed by loading CLK OUT more
lightly than the other outputs. Figure 3 shows how many ps
the outputs are moved vs. the difference in the loading be-
tween CLKOUT and the other outputs. As a rough guideline,
the adjustment is 50 ps/pF of loading difference. Note: the
zero delay buffer will always adjust itself to keep the Vdd/2
point of the output at zero delay from the Vdd/2 point of the
reference. If the application requires the outputs of the zero
delay buffer to have zero delay from another output of the
ref erence cl ock chip , the output of the clock chip that is driving
the zero delay buffer must be loaded the same as the other
output s of the c lock ch ip or the output s of the zero delay buffer
will be advanced/delayed with reference to those other out-
puts.
Figure 3. Lead Lag Adjustments
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
3
Output To Output Skew
The skew between CLKOUT and the other outputs is not dy-
namically adjusted by the loop. All MUST have the same load
on them to achieve zero output to output skew. If the other
outputs are less loaded than CLKOUT, they will lead it; and if
the other outputs are more loaded, they will lag the CLKOUT.
The relationship that e xists between the CLKOUT and the rest
of the out puts i s that t hey al l start the rising edge at the sam e
time, but different loads wil l cause them to have dif ferent rise
times and different times crossing the measurement thresh-
olds . Si nce CLK OUT is t he only output that is monitor ed, it will
be the output that has the zero dela y from the reference and
the other clocks will be relative to CLKOUT and their loading
differences.
Zero Delay Buffer Timing diagrams with differe nt loading configurations.
REF input and all
REF
CLKOUT
CLKA1
CLKA4
outputs loaded equall y
REF input and CLKA1-CLKB4 load ed
equally, with CLKO UT loade d l ess
REF i nput and CLKA1-CLKB4 loaded
REF
CLKOUT
equally, with CLKOUT loaded more
Advanced
REF
CLKOUT
Delayed
Zero D e lay
CLKB1
CLKB4
CLKA1
CLKA4
CLKB1
CLKB4
CLKA1
CLKA4
CLKB1
CLKB4
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
4
Pr oduc t Information
The CY2305 Zero Delay Buffer
The CY2305 is a 3.3-volt, five output zero delay buffer in an
8-pin 150-mil S OIC packag e. This part is intend ed for buff er-
ing one clock into five clocks for PCI buffering or four clocks
for use with 1 SDRAM module. The CY2305 is the simplest
and ea siest to use part i n the Cypr ess z ero dela y buff er f amily.
For a discussion of the special features of the CY2305 see
the special features sectio n of this application note, or for the
complete specifications on the CY2305 please refer to the
CY2305/CY2309 data sheet.
The CY2309 Zero Delay Buffer
The CY2309 is a 3.3-volt, nine output zero delay buffer in a
16-pin 150-mil SOIC package. This par t is intended for buff-
ering one clock into 9 clocks for PCI buffering or eight clocks
for use with 2 SDRAM m odules. For the complete specifica-
tions please refer to the CY2305/CY2309 data sheet.
The CY2309 has several opti ons f or shutt ing do wn t he outpu t
banks or compl etel y shutt ing down the part to conserv e pow-
er. As sho wn in the ta ble below, the inputs S1 and S2 control
which output banks are dr iven and the state of the PLL. You
will notice that the CLKOUT output is always driven. This is
because th e PL L m ust h a ve th e CLKOUT pi n runni ng i n order
to maint ain phase l ock. The CY2309 will al so go into a po we r
down state if the input reference stops as described in the
“Special Features of the Cypress Zero Delay Buffers” section.
VCO
REF CLK1
CLK2
CLK3
CLK4
CLKOUT
LP
Filter
Phase
Detector
PLL
1
2
3
45
8
7
6
REF
CLK2
CLK1
GND VDD
CLKOUT
CLK4
CLK3
SOIC
Top View
VCO
EF CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
LP
Filter
Phase
Detector PLL MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4
1
2
3
413
16
15
14
REF
CLKA1
CLKA2
VDD
CLKA3
CLKOUT
CLKA4
VDD
SOIC
Top View
5
6
7
8
GND
CLKB1
CLKB2
S2 9
12
11
10 CLKB3
GND
CLKB4
S1
Sel ect Input Decoding f or CY2309
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLK OUT[1] Output Source PLL Shutdown
0 0 Three-State Three-State Driven PLL N
0 1 Driven Three-State Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
Note:
1. This ou tput is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the delay between the
reference and the CLKA/CLKB outputs.
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
5
Applications
5 and 9 PCI Devi ce/Slot Zer o Delay Buff er Solution
The CY2305 and CY2309 are an excellent clocking solution
for a system that requires mor e PCI clocks than the currently
popular clock chips provide. The CY2305 comes in a tiny
150-mil 8-pin SOIC package and the CY2309 comes in a
small 150-mil 16-pin SOIC package. The CY2305 and
CY2309 are priced v ery aggressi vely for the high volum e PC
market. There are two solutions for implementing a PCI zero
delay buffer with the Cypress zero delay buffers: a 5 de-
vice/slot and a 9 device/slot buffer.
The 5 Device/Slot Soluti on:
•PCI/Slot 1 (CLKOUT) must always be loaded.
•If PCI Slot s represent diffe rent loads , t hey will ha ve earlie r
or lat er clocks (See Lead or Lag Adj ustments section of
“Special Features of Cypr ess Zero Delay Buffers ”.
The 9 Device/Slot Soluti on:
•PCI/Slot 1 (CLKOUT) must always be loaded.
•Select lines can be used to shut down output banks, see
CY2309 data sheet.
1 SDRAM DIMM Zer o Delay Buffer Solution
The CY2305 is an excellent clocking solution for a system
using 1 SDRAM DIMM. The CY2305 comes in a very small
150-mil 8-pin SOIC package and is priced very aggressively
for the high volume PC market. There are two solutions for
implementing 1 SDRAM DIMM su pport with the CY2305: t he
first is the ad jus table dela y solution, and the second is t he self
adju sti ng del ay solu tion .
The Adjust able Delay Solution:
•Cload must be equal to SDRAM module loadi ng for zero
delay.
•To make the SDRAM inputs le ad or lag t he ref erence input
see the Lead or Lag Adjustments section of “Special Fea-
tures of the Cypress Zero Delay Buffers”.
The Self Adjusting Solution:
•This sol uti on will autom ati cally compensate for different
SDRAM input loads.
•CLKOUT must driv e CK0 on the SDRAM module so that
CLKOUT is always fully loaded (pin 42 on the SDRAM
module).
CY2305
Zero Delay
Buffer
PCICLK
CLK4
REF
CLK3
CLK2
CLK1
4 PCI Devi ces/Slots
CLKOUT PC I D evice 1
CY2309
Zero Delay
Buffer
PCICLK
CLKA4
REF
CLKA3
CLKA2
CLKA1
4 PCI Devices/Slots
CLKOUT PCI Device 1
CLKB1
4 PCI Devices/Slots
CLKB2
CLKB3
CLKB4
S1
S2
Vdd
CY2305
SDRAM Module
Zero Del ay
Buffer
CPUCLK
CLK4
CLK3
CLK2
CLK1
CLKOUTREF Cload
CY2305 SDRAM Module
Zero Del ay
Buffer
CPUCLK
CLK4
CLK3
CLK2
CLK1
REF CLKOUT
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
6
2 SDRAM DIMM Zero Dela y Buffer Solution
The CY2309 is an excellent clocking solution for a system
using 2 SDRAM DIMMs. The CY2309 comes in a small
150-mi l 16-pin SOIC pac kage and is priced v ery aggr essiv ely
for the high volume PC market. There are two solutions for
implementing 2 SDRAM DIMMs support with the CY2309:
the firs t is the a dj ustab le delay s olu tion, an d t he second i s the
self adjust ing delay solution.
The Adjust able Delay Solution:
•Cload must be equal to SDRAM module loadi ng for zero
delay.
•To make the SDRAM inputs le ad or lag t he ref erence input
see the Lead or Lag Adjustments section of “Special Fea-
tures of the Cypress Zero Delay Buffers”.
•Clocks are three-stated when that SDRAM module i s not
present.
•If only 1 SDRAM module is i nstalled it must be module 1.
The Self Adjusting Solution:
•This solution wil l automatically compensate for dif ferent
SDRAM input l oads (only on module 1).
•CLK OUT must driv e CK0 on the SDRAM module 1 so t hat
CLKOUT is always fu ll y loaded (pin 42 on the SDRAM
module).
•If only one SDRAM module is installed it must be module 1.
•CLKA and CLKB clocks are three-stated when their re-
specti ve SDRAM module is not present, b ut CLK OUT wil l
continue to run.
CY2309 SDRAM Module 1
Zero Del ay
Buffer
CPUCLK
CLKA4
CLKA3
CLKA2
CLKA1
CLKOUTREF Cload
SDRAM Module 2
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
Decoding
Logic
CY2309 SDRAM Module 1
Zero Del ay
Buffer
CPUCLK
CLKA4
CLKA3
CLKA2
CLKA1
REF
SDRAM Module 2
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CLKOUT
Decoding
Logic
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
7
3 SDRAM DIMM Zero Dela y Buffer Solution
The CY2305 and CY2309 are e x celle nt cloc king soluti ons f or
a system using 3 SDRAM DIMMs. The CY2305 comes in a
small 150-m il 8-pin SOI C pac kage and t he CY2309 c omes in
a small 150-mil 16-pin SOIC. Both buffers are priced very
aggressively for the high volume PC market. There are two
solu ti ons for implementing 3 SDRAM DIMMs support with the
CY2305 and CY2309: the first is the adjustable delay solution,
and the second is the self adjusti ng delay solution.
The Adjust able Delay Solution:
•Cload1 and Cload2 must be equal to SDRAM module loading
for zero delay.
•To make the SDRAM inputs le ad or lag t he ref erence input
see the Lead or Lag Adjustments section of “Special Fea-
tures of the Cypress Zero Delay Buffers”.
•SDRAM modules must be installed in or der (modul e 1 first
and module 3 last).
•Module 2 and 3 clocks are three-stated when those
SDRAM modules are not present, bu t CLKOUT will
continue to run.
•Module 1 cl oc ks can o nly be three- st ated b y three- st ating
CPUCLK which will also three-state modules 2 and 3.
CY2309 SDRAM Module 2
Zero Del ay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUTREF Cload2
SDRAM Module 3
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CY2305
SDRAM Module 1
Zero Delay
Buffer
CPUCLK
CLK1
CLK2
CLK3
CLK4
CLKOUTREF Cload1
Decoding
Logic
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
8
The Self Adjusting Solution:
•This solution wil l automatically compensate for dif ferent
SDRAM input l oads (only on Module 1 and Module 2).
•CLKOUT must driv e CK0 on the SDRAM mod ule 1 and
modu le 2 so th at CLKOUT is alway s ful ly l oaded (pin 42
on the SDRAM module).
•SDRAM modules must be installed in or der (modul e 1 first
and module 3 last).
•Module 2 and 3 clocks are three-stated when those
SDRAM modules are not present, but CLK OUT will contin-
ue to run.
•Module 1 cl oc ks can o nly be three- st ated b y three- st ating
CPUCLK which will also three-state modules 2 and 3.
CY2309 SDRAM Module 2
Zero Delay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUTREF
SDRAM Module 3
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CY2305
SDRAM Module 1
Zero Del ay
Buffer
CPUCLK
CLK4
CLK3
CLK2
CLK1
CLKOUTREF
Decoding
Logic
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
9
4 SDRAM DIMM Zero Dela y Buffer Solution
Two CY230 9s are an excellent clo cking solutio n for a system
using 4 SDRAM DIMMs. The CY2309 comes in a small
150-mi l 16-pin SOIC pac kage and is priced v ery aggr essiv ely
for the high volume PC market. There are two solutions for
implementing 4 SDRAM DIMMs support with the CY2309:
the firs t is the a dj ustab le delay s olu tion, an d t he second i s the
self adjust ing delay solution.
The Adjust able Delay Solution:
•Cload1 and Cload2 must be equal to SDRAM module loading
for zero delay.
•To make the SDRAM inputs le ad or lag t he ref erence input
see the Lead or Lag Adjustments section of “Special Fea-
tures of the Cypress Zero Delay Buffers”.
• Clock s are thre e-stated when that S DRAM module i s not
present.
•SDRAM modules must be installed in or der (modul e 1 first
and module 4 last).
CY2309 SDRAM Module 3
Zero Del ay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUTREF Cload2
SDRAM Module 4
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CY2309 SDRAM Module 1
Zero Delay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUT
REF Cload1
SDRAM Module 2
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CPUCLK
Decoding
Logic
Decoding
Logic
CY2305 and CY230 9 as PCI and SDRAM Buf f e rs
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semicon ductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authoriz e
its products for use as critical components in life-support sy stems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life- support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
The Self Adjusting Solution:
•This solution wil l automatically compensate for dif ferent
SDRAM input l oads (only on Module 1 and Module 3).
•CLKOUT must driv e CK0 on the SDRAM mod ule 1 and
modu le 3 so th at CLKOUT is alway s ful ly l oaded (pin 42
on the SDRAM module).
•SDRAM modules must be installed in or der (modul e 1 first
and module 4 last).
•Clocks are three-stated when that SDRAM module i s not
present, but CLKOUT will continue to run.
CY2309 SDRAM Module 3
Zero Del ay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUTREF
SDRAM Module 4
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CY2309 SDRAM Module 1
Zero Delay
Buffer CLKA4
CLKA3
CLKA2
CLKA1
CLKOUT
REF
SDRAM Module 2
CLKB4
CLKB3
CLKB2
CLKB1
S1
S2
Module Sense
Module Sense
CPUCLK
Decoding
Logic
Decoding
Logic
