CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Supports Pentium III Class Motherboards
D
Uses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
D
Includes Spread Spectrum Clocking (SSC),
0.34% Downspread for Reduced EMI
Performance
D
Power Management Control Terminals
D
Low Output Skew and Jitter for Clock
Distribution
D
2.5-V and 3.3-V Supplies
D
Generates the Following Clocks:
– 4 CPU (2.5 V, 100/133 MHz)
– 7 PCI (3.3 V, 33.3 MHz)
– 1 PCI_F (Free Running, 3.3 V, 33.3 MHz)
– 2 CPU/2 (2.5 V, 50/66 MHz)
– 3 APIC (2.5 V, 16.67 MHz)
– 4 3V66 (3.3 V, 66 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 1 48MHz (3.3 V, 48 MHz)
D
Packaged in 56-Pin SSOP Package
D
Designed for Use with TI’s Direct Rambus
Clock Generators (CDCR81, CDCR82,
CDCR83)
description
The CDC925 is a clock synthesizer/driver that
generates system clocks necessary to support
Intel Pentium III systems on CPU, CPU_DIV2,
3V66, PCI, APIC, 48MHz, and REF clock signals.
All output frequencies are generated from a
14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two
phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz
clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All
outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN
terminal, the device operates normally, but when a logical low-level input is applied, the device powers down
completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or
CPU_STOP, the outputs operate normally . With a low-level applied to the PCI_STOP or CPU_STOP terminals,
the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding
setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
REF0
REF1
VDD3.3V
XIN
XOUT
GND
PCI_F
PCI1
VDD3.3V
PCI2
PCI3
GND
PCI4
PCI5
VDD3.3V
PCI6
PCI7
GND
GND
3V66(0)
3V66(1)
VDD3.3V
GND
3V66(2)
3V66(3)
VDD3.3V
SEL133/100
VDD2.5V
APIC2
APIC1
APIC0
GND
VDD2.5V
CPU_DIV2(1)
CPU_DIV2(0)
GND
VDD2.5V
CPU3
CPU2
GND
VDD2.5V
CPU1
CPU0
GND
VDD3.3V
GND
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
VDD3.3V
48MHz
GND
DL PACKAGE
(TOP VIEW)
Intel and Pentium III are trademarks of Intel Corporation.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
Since the CDC925 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL.
This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an
external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts.
function tables
SELECT FUNCTIONS
INPUTS OUTPUTS
SEL133/
100 SEL1 SEL0 CPU CPU_DIV2 3V66 PCI,
PCI_F 48MHz REF APIC FUNCTION
L L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 3-state
L L H N/A N/A N/A N/A N/A N/A N/A Reserved
LH L 100 MHz 50 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off
LH H 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on
H L L TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test
H L H N/A N/A N/A N/A N/A N/A N/A Reserved
HH L 133 MHz 66 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off
H H H 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on
ENABLE FUNCTIONS
INPUTS OUTPUTS INTERNAL
CPU_STOP PWR_DWN PCI_STOP CPU CPU_DIV2 APIC 3V66 PCI PCI_F REF,
48MHz Crystal VCOs
X L X L L L L L L L Off Off
LHLLOn On L L On On On On
LHHLOn On L On On On On On
HHLOnOn On On L On On On On
H H H On On On On On On On On On
OUTPUT BUFFER SPECIFICATIONS
BUFFER NAME VDD RANGE
(V) IMPEDANCE
()BUFFER TYPE
CPU, CPU_DIV2, APIC 2.375 – 2.625 13.5 – 45 TYPE 1
48MHz, REF 3.135 – 3.465 20 – 60 TYPE 3
PCI, PCI_F, 3V66 3.135 – 3.465 12 – 55 TYPE 5
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
3V66 [0–3] 21, 22, 25, 26 O3.3 V, Type 5, 66-MHz clock outputs
48MHz 30 O3.3 V, Type 3, 48-MHz clock output
APIC [0–2] 53, 54, 55 O2.5 V, Type 1, APIC clock outputs
CPU [0–3] 41, 42, 45, 46 O2.5 V, Type 1, CPU clock outputs
CPU_DIV2 [0–1] 49, 50 O2.5 V, Type 1, CPU_DIV2 clock outputs
CPU_STOP 36 IDisables CPU clock to low state
GND 1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
Ground
PCI [1–7] 9, 11, 12, 14,
15, 17, 18
O3.3 V, Type 5, 33-MHz PCI clock outputs
PCI_F 8 O Free-running 3.3-V, Type 5, 33-MHz PCI clock output
PCI_STOP 37 IDisables PCI clock to low state
PWR_DWN 35 IPower down for complete device with outputs forced low
REF0, REF1 2, 3 O3.3 V, Type 3, 14.318-MHz reference clock output
SEL0, SEL1 32, 33 ILVTTL level logic select terminals for function selection
SEL133/100 28 ILVTTL level logic select pins for enabling 100/133 MHz
SPREAD 34 IDisables SSC function
VDD3.3V 4, 10, 16, 23,
27, 31, 39 Power for the 3V66, 48MHz, PCI, REF outputs and CORE logic
VDD2.5V 43, 47, 51, 56 Power for CPU and APIC outputs
XIN 5 I Crystal input – 14.318 MHz
XOUT 6 O Crystal output – 14.318 MHz
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
spread spectrum clock (SSC) implementation for CDC925
Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency,
which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation
of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak.
A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in
Figure 1.
Highest Peak
Non-SSC
SSC
δ of fnom fnom
Figure 1. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a
“down-spread modulation”.
The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation was driven to keep
the average clock frequency closed to its upper specification limit. The modulation amount was set to
approximately –0.34% (compared to –0.5% on the CDC924).
In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation
signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for
CDC925 is shown in Figure 2.
51015202530354045
Period of Modulation Signal – µs
9.97
9.98
9.99
10
10.01
10.02
10.03
Period of Output Frequency – ns
Figure 2. SSC Modulation Profile
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
2*REF
14.318 MHz
(2,3)
SEL133/100
PWR_DOWN
PCI_STOP
SPREAD
XOUT
XIN
SEL1
SEL0 Control
Logic
28
33
32
3–State
Test
48–MHz Inactive
SEL133/100
Xtal
Oscillator
6
548 MHz
PLL
CPU
PLL
Spread
Logic
Sync Logic & Power Down Logic
/2 /2
34
37
36
35
1*48MHz
48 MHz
(30)
3*APIC
16.67 MHz
(53, 54, 55)
1*PCI_F
33 MHz
(8)
7*PCI
33 MHz
(9,11,12,14,
15,17,18)
4*AGP (3V66)
66 MHz
(21,22,25,26)
2*CPU_DIV2
50/66 MHz
(49,50)
4*CPU
100/133 MHz
(41,42,45,46)
/3
/4 STOP
STOP
CPU_STOP
/3
/4
/2
STOP
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance state or power-off state,
VO (see Note 1) 0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 2 × IOL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) 18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
DISSIPATION RATING TABLE
PACKAGE
T
A
25°CDERATING FACTOR
T
A
= 70°C T
A
= 85°C
PACKAGE
A
POWER RATNG ABOVE TA = 25°C
A
POWER RATING
A
POWER RATING
DL 1558.6 mW 12.468 mW/°C997.5 mW 810.52 mW
This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted device
at 80.2°C/W.
recommended operating conditions (see Note 2)
MIN NOMMAX UNIT
Su
pp
ly voltage VDD
3.3 V 3.135 3.465
V
S
u
ppl
y v
oltage
,
V
DD 2.5 V 2.375 2.625
V
High-level input voltage, VIH 2VDD +
0.3 V V
Low-level input voltage, VIL GND –
0.3 V 0.8 V
Input voltage, VI0 VDD V
CPUx, CPU_DIV2x –12
High level out
p
ut current IOH
APICx –12
mA
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OH 48MHz, REFx –14
mA
PCIx, PCI_F, 3V66x –18
CPUx, CPU_DIV2x 12
Low level out
p
ut current IOL
APICx 12
mA
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OL 48MHz, REFx 9
mA
PCIx, PCI_F, 3V66x 12
Reference frequency, f(XIN)Test mode 130 MHz
Crystal frequency, f(XTAL)§Normal mode 13.8 14.318 14.8 MHz
Operating free-air temperature, TA0 85 °C
NOTE 2: Unused inputs must be held high or low to prevent them from floating.
All nominal values are measured at their respective nominal VDD values.
Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven
externally up to f(XIN) = 130 MHz. If XIN is driven externally, XOUT is floating.
§This is a series fundamental crystal with fO = 14.31818 MHz.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK Input clamp voltage VDD = 3.135 V, II = –18 mA –1.2 V
RIInput resistance XIN-XOUT VDD = 3.465 V, VI = VDD –0.5 V 80 350 k
XOUT VDD = 3.135 V, VI = VDD –0.5 V 20 50 mA
IIH High-level input current
SEL0, SEL1,
CPU_STOP,
PCI_STOP,
SPREAD
VDD = 3.465 V, VI = VDD <10 10 µA
PWR_DWN VDD = 3.465 V, VI = VDD <10 10 µA
SEL133/100 VDD = 3.465 V, VI = VDD <10 10 µA
XOUT VDD = 3.135 V, VO = 0 V –2 –5 mA
IIL Low-level input current
SEL0, SEL1,
CPU_STOP,
PCI_STOP,
SPREAD
VDD = 3.465 V, VI = GND <10 –10 µA
PWR_DWN VDD = 3.465 V, VI = GND <10 –10 µA
SEL133/100 VDD = 3.465 V, VI = GND <10 –10 µA
IOZ High-impedance-state output current |VDD| = max, VO = VDD or GND ±10 µA
VDD = 2.625 V,
All outputs = low PWR_DWN = low, <20 100
I
Suppl
y
current VDD = 2.625 V,
All outputs = high VDDx = 2.5 V, <20 100 µA
y
VDD = 3.465 V,
All outputs = low PWR_DWN = low, <50 200
VDD = 3.465 V, All outputs = high 12 35 mA
High im
p
edance state su
pp
ly current
VDD = 2.625 V 1.4
mA
DD(Z)
High
-
impedance
-
state
s
u
ppl
y
c
u
rrent
VDD = 3.465 V 28
mA
Dynamic su
pp
ly current
CL = 20 pF, VDD = 3.465 V 114 146
mA
D
y
namic
s
u
ppl
y
c
u
rrent
L
CPU = 133 MHz VDD = 2.625 V 52 70
mA
CIInput capacitance VDD = 3.3 V, VI = VDD or GND 3.3 5.8 pF
Crystal terminal capacitance VDD = 3.3 V, VI = 0.3 V 18 18.5 22.5 pF
All typical values are measured at their respective nominal VDD values.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CPUx, CPU_DIV2x, APICx (Type 1)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
V
OH
Hi
g
h-level output volta
g
eVDD = min to max, IOH = –1 mA VDD –
0.1 V V
OH
gg
VDD = 2.375 V, IOH = –12 mA 2
VOL
Low level out
p
ut voltage
VDD = min to max, IOL = 1 mA 0.1
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VDD = 2.375 V, IOL = 12 mA 0.18 0.4
V
VDD = 2.375 V, VO = 1 V –26 –42
IOH High-level output current VDD = 2.5 V, VO = 1.25 V –46 mA
VDD = 2.625 V, VO = 2.375 V –16 –27
VDD = 2.375 V, VO = 1.2 V 27 57
IOL Low-level output current VDD = 2.5 V, VO = 1.25 V 63 mA
VDD = 2.625 V, VO = 0.3 V 23 43
COOutput capacitance VDD = 3.3 V, VO = VDD or GND 6 8.5 pF
ZO
Out
p
ut im
p
edance
High state VO = 0.5 VDD, VO/IOH 13.5 27 45
Z
O
O
u
tp
u
t
impedance
Low state VO = 0.5 VDD, VO/IOL 13.5 20 45
All typical values are measured at their respective nominal VDD values.
48MHz, REFx (Type 3)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
V
OH
High-level output voltage VDD = min to max, IOH = –1 mA VDD –
0.1 V V
OH
gg
VDD = 3.135 V, IOH = –14 mA 2.4
VOL
Low level out
p
ut voltage
VDD = min to max, IOL = 1 mA 0.1
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VDD = 3.135 V, IOL = 9 mA 0.18 0.4
V
VDD = 3.135 V, VO = 1 V –27 –41
IOH High-level output current VDD = 3.3 V, VO = 1.65 V –41 mA
VDD = 3.465 V, VO = 3.135 V –12 –23
VDD = 3.135 V, VO = 1.95 V 29 50
IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 53 mA
VDD = 3.465 V, VO = 0.4 V 20 37
COOutput capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7 pF
ZO
Out
p
ut im
p
edance
High state VO = 0.5 VDD, VO/IOH 20 40 60
Z
O
O
u
tp
u
t
impedance
Low state VO = 0.5 VDD, VO/IOL 20 31 60
All typical values are measured at their respective nominal VDD values.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PCIx, PCI_F, 3V66x (Type 5)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
V
OH
Hi
g
h-level output volta
g
eVDD = min to max, IOH = –1 mA VDD –
0.1 V V
OH
gg
VDD = 3.135 V, IOH = –18 mA 2.4
VOL
Low level out
p
ut voltage
VDD = min to max, IOL = 1 mA 0.1
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VDD = 3.135 V, IOL = 12 mA 0.15 0.4
V
VDD = 3.135 V, VO = 1 V –33 –53
IOH High-level output current VDD = 3.3 V, VO = 1.65 V –53 mA
VDD = 3.465 V, VO = 3.135 V –16 –33
VDD = 3.135 V, VO = 1.95 V 30 67
IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 70 mA
VDD = 3.465 V, VO = 0.4 V 27 49
COOutput capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF
ZO
Out
p
ut im
p
edance
High state VO = 0.5 VDD, VO/IOH 12 31 55
Z
O
O
u
tp
u
t
impedance
Low state VO = 0.5 VDD, VO/IOL 12 24 55
All typical values are measured at their respective nominal VDD values.
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overshoot/undershoot GND – 0.7 V VDD + 0.7 V V
Ring back VIL – 0.1 V VIH + 0.1 V V
Stabilization time, PWR_DWN to PCIx f(CPU) = 133 MHz 0.05 3 ms
tdis3 Disable time, PWR_DWN to PCIx f(CPU) = 133 MHz 50 ns
Stabilization time, PWR_DWN to CPUx f(CPU) = 133 MHz 0.03 3 ms
tdis4 Disable time, PWR_DWN to CPUx f(CPU) = 133 MHz 50 ns
Stabilization time
After SEL1, SEL0 3
ms
Stabili
z
ation
time
After power up 3
ms
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency , fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued)
CPUx
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 6 10 ns
tdis1 Output disable time SEL133/100 CPUx f(CPU) = 100 or 133MHz 8 10 ns
t
CPU clock period
f(CPU) = 100 MHz 10 10.04 10.2 ns
t
c
CPU
c
l
oc
k
per
i
o
d
f(CPU) = 133 MHz 7.5 7.53 7.7 ns
Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps
Duty cycle f(CPU) = 100 or 133MHz 45 55 %
tsk(o) CPU bus skew CPUx CPUx f(CPU) = 100 or 133MHz 50 175 ps
tsk(p) CPU pulse skew CPUn CPUn f(CPU) = 100 or 133MHz 2.2 ns
t(off) CPU clock to APIC clock offset, rising edge 1.5 2.8 4 ns
t(off) CPU clock to 3V66 clock offset, rising edge 0 0.75 1.5 ns
t1
Pulse duration width high
f(CPU) = 100 MHz 2.6 4.3
ns
t
w1
P
u
lse
d
u
ration
w
idth
,
high
f(CPU) = 133 MHz 1.4 3.7
ns
t2
Pulse duration width low
f(CPU) = 100 MHz 2.8 4.3
ns
t
w2
P
u
lse
d
u
ration
w
idth
,
lo
wf(CPU) = 133 MHz 1.7 4
ns
trRise time VO = 0.4 V to 2.0 V 0.4 1.5 2.2 ns
tfFall time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns
The average over any 1-µs period of time is greater than the minimum specified period.
CPU_DIV2x
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 CPU_DIV2x f(CPU) = 100 or 133MHz 6 10 ns
tdis1 Output disable time SEL133/100 CPU_DIV2x f(CPU) = 100 or 133MHz 8 10 ns
t
CPU DIV2 clock
p
eriod
f(CPU) = 100 MHz 20 20.08 20.4 ns
t
c
CPU
_
DIV2
clock
period
f(CPU) = 133 MHz 15 15.06 15.3 ns
Cycle to cycle jitter f(CPU) = 100 or 133MHz 250 ps
Duty cycle f(CPU) = 100 or 133MHz 45 55 %
tsk(o) CPU_DIV2 bus skew CPU_DIV2x CPU_DIV2x f(CPU) = 100 or 133MHz 50 175 ps
tsk(p) CPU_DIV2 pulse skew CPU_DIV2n CPU_DIV2n f(CPU) = 100 or 133MHz 1.6 ns
t1
Pulse duration width high
f(CPU) = 100 MHz 7.1
ns
t
w1
P
u
lse
d
u
ration
w
idth
,
high
f(CPU) = 133 MHz 4.7
ns
t2
Pulse duration width low
f(CPU) = 100 MHz 7.3 8.9
ns
t
w2
P
u
lse
d
u
ration
w
idth
,
lo
wf(CPU) = 133 MHz 5 6.6
ns
trRise time VO = 0.4 V to 2.0 V 0.4 1.4 2 ns
tfFall time VO = 0.4 V to 2.0 V 0.4 1.3 1.8 ns
The average over any 1-µs period of time is greater than the minimum specified period.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued)
APIC
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 APICx f(APIC) = 16.67 MHz 6 10 ns
tdis1 Output disable time SEL133/100 APICx f(APIC) = 16.67 MHz 8 10 ns
tcAPIC clock periodf(APIC) = 16.67 MHz 60 60.24 60.6 ns
Cycle to cycle jitter f(CPU) = 100 or 133 MHz 400 ps
Duty cycle f(APIC) = 16.67 MHz 45 55 %
tsk(o) APIC bus skew APICx APICx f(APIC) = 16.67 MHz 30 100 ps
tsk(p) APIC pulse skew APICn APICn f(APIC) = 16.67 MHz 3 ns
t(off) APIC clock to CPU clock offset,
rising edge APICx CPUx –1.5 –4 ns
tw1 Pulse duration width, high f(APIC) = 16.67 MHz 25.5 28 ns
tw2 Pulse duration width, low f(APIC) = 16.67 MHz 25.3 29.2 ns
trRise time VO = 0.4 V to 2 V 0.4 1.6 2.1 ns
tfFall time VO = 0.4 V to 2 V 0.4 1.2 1.7 ns
The average over any 1-µs period of time is greater than the minimum specified period.
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C
3V66
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 3V66x f(3V66) = 66 MHz 6 10 ns
tdis1 Output disable time SEL133/100 3V66x f(3V66) = 66 MHz 8 10 ns
tc3V66 clock periodf(3V66) = 66 MHz 15 15.06 15.3 ns
Cycle to cycle jitter f(CPU) = 100 or 133 MHz 400 ps
Duty cycle f(3V66) = 66 MHz 45 55 %
tsk(o) 3V66 bus skew 3V66x 3V66x f(3V66) = 66 MHz 50 150 ps
tsk(p) 3V66 pulse skew 3V66n 3V66n f(3V66) = 66 MHz 2.6 ns
t(off) 3V66 clock to CPU clock offset 3V66x CPUx 0 –0.75 –1.5 ns
t(off) 3V66 clock to PCI clock offset, rising edge 1.2 2.1 3 ns
tw1 Pulse duration width, high f(3V66) = 66 MHz 5.2 ns
tw2 Pulse duration width, low f(3V66) = 66 MHz 5 ns
trRise time VO = 0.4 V to 2 V 0.5 1.5 2 ns
tfFall time VO = 0.4 V to 2 V 0.5 1.5 2 ns
The average over any 1-µs period of time is greater than the minimum specified period.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
48MHz
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 48MHz f(48MHz) = 48 MHz 6 10 ns
tdis1 Output disable time SEL133/100 48MHz f(48MHz) = 48 MHz 8 10 ns
tc48MHz clock periodf(48MHz) = 48 MHz 20.5 20.83 21.1 ns
Cycle to cycle jitter f(CPU) = 100 or 133 MHz 500 ps
Duty cycle f(48MHz) = 48 MHz 45 55 %
tsk(p) 48MHz pulse skew 48MHz 48MHz f(48MHz) = 48 MHz 3 ns
tw1 Pulse duration width, high f(48MHz) = 48 MHz 7.8 ns
tw2 Pulse duration width, low f(48MHz) = 48 MHz 7.8 ns
trRise time VO = 0.4 V to 2 V 1 2.1 2.8 ns
tfFall time VO = 0.4 V to 2 V 1 1.9 2.8 ns
The average over any 1-µs period of time is greater than the minimum specified period.
REF
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 REFx f(REF) = 14.318 MHz 6 10 ns
tdis1 Output disable time SEL133/100 REFx f(REF) = 14.318 MHz 8 10 ns
tcREF clock periodf(REF) = 14.318 MHz 69.84 ns
Cycle to cycle jitter f(CPU) = 100 or 133 MHz 700 ps
Duty cycle f(REF) = 14.318 MHz 45 55 %
tsk(o) REF bus skew REFx REFx f(REF) = 14.318 MHz 150 250 ps
tsk(p) REF pulse skew REFn REFn f(REF) = 14.318 MHz 2 ns
tw1 Pulse duration width, high f(REF) = 14.318 MHz 26.2 32.7 ns
tw2 Pulse duration width, low f(REF) = 14.318 MHz 26.2 31.2 ns
trRise time VO = 0.4 V to 2 V 1 2 2.8 ns
tfFall time VO = 0.4 V to 2 V 1 1.9 2.8 ns
The average over any 1-µs period of time is greater than the minimum specified period.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
PCI, PCI_F
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
ten1 Output enable time SEL133/100 PCIx f(PCI) = 33 MHz 6 10 ns
tdis1 Output disable time SEL133/100 PCIx f(PCI) = 33 MHz 8 10 ns
tcPCIx clock periodf(PCI) = 33 MHz 30 30.12 30.5 ns
Cycle to cycle jitter f(CPU) = 100 or 133 MHz 300 ps
Duty cycle f(PCI) = 33 MHz 45 55 %
tsk(o) PCIx bus skew PCIx PCIx f(PCI) = 33 MHz 70 300 ps
tsk(p) PCIx pulse skew PCIn PCIn f(PCI) = 33 MHz 4 ns
t(off) PCIx clock to 3V66 clock offset –1.2 –3 ns
tw1 Pulse duration width, high f(PCI) = 33 MHz 12 ns
tw2 Pulse duration width, low f(PCI) = 33 MHz 12 ns
trRise time VO = 0.4 V to 2 V 0.5 1.6 2 ns
tfFall time VO = 0.4 V to 2 V 0.5 1.5 2 ns
The average over any 1-µs period of time is greater than the minimum specified period.
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL = 500
LOAD CIRCUIT for tpd and tsk
From Output
Under Test CL
(see Note A)
RL = 500 S1 VO_REF
OPEN
GND tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VO_REF
GND
TEST S1
ÎÎ
tw
Input
3 V
0 V
VIH_REF
VT_REF
VIL_REF
From Output
Under Test Test
Point
CL
(see Note A)
LOAD CIRCUIT FOR tr and tfVOLTAGE WAVEFORMS
0 V
Output
W aveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
VOH
VOL
VDD
VT_REF
VT_REF
VT_REF
tPZL tPLZ
tPHZ
tPZH
VT_REF VOH – 0.3 V
VOL + 0.3 V
3 V
0 V
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
Enable
(high-level
enabling)
tr
3 V
0 V
VIH_REF
VT_REF
VIL_REF
VT_REF VT_REF
tPLH tPHL
tf
tw_high
tw_low
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. CL = 20 pF (CPUx, APICx, 48MHz, REF), CL = 30 pF (PCIx, 3V66)
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
v
14.318 MHz, ZO = 50 , tr 2.5 ns,
tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
PARAMETER 3.3-V INTERFACE 2.5-V INTERFACE UNIT
VIH_REF High-level reference voltage 2.4 2 V
VIL_REF Low-level reference voltage 0.4 0.4 V
VT_REF Input Threshold reference voltage 1.5 1.25 V
VO_REF Off-state reference voltage 6 4.6 V
Figure 3. Load Circuit and Voltage Waveforms
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tsk(o)
VT_REF
CPUx or PCIx Clock
3V66 or CPUx
CPUx or PCIx Clock
VT_REF
VT_REF
t(low) t(high)
tc
tsk(p)
+Ť
tPLH–tPHL
Ť
Duty Cycle
+
t(low or high)
tc
100
VT_REF
t(off) [3V66 to PCIx]
t(off) [CPUx to APICx]
t(off) [CPUx to 3V66]
3V66, PCIx, or APICx
Figure 4. Waveforms for Calculation of Skew, Offset, and Jitter
CPU
(internal)
PCI
(internal)
CPU_STOP
PCI_STOP
PWR_DOWN
PCI_F
(external)
CPU
(external)
3V66
(external)
Figure 5. CPU_STOP Timing
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CPU
(internal)
PCI
(internal)
CPU_STOP
PCI_STOP
PWR_DOWN
PCI_F
(external)
PCI
(external)
Figure 6. PCI_STOP Timing
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇ
CPU
(internal)
PCI
(internal)
PWR_DOWN
PCI
(external)
CPU
(external)
VCO
CRYSTAL
NOTE A: Shaded sections on the VCO and Crystal waveforms indicate that the VCO and crystal oscillators are active and there is a valid clock.
Figure 7. Power-Down Timing
CDC925
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS633 – JULY 28, 1999
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/D 08/97
48-PIN SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.006 (0,15) NOM
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.012 (0,305)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–8°
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
E. Falls within JEDEC MO-118
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDC925DL ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDC925DLG4 ACTIVE SSOP DL 56 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2008
Addendum-Page 1
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