RF1S45N06LESM - Intersil Corporation

1CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

PSPICE® is a registered trademark of MicroSim Corporation.

RFP45N06LE, RF1S45N06LESM

45A, 60V, 0.028 Ohm, Logic Level

N-Channel Power MOSFETs

These are N-Channel enhancement mode power MOSFETs

manufactured using the latest manufacturing process

technology. This process, which uses feature sizes

approaching those of LSI circuits, gives optimum utilization

of silicon, resulting in outstanding performance. They were

designed for use in applications such as switching

regulators, switching converters, motor drivers, and relay

drivers. These transistors can be operated directly from

integrated circuits.

Formerly developmental type TA49177.

Features

• 45A, 60V

•r

DS(ON) = 0.028Ω

• Temperature Compensating PSPICE® Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• 175oC Operating Temperature

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

Ordering Information

PART NUMBER PACKAGE BRAND

RFP45N06LE TO-220AB FP45N06L

RF1S45N06LESM TO-263AB F45N06LE

NOTE: Whenordering, use the entire part number.Addthesuffix9Ato

obtain the TO-263AB variant in tape and reel i.e., RF1S45N06LESM9A.

JEDEC T O-220AB JEDEC TO-263AB

GATE

DRAIN (FLANGE)

SOURCE

DRAIN

(FLANGE)

GATE

SOURCE

Data Sheet October 1999 File Number 4076.2

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed RFP45N06LE, RF1S45N06LESM UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 60 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 45

Refer to Peak Current Curve A

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

0.95 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ= 25oC to 150oC.

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 13) 60 - - V

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 12) 1 - 3 V

Zero Gate Voltage Drain Current IDSS VDS = 55V, VGS = 0V - - 1 µA

VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±10V - - 10 µA

Drain to Source On Resistance (Note 2) rDS(ON) ID = 45A, VGS = 5V (Figure 11) - - 0.028 Ω

Turn-On Time tON VDD = 30V, ID = 45A, RL = 0.67Ω,

VGS = 5V, RGS = 2.5Ω

(Figures 10, 18, 19)

- - 215 ns

Turn-On Delay Time td(ON) -20-ns

Rise Time tr- 150 - ns

Turn-Off Delay Time td(OFF) -55-ns

Fall Time tf-90-ns

Turn-Off Time tOFF - - 185 ns

Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 48V,

ID = 45A,

RL = 1.07Ω

(Figures 20, 21)

- 107 135 nC

Gate Charge at 5V Qg(5) VGS = 0V to 5V - 58 75 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 2.4 3.0 nC

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz

(Figure 14) - 2150 - pF

Output Capacitance COSS - 640 - pF

Reverse Transfer Capacitance CRSS - 240 - pF

Thermal Resistance Junction to Case RθJC - - 1.05 oC/W

Thermal Resistance Junction to Ambient RθJA TO-220, and TO-263 - - 80 oC/W

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 45A - - 1.5 V

Diode Reverse Recovery Time trr ISD = 45A, dISD/dt = 100A/µs - - 155 ns

NOTES:

2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

RFP45N06LE, RF1S45N06LESM

Typical Performance Curves Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150

025 50 75 100 125 150

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC) 175

t, RECTANGULAR PULSE DURATION (s)

10-5 10-3 10-2 10-1 100

0.01

0.1

10-4 101

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

SINGLE PULSE

ZθJC, NORMALIZED

THERMAL IMPEDANCE

0.5

0.2

0.1

0.05

0.01

0.02

VDS, DRAIN TO SOURCE VOLTAGE (V)

1 10 100

100

ID, DRAIN CURRENT (A)

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

100µs

10ms

1ms

500

200

TC = 25oC

TJ = MAX RATED

t, PULSE WIDTH (s)

500

10-5 10-4 10-3 10-2 10-1 100101

IDM, PEAK CURRENT CAPABILITY (A)

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 5V

THERMAL IMPEDANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 10V

100

TC = 25oC

RFP45N06LE, RF1S45N06LESM

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

100

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

STARTING TJ = 150oC

STARTING TJ = 25oC

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

1 10 1000.01 0.1

200

0 1.5 3.0 4.5 6.0

100

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 3V

VGS = 5V

VGS = 10V

VGS = 2.5V

VGS = 4V

PULSE DURATION = 80µs

TC = 25oC

DUTY CYCLE = 0.5% MAX

VGS = 3.5V

0 3.0 4.5 6.01.5

100

175oC

IDS(ON), DRAIN TO SOURCE CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

-55oC25oC

VDD = 15V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

03.0

VGS, GATE TO SOURCE VOLTAGE (V)

rDS(ON), DRAIN TO SOURCE

2.0 3.5 4.5 5.0

ID = 45A

ID = 11.25A

ID = 22.5A

4.02.5

ID = 90A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

ON RESISTANCE (mΩ)

200

20 30 40 500

500

400

300

100

010

SWITCHING TIME (ns)

RGS, GATE TO SOURCE RESISTANCE (Ω)

600

td(OFF)

td(ON)

VDD = 30V, ID = 45A, RL= 0.67Ω

0.5

1.0

1.5

2.0

-80 -40 0 40 80 120 160

NORMALIZED ON RESISTANCE

TJ, JUNCTION TEMPERATURE (oC)

2.5

200

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 5V, ID = 45A

RFP45N06LE, RF1S45N06LESM

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR

CONSTANT GATE CURRENT

Test Circuits and Waveforms

FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

-80 -40 0 40 80 120 160

NORMALIZED GATE

THRESHOLD VOLTAGE

TJ, JUNCTION TEMPERATURE (oC) 200

1.2

0.8

0.6

0.4

1.0

VGS = VDS, ID = 250µA1.2

1.0

0.9

0.8-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

200

1.1

ID = 250µA

2500

2000

1000

00 5 10 15 20 25

C, CAPACITANCE (pF)

CRSS

1500

CISS

COSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

500

3000

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

20IGREF()

IG ACT()

----------------------t, TIME (µs) 80IGREF()

IGACT()

----------------------

5.00

3.75

2.50

1.25

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS, GATE TO SOURCE VOLTAGE (V)

RL = 1.3Ω

IG(REF) = 1.3mA

VGS = 5V

VDD = BVDSS

VDD = 0.75 BVDSS

VDD = 0.50 BVDSS

VDD = 0.25 BVDSS

PLATEAU VOLTAGES IN

DESCENDING ORDER:

VDD = BVDSS VDD = BVDSS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

RFP45N06LE, RF1S45N06LESM

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS

Test Circuits and Waveforms (Continued)

VGS

RGS

DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10) OR Qg(5)

VGS = 5V FOR

Qg(TOT)

VGS = 20V

VDS

VGS

Ig(REF)

VGS = 1V FOR

L2 DEVICES

VGS = 10V

VGS = 10V FOR

L2 DEVICES

RFP45N06LE, RF1S45N06LESM

PSPICE Electrical Model

SUBCKT 45N06LE 2 1 3 ; rev 10/25/95

CA 12 8 3.73e-9

CB 15 14 3.73e-9

CIN 6 8 2.08e-9

DBODY 7 5 DBODYMOD

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 66.5

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRAIN 2 5 4.0e-9

LGATE 1 9 6.0e-9

LSOURCE 3 7 3.0e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 3.75e-3

RGATE 9 20 1.0

RLDRAIN 2 5 40

RLGATE 1 9 60

RLSOURCE 3 7 30

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 6.15e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))}

.MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47)

.MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7)

.MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10)

.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0)

.MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1)

.MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0)

.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5)

.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6)

.MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5)

.MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6)

.MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.3 VOFF= -2.5)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -5.3)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.4 VOFF= 0.5)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.4)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RFP45N06LE, RF1S45N06LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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RFP45N06LE, RF1S45N06LESM