INTEGRATED CIRCUITS DATA SHEET 74LVC374A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Product specification Supersedes data of 1998 July 29 2003 May 14 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A FEATURES DESCRIPTION * 5 V tolerant inputs/outputs; for interfacing with 5 V logic The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. * Wide supply voltage range from 1.2 to 3.6 V * Inputs accept voltages up to 5.5 V Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. * CMOS low power consumption * Direct interface with TTL levels * High-impedance when VCC = 0 V * 8-bit positive edge-triggered register The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. * Independent register and 3-state buffer operation * Complies with JEDEC standard no. 8-1A * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. * Specified from -40 to +85 C and -40 to +125 C. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74LVC374A is functionally identical to the 74LVC574A, but the 74LVC574A has a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL PARAMETER tPHL/tPLH propagation delay CP to Qn fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per gate CONDITIONS CL = 50 pF; VCC = 3.3 V VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 May 14 2 TYPICAL UNIT 2.7 ns 100 MHz 4.0 pF 15 pF Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A FUNCTION TABLE See note 1. INPUT OE CP Dn L l L L Load and read register Load register and disable outputs OUTPUT INTERNAL FLIP-FLOP OPERATING MODE Qn L h H H H l L Z H h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC374AD -40 to +125 C 20 SO20 plastic SOT163-1 74LVC374ADB -40 to +125 C 20 SSOP20 plastic SOT339-1 74LVC374APW -40 to +125 C 20 TSSOP20 plastic SOT360-1 74LVC374ABQ -40 to +125 C 20 DHVQFN20 plastic SOT764-1 PINNING PIN PIN SYMBOL DESCRIPTION SYMBOL DESCRIPTION 11 CP clock input (LOW-to-HIGH, edge-triggered) 1 OE output enable input (active LOW) 2 Q0 3-state flip-flop output 12 Q4 3-state flip-flop output 3 D0 data input 13 D4 data input D5 data input 4 D1 data input 14 5 Q1 3-state flip-flop output 15 Q5 3-state flip-flop output 6 Q2 3-state flip-flop output 16 Q6 3-state flip-flop output D6 data input 7 D2 data input 17 8 D3 data input 18 D7 data input 9 Q3 3-state flip-flop output 19 Q7 3-state flip-flop output 10 GND ground (0 V) 20 VCC supply voltage 2003 May 14 3 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state handbook, halfpage handbook, halfpage OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 16 Q6 Q1 5 74LVC374A OE VCC 1 20 Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 374 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP GND(1) Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 MNA194 Top view 10 11 GND CP MNB001 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN20. Fig.1 Pin configuration SO20 and (T)SSOP20. handbook, halfpage 1 11 3 EN 11 handbook, halfpage C1 3 4 2 1D 7 4 5 8 7 6 13 8 9 14 13 17 12 18 14 15 17 16 18 19 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 5 6 9 12 15 16 19 OE 1 MNA891 MNA196 Fig.3 Logic symbol. 2003 May 14 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A handbook, halfpage 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 FF1 to FF8 3-STATE OUTPUTS Q4 12 11 CP 1 OE MNA892 Fig.5 Functional diagram. D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA893 Fig.6 Logic diagram. 2003 May 14 5 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V in free air -40 +125 C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage -0.5 +6.5 V IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 mA VO output voltage output HIGH or LOW state; note 1 -0.5 output 3-state; note 1 -0.5 VCC + 0.5 V +6.5 V IO output source or sink current - 50 mA ICC, IGND VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation - 500 mW VO = 0 to VCC Tamb = -40 to +125 C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 2003 May 14 6 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +85 C; note 1 VIH VIL LOW-level input voltage VOH HIGH-level output voltage VOL 1.2 VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V IO = -100 A 2.7 to 3.6 VCC - 0.2 - - V IO = -12 mA 2.7 VCC - 0.5 - - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA 3.0 VCC - 0.8 - - V IO = 100 A 2.7 to 3.6 - - 0.20 V IO = 12 mA 2.7 - - 0.40 V IO = 24 mA 3.0 - - 0.55 V HIGH-level input voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - 0.1 5 A Ioff power-off leakage supply VI or VO = 5.5 V 0.0 - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 10 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.7 to 3.6 - 5 500 A 2003 May 14 7 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = -40 to +125 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 1.2 VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V VI = VIH or VIL IO = -100 A 2.7 to 3.6 VCC - 0.3 - - V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA 3.0 VCC - 1 - - V IO = 100 A 2.7 to 3.6 - - 0.3 V IO = 12 mA 2.7 - - 0.6 V IO = 24 mA 3.0 - - 0.8 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND 3.6 - - 20 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - - 20 A Ioff power-off leakage supply VI or VO = 5.5 V 0.0 - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - - 40 A ICC additional quiescent supply VI = VCC - 0.6 V; current per input pin IO = 0 2.7 to 3.6 - - 5000 A Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2003 May 14 8 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORM TYP. MAX. UNIT VCC (V) Tamb = -40 to +85 C; note1 tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th fmax tsk(0) propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock frequency skew 2003 May 14 Figs 7 and 10 Figs 8 and 10 Figs 8 and 10 Fig.7 Fig.9 Fig.9 Fig.7 note 2 9 1.2 - 16 - ns 2.7 1.5 2.9 8.0 ns 3.0 to 3.6 1.5 2.7 7.0 ns 1.2 - 19 - ns 2.7 1.5 4.1 8.5 ns 3.0 to 3.6 1.5 3.4 7.5 ns 1.2 - 8.0 - ns 2.7 1.5 2.7 7.0 ns 3.0 to 3.6 1.5 2.4 6.0 ns 1.2 - - - ns 2.7 3.0 - - ns 3.0 to 3.6 3.0 1.5 - ns 1.2 - - - ns 2.7 2.0 - - ns 3.0 to 3.6 2.0 0 - ns 1.2 - - - ns 2.7 1.5 - - ns 3.0 to 3.6 1.5 0.6 - ns 1.2 - - - MHz 2.7 80 - - MHz 3.0 to 3.6 100 - - MHz 3.0 to 3.6 - - 1.0 ns Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORM TYP. MAX. UNIT VCC (V) Tamb = -40 to +125 C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th fmax tsk(0) propagation delay CP to Qn Figs 7 and 10 3-state output enable time OE to Qn Figs 8 and 10 3-state output disable time OE to Qn Figs 8 and 10 clock pulse width HIGH or LOW Fig.7 set-up time Dn to CP hold time Dn to CP maximum clock frequency skew Fig.9 Fig.9 Fig.7 note 2 1.2 - - - ns 2.7 1.5 - 10.0 ns 3.0 to 3.6 1.5 - 9.0 ns 1.2 - - - ns 2.7 1.5 - 11.0 ns 3.0 to 3.6 1.5 - 9.5 ns 1.2 - - - ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 7.5 ns 1.2 - - - ns 2.7 4.5 - - ns 3.0 to 3.6 4.5 - - ns 1.2 - - - ns 2.7 2.0 - - ns 3.0 to 3.6 2.0 - - ns 1.2 - - - ns 2.7 1.5 - - ns 3.0 to 3.6 1.5 - - ns 1.2 - - - MHz 2.7 64 - - MHz 3.0 to 3.6 80 - - MHz 3.0 to 3.6 - - 1.5 ns Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 May 14 10 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A AC WAVEFORMS 1/f max handbook, full pagewidth VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL MNA894 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.7 Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. 2003 May 14 11 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A VI handbook, full pagewidth OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA644 VM = 1.5 V at VCC 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.1 VCC at VCC < 2.7 V; VY = VOH - 0.3 V at VCC 2.7 V; VY = VOH - 0.1 VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.8 3-state enable and disable times. VI handbook, full pagewidth VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL MNA202 VM = 1.5 V at VCC 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig.9 Data setup and hold times for the Dn input to the CP input. 2003 May 14 12 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state S1 handbook, full pagewidth VCC PULSE GENERATOR VI 500 VO 74LVC374A 2 x VCC open GND D.U.T. CL = 50 pF RT 500 MNA896 SWITCH POSITION TEST S1 VCC VI tPLH/tPHL open tPLZ/tPZL 2 x VCC < 2.7 V VCC tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. 2003 May 14 13 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2003 May 14 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 14 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 2003 May 14 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 15 o Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2003 May 14 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 16 o Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2003 May 14 17 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferably be kept: Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. * below 220 C for all the BGA packages and packages with a thickness 2.5mm and packages with a thickness <2.5 mm and a volume 350 mm3 so called thick/large packages Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. * below 235 C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages. Wave soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2003 May 14 74LVC374A 18 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 May 14 19 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 74LVC374A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 May 14 20 Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state NOTES 2003 May 14 21 74LVC374A Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state NOTES 2003 May 14 22 74LVC374A Philips Semiconductors Product specification Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state NOTES 2003 May 14 23 74LVC374A Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 (c) Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/02/pp24 Date of release: 2003 May 14 Document order number: 9397 750 10552