DATA SH EET
Product specification
Supersedes data of 1998 July 29 2003 May 14
INTEGRATED CIRCUITS
74LVC374A
Octal D-type flip-flop with 5 V
tolerant inputs/outputs; positive
edge-trigger; 3-state
2003 May 14 2
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
FEATURES
•5 V tolerant inputs/outputs; for interfacing with 5 V logic
•Wide supply voltage range from 1.2 to 3.6 V
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•High-impedance when VCC =0V
•8-bit positive edge-triggered register
•Independent register and 3-state buffer operation
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC374A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC374A is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus-oriented applications. A clock input (CP)
and an outputs enable input (OE) are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is
availableattheoutputs.Whenpin OEisHIGH,theoutputs
go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
The 74LVC374A is functionally identical to the
74LVC574A, but the 74LVC574A has a different pin
arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay CP to Qn CL= 50 pF; VCC = 3.3 V 2.7 ns
fmax maximum clock frequency 100 MHz
CIinput capacitance 4.0 pF
CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 15 pF
2003 May 14 3
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑= LOW-to-HIGH clock transition.
ORDERING INFORMATION
OPERATING MODE INPUT INTERNAL
FLIP-FLOP OUTPUT
OE CP Dn Qn
Load and read
register L↑lLL
L↑hHH
Load register and
disable outputs H↑lLZ
H↑hHZ
TYPE NUMBER PACKAGE
TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE
74LVC374AD −40 to +125 °C 20 SO20 plastic SOT163-1
74LVC374ADB −40 to +125 °C 20 SSOP20 plastic SOT339-1
74LVC374APW −40 to +125 °C 20 TSSOP20 plastic SOT360-1
74LVC374ABQ −40 to +125 °C 20 DHVQFN20 plastic SOT764-1
PINNING
PIN SYMBOL DESCRIPTION
1OE output enable input (active LOW)
2 Q0 3-state flip-flop output
3 D0 data input
4 D1 data input
5 Q1 3-state flip-flop output
6 Q2 3-state flip-flop output
7 D2 data input
8 D3 data input
9 Q3 3-state flip-flop output
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH,
edge-triggered)
12 Q4 3-state flip-flop output
13 D4 data input
14 D5 data input
15 Q5 3-state flip-flop output
16 Q6 3-state flip-flop output
17 D6 data input
18 D7 data input
19 Q7 3-state flip-flop output
20 VCC supply voltage
PIN SYMBOL DESCRIPTION
2003 May 14 4
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
handbook, halfpage
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
CP
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
374
MNA194
Fig.1 Pin configuration SO20 and (T)SSOP20.
handbook, halfpage
1
2
3
4
5
6
7
8
9
Q0
D0
D1
Q1
Q2
D2
D3
Q3
19
18
17
16
15
14
13
12
Q7
D7
D6
Q6
Q5
D5
D4
Q4
20
OE VCC
10 11
GND
Top view CP
GND(1)
MNB001
Fig.2 Pin configuration DHVQFN20.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA196
19
16
15
12
9
6
5
11 C1
1EN
1D 2
18
17
14
13
8
7
4
3
Fig.3 Logic symbol.
handbook, halfpage
MNA891
D0
D1
D2
D3
D4
D5
D6
D7 OE
CP Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.4 Logic symbol (IEEE/IEC).
2003 May 14 5
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
handbook, halfpage
MNA892
3-STATE
OUTPUTS
FF1
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
18
11
1
17
14
13
8
7
4
3
Fig.5 Functional diagram.
MNA893
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF1
Q
CP
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF7
Q
CP
D
FF8
Q
CP
OE
Q5
D5
Q6
D6
Q7
D7
Fig.6 Logic diagram.
2003 May 14 6
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH or LOW state 0 VCC V
output 3-state 0 5.5 V
Tamb operating ambient temperature in free air −40 +125 °C
tr, tfinput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V
output 3-state; note 1 −0.5 +6.5 V
IOoutput source or sink current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 to +125 °C; note 2 −500 mW
2003 May 14 7
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C; note 1
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.2 −−V
I
O
=−12 mA 2.7 VCC −0.5 −−V
I
O
=−18 mA 3.0 VCC −0.6 −−V
I
O
=−24 mA 3.0 VCC −0.8 −−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.20 V
IO=12mA 2.7 −−0.40 V
IO=24mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 V or GND 3.6 −±0.1 ±5µA
Ioff power-off leakage supply VIor VO= 5.5 V 0.0 −±0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 3.6 −0.1 10 µA
∆ICC additionalquiescentsupply
current per input pin VI=V
CC −0.6 V;
IO=0 2.7 to 3.6 −5 500 µA
2003 May 14 8
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
I
O
=−12 mA 2.7 VCC −0.65 −−V
I
O
=−18 mA 3.0 VCC −0.75 −−V
I
O
=−24 mA 3.0 VCC −1−−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO=12mA 2.7 −−0.6 V
IO=24mA 3.0 −−0.8 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −−±20 µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 V or GND 3.6 −−±20 µA
Ioff power-off leakage supply VIor VO= 5.5 V 0.0 −−±20 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 3.6 −−40 µA
∆ICC additionalquiescentsupply
current per input pin VI=V
CC −0.6 V;
IO=0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2003 May 14 9
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns; CL= 50 pF; RL= 500 Ω.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORM VCC (V)
Tamb =−40 to +85 °C; note1
tPHL/tPLH propagation delay CP to Qn Figs 7 and 10 1.2 −16 −ns
2.7 1.5 2.9 8.0 ns
3.0 to 3.6 1.5 2.7 7.0 ns
tPZH/tPZL 3-state output enable time
OE to Qn Figs 8 and 10 1.2 −19 −ns
2.7 1.5 4.1 8.5 ns
3.0 to 3.6 1.5 3.4 7.5 ns
tPHZ/tPLZ 3-state output disable time
OE to Qn Figs 8 and 10 1.2 −8.0 −ns
2.7 1.5 2.7 7.0 ns
3.0 to 3.6 1.5 2.4 6.0 ns
tWclock pulse width HIGH or LOW Fig.7 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 3.0 1.5 −ns
tsu set-up time Dn to CP Fig.9 1.2 −−−ns
2.7 2.0 −−ns
3.0 to 3.6 2.0 0 −ns
thhold time Dn to CP Fig.9 1.2 −−−ns
2.7 1.5 −−ns
3.0 to 3.6 1.5 0.6 −ns
fmax maximum clock frequency Fig.7 1.2 −−−MHz
2.7 80 −−MHz
3.0 to 3.6 100 −−MHz
tsk(0) skew note 2 3.0 to 3.6 −−1.0 ns
2003 May 14 10
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay CP to Qn Figs 7 and 10 1.2 −−−ns
2.7 1.5 −10.0 ns
3.0 to 3.6 1.5 −9.0 ns
tPZH/tPZL 3-state output enable time
OE to Qn Figs 8 and 10 1.2 −−−ns
2.7 1.5 −11.0 ns
3.0 to 3.6 1.5 −9.5 ns
tPHZ/tPLZ 3-state output disable time
OE to Qn Figs 8 and 10 1.2 −−−ns
2.7 1.5 −9.0 ns
3.0 to 3.6 1.5 −7.5 ns
tWclock pulse width HIGH or LOW Fig.7 1.2 −−−ns
2.7 4.5 −−ns
3.0 to 3.6 4.5 −−ns
tsu set-up time Dn to CP Fig.9 1.2 −−−ns
2.7 2.0 −−ns
3.0 to 3.6 2.0 −−ns
thhold time Dn to CP Fig.9 1.2 −−−ns
2.7 1.5 −−ns
3.0 to 3.6 1.5 −−ns
fmax maximum clock frequency Fig.7 1.2 −−−MHz
2.7 64 −−MHz
3.0 to 3.6 80 −−MHz
tsk(0) skew note 2 3.0 to 3.6 −−1.5 ns
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORM VCC (V)
2003 May 14 11
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
AC WAVEFORMS
handbook, full pagewidth
MNA894
CP input
Qn output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Fig.7 Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the
maximum clock pulse frequency.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
2003 May 14 12
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
handbook, full pagewidth
MNA644
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.8 3-state enable and disable times.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VX=V
OL + 0.3 V at VCC ≥2.7 V;
VX=V
OL + 0.1 VCC at VCC < 2.7 V;
VY=V
OH −0.3 V at VCC ≥2.7 V;
VY=V
OH −0.1 VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load.
handbook, full pagewidth
MNA202
GND
GND
thth
tsu
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
Dn input
Fig.9 Data setup and hold times for the Dn input to the CP input.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
2003 May 14 13
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA896
D.U.T.
CL =
RT500 Ω
500 Ω
PULSE
GENERATOR
S1
Fig.10 Load circuitry for switching times.
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
SWITCH POSITION
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
VCC VI
< 2.7 V VCC
2.7 to 3.6 V 2.7 V
2003 May 14 14
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
2003 May 14 15
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
2003 May 14 16
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
2003 May 14 17
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
2003 May 14 18
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsight to a complextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitisnotsuitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing,stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
•below 220 °C for all the BGA packages and packages
with a thickness ≥2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
•below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2003 May 14 19
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailed information onthe BGA packagesreferto the
“(LF)BGAApplication Note
”(AN01026);order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable
2003 May 14 20
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat any other conditionsabovethosegiven in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2003 May 14 21
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
NOTES
2003 May 14 22
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
NOTES
2003 May 14 23
Philips Semiconductors Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state 74LVC374A
NOTES
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a world wide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 613508/02/pp24 Date of release: 2003 May 14 Document order number: 9397 750 10552
