74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2
February 2011
74AC14, 74ACT14
Hex Inverter with Schmitt Trigger Input
Features
■ICC reduced by 50%
■Outputs source/sink 24mA
■74ACT14 has TTL-compatible inputs
General Description
The 74AC14 and 74ACT14 contain six inverter gates
each with a Schmitt trigger input. They are capable of
transforming slowly changing input signals into sharply
defined, jitter-free output signals. In addition, they have a
greater noise margin than conventional inverters.
The 74AC14 and 74ACT14 have hysteresis between the
positive-goin g and negative-going input thresholds (typi-
cally 1.0V) which is determined internally by transistor
ratios and is essentially insensitive to temperature and
supply voltage variations.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering nu mber.
Order
Number Package
Number Package Descripti on
74AC14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 2
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Function Table
Pin Names Description
InInputs
OnOutputs
Input Output
AO
LH
HL
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 3
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operati on. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
VCC Supply Voltage –0.5V to +7.0V
IIK DC Input Diode Current
VI –0.5V –20mA
VI VCC + 1.5 +20mA
VIDC Input Voltage –0.5V to VCC + 1.5V
IOK DC Output Diode Current
VO –0.5V –20mA
VO VCC + 0.5V +20mA
VODC Output Voltage –0.5V to VCC + 0.5V
IODC Output Source or Sink Current ±50mA
ICC or IGND DC VCC or Ground Current per Output Pin ±50mA
TSTG St orage Temperature –65°C to +150°C
TJJunction Temperatur e 140°C
Symbol Parameter Rating
VCC Supply Voltage
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
VIInput Voltage 0V to VCC
VOOutput Voltage 0V to VCC
TAOperati ng Temperature –40°C to +85°C
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 4
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
DC Electrical Characteristics for AC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Symbol Parameter
VCC Conditions
TA +25°C TA –40°C
to +85°C
Units(V) Typ Guaranteed Limits
VOH Minimum HIGH Level
Output V oltage 3.0 IOUT –50µA 2.99 2.9 2.9 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
3.0 IOH 12mA 2.56 2.46
4.5 IOH 24mA 3.86 3.76
5.5 IOH 24mA(1) 4.86 4.76
VOL Maximum LOW Level
Output V oltage 3.0 IOUT 50µA 0.002 0.1 0.1 V
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
3.0 IOL 12mA 0.36 0.44
4.5 IOL 24mA 0.36 0.44
5.5 IOL 24mA(1) 0.36 0.44
IIN(3) Maximum Input Leakage
Current 5.5 VI VCC, GND ±0.1 ±1.0 µA
Vt+ Maximum Positive
Threshold 3.0 TA Worst Case 2.2 2.2 V
4.5 3.2 3.2
5.5 3.9 3.9
Vt– Minimum Negative
Threshold 3.0 TA Worst Case 0.5 0.5 V
4.5 0.9 0.9
5.5 1.1 1.1
VH(MAX) Maximum Hysteresis 3.0 TA Worst Case 1.2 1.2 V
4.5 1.4 1.4
5.5 1.6 1.6
VH(MIN) Minimum Hysteresis 3.0 TA Worst Case 0.3 0.3 V
4.5 0.4 0.4
5.5 0.5 0.5
IOLD Minimum Dynamic 5.5 VOLD 1.65V Max. 75 mA
IOHD Output Current(2) 5.5 VOHD 3.85V Min. –75 mA
ICC(3) Maximum Quiescent
Supply Current 5.5 VIN VCC or GND 2.0 20.0 µA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 5
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
DC Electrical Characteristics for ACT
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter VCC
(V) Conditions
TA +25°C TA –40°C to +85°C
UnitsTyp. Guaranteed Limits
VIH Minimum HIGH Level
Input Vo ltage 4.5 VOUT 0.1V or
VCC – 0.1V 1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
VIL Maximum LOW Level
Input Vo ltage 4.5 VOUT 0.1V or
VCC – 0.1V 1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
VOH Minimum HIGH Level
Output Voltage 4.5 IOUT –50µA 4.49 4.34 4.4 V
5.5 5.49 5.4 5.4
4.5 VIN VIL or VIH,
IOH –24mA 3.86 3.76
5.5 VIN VIL or VIH,
IOH –24mA(4) 4.86 4.76
VOL Maximum LOW Level
Output Voltage 4.5 IOUT 50µA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
4.5 VIN VIL or VIH,
IOL 24mA 0.36 0.44
5.5 VIN VIL or VIH,
IOL 24mA(4) 0.36 0.44
IIN Maximum Input
Leakage Current 5.5 VI VCC, GND ±0.1 ±1.0 µA
VH(MAX) Maximum Hysteresis 4.5 TA Worst Case 1.4 1.4 V
5.5 1.6 1.6
VH(MIN) Minimum Hysteresis 4.5 TA Worst Case 0.4 0.4 V
5.5 0.5 0.5
Vt+ Maximum Positive
Threshold 4.5 TA Worst Case 2.0 2.0 V
5.5 2.0 2.0
Vt– Minimum Negative
Threshold 4.5 TA Worst Case 0.8 0.8 V
5.5 0.8 0.8
ICCT Maximum ICC/Input 5.5 VI VCC – 2.1V 0.6 1.5 mA
IOLD Minimum Dynamic
Output Curre n t(5) 5.5 VOLD 1.65V Max. 75 mA
IOHD 5.5 VOHD 3.85V Min. –75 mA
ICC Maximum Quiescent
Supply Current 5.5 VIN VCC or GND 2.0 20.0 µA
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 6
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
AC Electrical Characteristics for AC
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
Note:
7. Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol Parameter VCC (V)(6)
TA +25°C,
CL 50pF TA –40°C to +85°C,
CL 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay 3.3 1.5 9.5 13.5 1.5 15.0 ns
5.0 1.5 7.0 10.0 1.5 11.0
tPHL Propagation Delay 3.3 1.5 7.5 11.5 1.5 13.0 ns
5.0 1.5 6.0 8.5 1.5 9.5
Symbol Parameter VCC (V)(7)
TA +25°C,
CL 50pF TA –40°C to +85°C,
CL 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay 5.0 3.0 8.0 10.0 3.0 11.0 ns
tPHL Propagation Delay 5.0 3.0 8.0 10.0 3.0 11.0 ns
Symbol Parameter Conditions Typ Units
CIN Input Capacitance VCC OPEN 4.5 pF
CPD Power Dissipation Capacitance
AC VCC 5.0V 25.0 pF
ACT 80
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 7
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers consider ing Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semicond uctor r epresentative to ver ify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X 45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 8
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers consider ing Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semicond uctor r epresentative to ver ify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 9
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers consider ing Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semicond uctor r epresentative to ver ify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°
TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC14, 74ACT14 • Rev. 1.7.2 10
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
