10 N.C.
D1+ 1
9N.C.
D1–2
8GNDGND 3
7N.C.
D2+ 4
6N.C.
D2–5
D+
3
1
2
D–
GND
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
www.ti.com
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
2, 4-CHANNEL PROTECTION SOLUTION FOR SUPER-SPEED (6 GBPS) USB 3.0
INTERFACE
Check for Samples: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
1FEATURES
DRT PACKAGE
• Single and Dual-Pair Differential Lines to (TOP VIEW)
Protect the Differential Data and Clock Lines of
the USB3.0, eSATA, or LVD Interface
• Flow-Through Pin Mapping for the High-Speed
Lines Ensures near Zero Additional Skew Due
to Board Layout While Placing Protection Chip
Near the Connector
• Supports Data Rates in Excess of 6 Gbps DQA PACKAGE
• ESD Protection Meets or Exceeds IEC61000-4- (TOP VIEW)
2 (Level 4)
• Low Capacitance 0.05pF (IO to IO)
• 0.6 ΩDynamic Resistance
• 5-A Peak Pulse Current (per 8/20 μs Pulse)
• Industrial Temperature Range: –40°C to 85°C
• Space-Saving DRT, DQA Packages
APPLICATIONS
• Notebooks
• Set-Top Boxes
• DVD Players
• Media Players
• Portable Computers
DESCRIPTION/ORDERING INFORMATION
The TPD2EUSB30, TPD2EUSB30A, and TPD4EUSB30 provide 2 and 4 channel ESD and surge protection
solutions in space saving, flow-through packages. These devices have been designed to protect sensitive
components which are connected to ultra high-speed data and transmission lines. These devices also offer 5 A
(8/20 μs) peak pulse current ratings per IEC 61000-4-5 (lightning) specification.
The monolithic silicon technology allows matching between the differential signal pairs. The differential 0.05-pF
capacitance ensures that the signal distortion due to added ESD clamp remains minimal at high-speed
differential data transmission.
The TPD2EUSB30A offers low 4.5V dc break-down voltage. The low capacitance and break-down voltage,
coupled low dynamic resistance, make the TPD2EUSB30A a superior ESD/ surge protection device for high-
speed differential IOs based off ultra-low voltage process nodes.
The TPD2EUSB30 and TPD2EUSB30A are offered in space saving DRT (1 mm × 1 mm) package. The
TPD4EUSB30 is offered in space saving DQA (1 mm × 2.5 mm) package. These devices are characterized for
operation over ambient air temperature range of –40°C to 85°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
GND
D+
D–
GND
D2+
D2-
D1+
D1-
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
www.ti.com
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
SOT – DRT Tape and reel TPD2EUSB30DRTR 5P
–40°C to 85°C SOT – DRT Tape and reel TPD2EUSB30ADRTR 5S
SON – DQA Tape and reel TPD4EUSB30DQAR 66_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DQA: The actual top-side marking has one additional character that designates wafer fab/assembly site.
CIRCUIT DIAGRAMS
Figure 1. TPD4EUSB30 Circuit
Figure 2. TPD2EUSB30/A Circuit
TERMINAL FUNCTIONS
TERMINAL TYPE DESCRIPTION
DRT
NAME DQA PIN NO.
PIN NO.
Dx+, 1, 1,2, High-speed ESD clamp, provides ESD protection to the high-speed differential
ESD port
Dx– 2 4, 5 data lines
GND 3 3, 8 GND Ground
6, 7,
N.C. Not normally connected
9, 10
2Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
www.ti.com
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
IO voltage tolerance D+, D– pins 0 6
TAOperating free-air temperature range –40 85 °C
Tstg Storage temperature range –65 125 °C
IEC 61000-4-2 Contact Discharge D+, D– pins ±8 kV
IEC 61000-4-2 Air-Gap Discharge D+, D– pins ±8 kV
ESD protection (TPD2EUSB30/A)
IEC 61000-4-2 Air-Gap Discharge D+, D– pins ±9 kV
(TPD4EUSB30)
Peak pulse current (tp= 8/20 μs) D+, D– pins 5 A
Peak pulse power (tp= 8/20 μs) D+, D– pins 45 W
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reverse stand-off voltage, D+,D– pins to ground 5.5 V
TPD2EUSB30, TPD4EUSB30
VRWM Reverse stand-off voltage, D+,D– pins to ground 3.6 V
TPD2EUSB30A
Vclamp Clamp voltage D+,D– pins to ground, IIO = 1 A 8 V
IIO Current from IO port to supply pins VIO = 2.5 V, ID= 8 mA 0.01 0.1 μA
D+,D– pins, VIO = 2.5 V,
VDDiode forward voltage 0.6 0.8 0.95 V
lower clamp diode, ID= 8 mA
Rdyn Dynamic resistance D+,D– pins I = 1 A 0.6 Ω
CIO-IO Capacitance IO to IO D+,D– pins VIO = 2.5 V 0.05 pF
D+,D– pins (DRT) 0.7
CIO-GND Capacitance IO to GND VIO = 2.5 V pF
D1+, D1-, 0.8
D2+, D2- (DQA )
Break-down voltage, TPD2EUSB30, IIO = 1 mA 7 V
TPD4EUSB30
VBR Break-down voltage, IIO = 1 mA 4.5 V
TPD2EUSB30A
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
Voltage (V)
Current (A)
0
1
2
3
4
5
6
7
8
9
10
11
0 5 10 15 20 25 30 35 40
Measured at one IO,
the other IO open
0510 15 20 25 30 35 40 45 50
Time ( s)m
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
IPP (A)
0
5
10
15
20
25
30
35
40
45
50
55
60
PPP (W)
Current (A)
Power (W)
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
–40 25 55 85
Temperature (°C)
Leakage Current (pA)
V = 2.5 V
IO
D–
D+
5.00E-13
6.00E-13
7.00E-13
8.00E-13
9.00E-13
1.00E-12
1.10E-12
1.20E-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Capacitnace (Farads)
Voltage (V)
DRT Package
T = 25°C
A
DQA Package
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
www.ti.com
TYPICAL OPERATING CHARACTERISTICS
Figure 3. IO Capacitance vs IO Voltage Figure 4. Leakage Current vs Temperature
Figure 5. Peak Pulse Waveforms Figure 6. D+,D– Transmission Line Pulser Plot for
TPD2EUSB30 (100 ns Pulse, 10 ns Rise Time)
4Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
Time (ns)
Amplitude (V)
0 200
25 50 75 100 125 150 175
-100
20
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Time (ns)
Amplitude (V)
-20
100
0 200
-10
0
10
20
30
40
50
60
70
80
90
25 50 75 100 125 150 175
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
www.ti.com
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
TYPICAL OPERATING CHARACTERISTICS (continued)
Figure 7. IEC Clamping Waveforms (8 kV Contact) Figure 8. IEC Clamping Waveforms (–8 kV Contact)
Figure 9. Insertion Loss
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
1-mm
1-mm
GND
D+
D-
1-mm1-mm
1-mm1-mm
GND
D+
D-
TPD2EUSB30DRTR
TX+
TX-
GND
RX+
RX-
VBUS
D-
D+
GND
8-mm
USB 3.0
Host/ Controller
TX+
TX-
GND
RX+
RX-
VBUS
D-
D+
GND
USB 3.0
Host/ Controller 8-mm
1-mm
2.5-mm
1-mm1-mm
2.5-mm2.5-mm
TPD4EUSB30
D1+
D1-
GND GND
D2+
D2-
One TPD4EUSB30 & One TPD2EUSB30 to Protect USB3.0 Class A connec tor (Two Layer Routing)
Three TPD2EUSB30 to Protect USB3.0 Class A connector (One Layer Routing)
N.C.
N.C.
N.C.
N.C.
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
www.ti.com
APPLICATION INFORMATION
Layout Guide with TPDxEUSB30/A
Refer to Figure 10, the TPD2EUSB30/A are offered in space saving DRT package. The DRT is a 1mm* 1mm
package with flow-through pin-mapping for the high-speed differential lines. The TPD4EUSB30 is offered in
space saving DQA package. The DQA is a 1mm* 2.5mm package with flow-through pin-mapping for the high-
speed differential lines. It is recommended to place the package right next to the USB 3.0 connector. The GND
pin should connected to GND plane of the board through a large VIA. If a dedicated GND plane is not present
right underneath, it is recommended to route to the GND plane through a wide trace. The current associated with
IEC ESD stress can be in the range of 30Amps or higher momentarily. A good, low impedance GND path
ensures the system robustness against IEC ESD stress.
The TPDxEUSB30/A can provide system level ESD protection to the high-speed differential ports (>6 Gbps data
rate). The flow-through package offers flexibility for board routing with traces up to 15 mills wide. It allows the
differential signal pairs couple together right after they touch the ESD ports of the TPDxEUSB30/A.
Figure 10. Layout Guide with the TPDxEUSB30/A at the USB3.0 Class A Connector
TPDxEUSB30/A Eye Pattern Test
See Figure 12 for a demonstration of the TPDxEUSB30/A performance the lab set-up. Figure 11 shows a lab
board that was designed to demonstrate the degradation of the eye pattern quality with and without the
TPD2EUSB30/A in the USB 3.0 signal path. Figure 13 shows that there is only ~2 ps jitter penalty to the
differential signal when the TPD2EUSB30/A device was added in the signal path. Similar setup was employed to
measure eye pattern for the TPD4EUSB30.
6Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
Pattern Generator TPD2EUSB30 USB3.0 Receiver PHY
36” Lossy Transmission Line
Eye Pattern
Measurement Point
Pattern Generator USB3.0 Receiver PHY
36” Lossy Transmission Line
Eye Pattern
Measurement Point
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
www.ti.com
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
Figure 11. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A
Figure 12. Measurement Setup to collect the Eye Pattern on a Reference Board with TPD2EUSB30/A
Figure 13. Lab Setup for the Eye-Pattern Measurement with TPDxEUSB30/A
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
www.ti.com
Figure 14. Output Eye Diagram Without Figure 15. Output Eye Diagram with the
TPD2EUSB30/A (Figure 11 Setup, 5 Gbps Data TPD2EUSB30/A (Figure 11 Setup, 5 Gbps Data
Rate) Rate)
Figure 16. Output Eye Diagram Without the Figure 17. Output Eye Diagram with the
TPD4EUSB30 (5 Gbps Data Rate) TPD4EUSB30 (5 Gbps Data Rate)
Figure 18. TPDxEUSB30/A EVM – TPD4EUSB30 Figure 19. TPDxEUSB30/A EVM – TPD2EUSB30/A
Side Side
8Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
www.ti.com
SLVSAC2D –AUGUST 2010–REVISED AUGUST 2012
REVISION HISTORY
Changes from Original (August 2010) to Revision A Page
• Added TPS2EUSB30A part to document. ............................................................................................................................ 1
Changes from Revision A (December 2010) to Revision B Page
• Changed TOP-SIDE MARKING column in the Ordering Information Table. ........................................................................ 2
Changes from Revision B (July 2011) to Revision C Page
• Added Insertion Loss graphic to TYPICAL OPERATING CHARACTERISTICS section. .................................................... 5
Changes from Revision December 2011 (C) to Revision D Page
• Updated Dynamic Resistance value. .................................................................................................................................... 1
• Updated Dynamic Resistance value. .................................................................................................................................... 3
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30
PACKAGE OPTION ADDENDUM
www.ti.com 10-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPD2EUSB30ADRTR ACTIVE SOT DRT 3 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD2EUSB30DRTR ACTIVE SOT DRT 3 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPD4EUSB30DQAR ACTIVE SON DQA 10 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPD2EUSB30ADRTR SOT DRT 3 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3
TPD2EUSB30DRTR SOT DRT 3 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q3
TPD4EUSB30DQAR SON DQA 10 3000 180.0 8.4 1.3 2.83 0.65 4.0 8.0 Q1
TPD4EUSB30DQAR SON DQA 10 3000 179.0 8.4 1.25 2.8 0.7 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPD2EUSB30ADRTR SOT DRT 3 3000 202.0 201.0 28.0
TPD2EUSB30DRTR SOT DRT 3 3000 202.0 201.0 28.0
TPD4EUSB30DQAR SON DQA 10 3000 202.0 201.0 28.0
TPD4EUSB30DQAR SON DQA 10 3000 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2012
Pack Materials-Page 2
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