GTL2014 4-bit LVTTL to GTL transceiver Rev. 3 -- 14 June 2012 Product data sheet 1. General description The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface with a GTL-/GTL/GTL+ bus, where GTL-/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage thresholds associated with it. The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or as a LVTTL to GTL interface. The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant. The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications. GTL2014 is pin-to-pin backward compatible to the GTL2005 (labels for A port and B port are interchanged). GTL2014's Vref tracks down to 0.5 V for low voltage CPU, propagation delays are slightly longer, while GTL2005's Vref linearity degrades below 0.8 V and has shorter propagation delay. fast tPD GTL2005 GTL2014 slow tPD GTL- GTL GTL+ 002aab378 Fig 1. GTL2005/GTL2014 positioning 2. Features and benefits Operates as a 4-bit GTL-/GTL/GTL+ sampling receiver or as a LVTTL to GTL-/GTL/GTL+ driver 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input GTL input and output 3.6 V tolerant Vref adjustable from 0.5 V to VCC/2 Partial power-down permitted ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-CC101 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver Latch-up protection exceeds 500 mA per JESD78 Package offered: TSSOP14 3. Quick reference data Table 1. Quick reference data Tamb = 25 C Symbol Parameter Conditions Min Typ Max Unit tPLH LOW to HIGH propagation delay An-to-Bn; CL = 50 pF; VCC = 3.3 V - 2.8 - ns tPHL HIGH to LOW propagation delay An-to-Bn; CL = 50 pF; VCC = 3.3 V - 3.4 - ns tPLH LOW to HIGH propagation delay Bn-to-An; CL = 50 pF; VCC = 3.3 V - 5.2 - ns tPHL HIGH to LOW propagation delay Bn-to-An; CL = 50 pF; VCC = 3.3 V - 4.9 - ns Ci input capacitance control inputs; VI = 3.0 V or 0 V - 2 2.5 pF Cio input/output capacitance A port; VO = 3.0 V or 0 V - 4.6 6 pF B port; VO = VTT or 0 V - 3.4 4.3 pF 4. Ordering information Table 2. Ordering information Type number GTL2014PW Package Name Description Version TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 Standard packing quantities and other packaging data are available at www.nxp.com/packages/. 4.1 Ordering options Table 3. GTL2014 Product data sheet Ordering options Type number Topside mark Temperature range GTL2014PW GTL2014 Tamb = -40 C to +85 C All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 2 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 5. Functional diagram GTL2014 B0 A0 B1 A1 B2 A2 B3 A3 002aab139 VREF Fig 2. GTL2014 Product data sheet DIR Logic diagram for GTL2014 All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 3 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 6. Pinning information 6.1 Pinning DIR 1 14 VCC B0 2 13 A0 B1 3 VREF 4 B2 5 10 A2 B3 6 9 A3 GND 7 8 GND 12 A1 GTL2014PW 11 GND 002aab138 Fig 3. Pin configuration for TSSOP14 6.2 Pin description Table 4. GTL2014 Product data sheet Pin description Symbol Pin Description DIR 1 direction control input (LVTTL) B0 2 data inputs/outputs (GTL) B1 3 B2 5 B3 6 A0 13 A1 12 A2 10 A3 9 VREF 4 GTL reference voltage GND 7, 8, 11 ground (0 V) VCC 14 positive supply voltage data inputs/outputs (LVTTL) All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 4 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 7. Functional description Refer to Figure 2 "Logic diagram for GTL2014". 7.1 Function table Table 5. Function table H = HIGH voltage level; L = LOW voltage level. Input Input/output DIR A (LVTTL) B (GTL) H input Bn = An L An = Bn input 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current input voltage VI Conditions Min Max Unit -0.5 +4.6 V VI < 0 V - -50 mA A port -0.5[2] +7.0 V B port -0.5[2] +4.6 V - -50 mA A port -0.5[2] +7.0 V B port -0.5[2] +4.6 V A port - 32 mA B port - 80 mA - -32 mA -60 +150 C IOK output clamping current A port; VO < 0 V VO output voltage output in OFF or HIGH state LOW-level output current IOL IOH HIGH-level output current Tstg storage temperature [1] current into any output in the LOW state current into any output in the HIGH state; A port [3] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 9 "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [3] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 5 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 9. Recommended operating conditions Table 7. Operating conditions [1] Symbol Parameter VCC supply voltage termination VTT Conditions voltage[2] reference voltage Vref input voltage VI GTL- HIGH-level input voltage LOW-level input voltage VIL Typ Max Unit 3.0 - 3.6 V 0.85 0.9 0.95 V GTL 1.14 1.2 1.26 V GTL+ 1.35 1.5 1.65 V overall 0.5 2 V 3 TT VCC/2 V GTL- 0.5 0.6 0.63 V GTL 0.76 0.8 0.84 V GTL+ 0.87 1.0 1.10 V B port 0 VTT 3.6 V 0 3.3 5.5[3] V except B port VIH Min B port Vref + 0.050 - - V except B port 2 - - V B port - - Vref - 0.050 V except B port - - 0.8 V IOH HIGH-level output current A port - - -16 mA IOL LOW-level output current B port - - 40 mA A port - - 16 mA operating in free-air -40 - +85 C Tamb ambient temperature [1] Unused inputs must be held HIGH or LOW to prevent them from floating. [2] VTT maximum of 3.6 V with resistor sized so IOL maximum is not exceeded. [3] A0, A1, A2, A3 VI(max) is 3.6 V if configured as outputs (DIR = L). GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 6 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 10. Static characteristics Table 8. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 C to +85 C Symbol VOH VOL Typ[1] Max Unit A port; VCC = 3.0 V to 3.6 V; IOH = -100 A [2] VCC - 0.2 - - V A port; VCC = 3.0 V; IOH = -16 mA [2] 2.0 - - V B port; VCC = 3.0 V; IOL = 40 mA [2] - 0.23 0.4 V A port; VCC = 3.0 V; IOL = 8 mA [2] - 0.28 0.4 V A port; VCC = 3.0 V; IOL = 12 mA [2] - 0.40 0.55 V A port; VCC = 3.0 V; IOL = 16 mA [2] Conditions HIGH-level output voltage LOW-level output voltage input current II Min Parameter - 0.55 0.8 V control inputs; VCC = 3.6 V; VI = VCC or GND - - 1 A B port; VCC = 3.6 V; VI = VTT or GND - - 1 A A port; VCC = 0 V or 3.6 V; VI = 5.5 V - - 10 A A port; VCC = 3.6 V; VI = VCC - - 1 A A port; VCC = 3.6 V; VI = 0 V - - -5 A IOZ OFF-state output current A port; VCC = 0 V; VI or VO = 0 V to 3.6 V - - 100 A ICC quiescent supply current A port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA - 4 10 mA B port; VCC = 3.6 V; VI = VTT or GND; IO = 0 mA - 4 10 mA ICC[3] additional quiescent current (per input) A port or control inputs; VCC = 3.6 V; VI = VCC - 0.6 V - - 500 A Ci input capacitance control inputs; VI = 3.0 V or 0 V - 2 2.5 pF Cio input/output capacitance A port; VO = 3.0 V or 0 V - 4.6 6 pF B port; VO = VTT or 0 V - 3.4 4.3 pF [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 7 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 002aab144 1200 Vth+ and Vth- (mV) 1000 Vth+ Vth- Vref 800 002aab145 1200 Vth+ and Vth- (mV) 1000 Vth+ Vth- Vref 800 600 600 400 0.5 0.6 0.7 0.8 0.9 400 0.5 1.0 Vref (V) a. VCC = 3.0 V; Tamb = -40 C 0.6 0.7 0.8 0.9 1.0 Vref (V) b. VCC = 3.3 V; Tamb = 25 C 002aab146 1200 Vth+ and Vth- (mV) 1000 Vth+ Vth- Vref 800 600 400 0.5 0.6 0.7 0.8 0.9 1.0 Vref (V) c. VCC = 3.6 V; Tamb = 85 C Vref is equal to the reference voltage on the GTL bus. Vth+ is the GTL input high threshold, which is typically equal to Vref + 50 mV. Vth- is the GTL input low threshold, which is typically equal to Vref - 50 mV. Fig 4. GTL Vth+ and Vth- versus Vref GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 8 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 11. Dynamic characteristics Table 9. Dynamic characteristics VCC = 3.3 V 0.3 V Symbol Parameter Conditions Min Typ[1] Max Unit GTL-; Vref = 0.6 V; VTT = 0.9 V tPLH LOW to HIGH propagation delay An to Bn; see Figure 5 - 2.8 5 ns tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 - 3.3 7 ns tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 - 5.3 8 ns tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 - 5.2 8 ns An to Bn; see Figure 5 - 2.8 5 ns GTL; Vref = 0.8 V; VTT = 1.2 V tPLH LOW to HIGH propagation delay tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 - 3.4 7 ns tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 - 5.2 8 ns tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 - 4.9 7 ns An to Bn; see Figure 5 - 2.8 5 ns GTL+; Vref = 1.0 V; VTT = 1.5 V tPLH LOW to HIGH propagation delay tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 - 3.4 7 ns tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 - 5.1 8 ns tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 - 4.7 7 ns [1] All typical values are at VCC = 3.3 V and Tamb = 25 C. GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 9 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 11.1 Waveforms VM = 1.5 V at VCC 3.0 V; VM = VCC/2 at VCC 2.7 V for A ports and control pins; VM = Vref for B ports. 3.0 V input 1.5 V 1.5 V 0V tPLH tp tPHL VOH 3.0 V VM output VM Vref Vref VOL 0V 002aab141 002aab140 VM = 1.5 V for A port and Vref for B port B port to A port a. Pulse duration Fig 5. b. Propagation delay times Voltage waveforms VTT input Vref Vref 1/ V 3 TT tPLH tPHL VOH output 1.5 V 1.5 V VOL 002aab142 PRR 10 MHz; Z0 = 50 ; tr 2.5 ns; tf 2.5 ns Fig 6. GTL2014 Product data sheet Propagation delay, Bn to An All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 10 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 12. Test information VCC PULSE GENERATOR VI VO DUT RL 500 CL 50 pF RT 002aab006 Fig 7. Load circuitry for switching times VTT VCC PULSE GENERATOR 25 VO VI DUT CL 30 pF RT 002aab143 Fig 8. Load circuit for B outputs RL -- Load resistor CL -- Load capacitance; includes jig and probe capacitance RT -- Termination resistance; should be equal to output impedance of pulse generators. GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 11 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 13. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 12 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 13 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 14.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10. GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 14 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 15. Abbreviations Table 12. GTL2014 Product data sheet Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor CPU Central Processing Unit ESD ElectroStatic Discharge GTL Gunning Transceiver Logic HBM Human Body Model LVTTL Low Voltage Transistor-Transistor Logic PRR Pulse Rate Repetition TTL Transistor-Transistor Logic All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 15 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 16. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes GTL2014 v.3 20120614 Product data sheet - GTL2014 v.2 Modifications: * Section 1 "General description", first paragraph, first sentence: added phrase "where GTL-/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage thresholds associated with it" * Added (new) Figure 4 "GTL Vth+ and Vth- versus Vref" GTL2014 v.2 20120306 Product data sheet - GTL2014 v.1 GTL2014 v.1 (9397 750 13534) 20050519 Product data sheet - - GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 16 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. GTL2014 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 17 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com GTL2014 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 -- 14 June 2012 (c) NXP B.V. 2012. All rights reserved. 18 of 19 GTL2014 NXP Semiconductors 4-bit LVTTL to GTL transceiver 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 June 2012 Document identifier: GTL2014