GTL2014PW,118 - NXP SEMICONDUCTORS

1. General description

The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface

with a GTL−/GTL/GTL+ bus, where GTL−/GTL/GTL+ refers to the refe rence voltage of the

GTL bus and the input/output voltage thresholds associated with it.

The direction pin allows the p art to function as eith er a GTL to LVTTL sampling receiver or

as a LVTTL to GTL interface.

The GTL2014 LVTTL inp uts (only) are tolera nt up to 5.5 V allowing direct access to TTL or

5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.

The GTL2014 GTL inpu t s and o utput s o perate up to 3.6 V, allo wing the device to be used

in higher voltage open-drain output applications.

GTL2014 is pin-to-pin backward compatible to the GTL2005 (labels for A port and B port

are interchanged). GTL 201 4’s Vref tracks down to 0.5 V for low volt age CPU, pr opagation

delays are slightly longer, while GTL2005’s Vref linearity degrades below 0.8 V and has

shorter propagation dela y.

2. Features and benefits

Operates as a 4-bit GTL−/GTL/GTL+ sampling receiver or as a LVTTL to

GTL−/GTL/GTL+ driver

3.0 V to 3.6 V operation with 5 V tolerant LVTTL input

GTL input and output 3.6 V tolerant

Vref adjustable from 0.5 V to VCC/2

Partial power-down permitted

ESD protection exceeds 2000 V HBM per JESD22-A114 an d 1000 V CDM per

JESD22-CC101

GTL2014

4-bit LVTTL to GTL transceiver

Rev. 3 — 14 June 2012 Product data sheet

Fig 1. GTL2005/GTL2014 positioning

002aab378

GTL−GTL GTL+

fast tPD

slow tPD

GTL2014

GTL2005

Product data sheet Rev. 3 — 14 June 2012 2 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

Latch-up protection exceeds 500 mA per JESD78

Package offered: TSSOP14

3. Quick reference data

4. Ordering information

Standard packing quantities and other packaging data are available at

www.nxp.com/packages/.

4.1 Ordering options

Table 1. Quick reference data

Tamb =25

Symbol Parameter Conditions Min Typ Max Unit

tPLH LOW to HIGH propagation delay An-to-Bn; CL=50pF; V

CC = 3.3 V - 2.8 - ns

tPHL HIGH to LOW propagation delay An-to-Bn; CL=50pF; V

CC = 3.3 V - 3.4 - ns

tPLH LOW to HIGH propagation delay Bn-to-An; CL=50pF; V

CC = 3.3 V - 5.2 - ns

tPHL HIGH to LOW propagation delay Bn-to-An; CL=50pF; V

CC = 3.3 V - 4.9 - ns

Ciinput capacitance control inputs; VI= 3.0 V or 0 V - 2 2.5 pF

Cio input/output capacitance A port; VO= 3.0 Vor 0 V - 4.6 6 pF

B port; VO=V

TT or 0 V - 3.4 4.3 pF

Table 2. Ordering information

Type number Package

Name Description Version

GTL2014PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

Table 3. Orderin g options

Type number Topside mark Temperature range

GTL2014PW GTL2014 Tamb =−40 °Cto +85°C

Product data sheet Rev. 3 — 14 June 2012 3 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

5. Functional diagram

Fig 2. Logic diagram for GTL2014

002aab139

GTL2014

VREF DIR

Product data sheet Rev. 3 — 14 June 2012 4 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 3. Pin confi gura tio n for TSSOP14

GTL2014PW

DIR V

B0 A0

B1 A1

VREF GND

B2 A2

B3 A3

GND GND

002aab138

Table 4. Pin description

Symbol Pin Description

DIR 1 direction control input (LVTT L)

B0 2 data inputs/outputs (GTL)

B1 3

B2 5

B3 6

A0 13 data inputs/outputs (LVTTL)

A1 12

A2 10

A3 9

VREF 4 GTL reference voltage

GND 7, 8, 11 ground (0 V)

VCC 14 positive supply voltage

Product data sheet Rev. 3 — 14 June 2012 5 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

7. Functional description

Refer to Figure 2 “Logic diagram for GTL2014”.

7.1 Function table

8. Limiting values

[1] S tresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under Section 9 “Recommended operating conditions” is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[3] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

Table 5. Functio n table

H = HIGH voltage level; L = LOW voltage level.

Input Input/output

DIR A (LVTTL) B (GTL)

H input Bn = An

L An = Bn input

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

IIK input clamping current VI<0V - −50 mA

VIinput voltage A port −0.5[2] +7.0 V

B port −0.5[2] +4.6 V

IOK output clamping current A port; VO<0V - −50 mA

VOoutput voltage output in OFF or HIGH state

A port −0.5[2] +7.0 V

B port −0.5[2] +4.6 V

IOL LOW-level output current current into any output in the LOW state

A port - 32 mA

B port - 80 mA

IOH HIGH-level output current current into any output in the HIGH state;

A port -−32 mA

Tstg storage temperature [3] −60 +150 °C

Product data sheet Rev. 3 — 14 June 2012 6 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

9. Recommended operating conditions

[1] Unused inputs must be held HIGH or LOW to prevent them from floating.

[2] VTT maximum of 3.6 V with resistor sized so IOL maximum is not exceeded.

[3] A0, A1, A2, A3 VI(max) is 3.6 V if configured as outputs (DIR = L).

Table 7. Operating conditions [1]

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 3.0 - 3.6 V

VTT termination voltage[2] GTL−0.85 0.9 0.95 V

GTL 1.14 1.2 1.26 V

GTL+ 1.35 1.5 1.65 V

Vref reference voltage overall 0.5 2⁄3VTT VCC/2 V

GTL−0.5 0.6 0.63 V

GTL 0.76 0.8 0.84 V

GTL+ 0.87 1.0 1.10 V

VIinput voltage B port 0 VTT 3.6 V

except B port 0 3.3 5.5[3] V

VIH HIGH-level input voltage B port Vref + 0.050 - - V

except B port 2 - - V

VIL LOW-level input voltage B port - - Vref −0.050 V

except B port - - 0.8 V

IOH HIGH-level output current A port - - −16 mA

IOL LOW-level output current B port - - 40 mA

A port - - 16 mA

Tamb ambient temperature operating in free-air −40 - +85 °C

Product data sheet Rev. 3 — 14 June 2012 7 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

10. Static characteristics

[1] All typical values are measured at VCC = 3.3 V and Tamb =25°C.

[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[3] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Table 8. Static characteristics

Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb =

−

Cto +85

Symbol Parameter Conditions Min Typ[1] Max Unit

VOH HIGH-level output

voltage A port; VCC = 3.0 V to 3.6 V; I OH =−100 μA[2] VCC −0.2 - - V

A port; VCC = 3.0 V; IOH =−16 mA [2] 2.0 - - V

VOL LOW-level output

voltage B port; VCC = 3.0 V; IOL =40mA [2] -0.230.4V

A port; VCC = 3.0 V; IOL =8mA [2] -0.280.4V

A port; VCC = 3.0 V; IOL =12mA [2] -0.400.55V

A port; VCC = 3.0 V; IOL =16mA [2] -0.550.8V

IIinput current control inputs; VCC =3.6V;

VI=V

CC or GND --±1μA

B port; VCC = 3.6 V; VI=V

TT or GND - - ±1μA

A port; VCC = 0 V or 3.6 V; VI=5.5V - - 10 μA

A port; VCC = 3.6 V; VI=V

CC --±1μA

A port; VCC = 3.6 V; VI=0V - - −5μA

IOZ OFF-state output

current A port; VCC =0V; V

Ior VO=0Vto3.6V - - ±100 μA

ICC quiescen t supply

current A port; VCC = 3.6 V; VI=V

CC or GND;

IO=0mA -410mA

B port; VCC = 3.6 V; VI=V

TT or GND;

IO=0mA -410mA

ΔICC[3] additional quiescent

current (per input) A port or control inputs; VCC =3.6V;

VI=V

CC −0.6 V --500μA

Ciinput capacitance control inputs; VI=3.0Vor0V - 2 2.5 pF

Cio input/output

capacitance A port; VO= 3.0 V or 0 V - 4.6 6 pF

B port; VO=V

TT or 0 V - 3.4 4.3 pF

Product data sheet Rev. 3 — 14 June 2012 8 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

a. VCC = 3.0 V; Tamb =−40 °Cb.V

CC =3.3V; T

amb =25°C

c. VCC = 3.6 V; Tamb =85°C

Vref is equal to the reference voltage on the GTL bus.

Vth+ is the GTL input high threshold, which is typically equal to Vref +50mV.

Vth− is the GTL input low threshold, which is typically equal to Vref −50 mV.

Fig 4. GT L Vth+ and Vth− versus Vref

002aab144

Vref (V)

0.5 1.00.90.6

800

600

1000

1200

Vth+

and

Vth−

(mV)

400 0.7 0.8

Vth+

Vth−

Vref

002aab145

Vref (V)

0.5 1.00.90.6

800

600

1000

1200

Vth+

and

Vth−

(mV)

400 0.7 0.8

Vth+

Vth−

Vref

002aab146

Vref (V)

0.5 1.00.90.6

800

600

1000

1200

Vth+

and

Vth−

(mV)

400 0.7 0.8

Vth+

Vth−

Vref

Product data sheet Rev. 3 — 14 June 2012 9 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

11. Dynamic characteristics

[1] All typical values are at VCC = 3.3 V and Tamb =25°C.

Table 9. Dynamic characteristics

VCC =3.3V

0.3 V

Symbol Parameter Conditions Min Typ[1] Max Unit

GTL−; Vref = 0.6 V; VTT =0.9V

tPLH LOW to HIGH propagation delay An to Bn; see Figure 5 -2.85ns

tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 -3.37ns

tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 -5.38ns

tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 -5.28ns

GTL; Vref = 0.8 V; VTT =1.2V

tPLH LOW to HIGH propagation delay An to Bn; see Figure 5 -2.85ns

tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 -3.47ns

tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 -5.28ns

tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 -4.97ns

GTL+; Vref = 1.0 V; VTT =1.5V

tPLH LOW to HIGH propagation delay An to Bn; see Figure 5 -2.85ns

tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 -3.47ns

tPLH LOW to HIGH propagation delay Bn to An; see Figure 6 -5.18ns

tPHL HIGH to LOW propagation delay Bn to An; see Figure 6 -4.77ns

Product data sheet Rev. 3 — 14 June 2012 10 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

11.1 Waveforms

VM= 1.5 V at VCC ≥3.0 V; VM=V

CC/2 at VCC ≤2.7 V for A ports and control pins;

VM=V

ref for B ports.

VM= 1.5 V for A port and Vref for B port B port to A port

a. Pulse duration b. Propagation delay times

Fig 5. Voltage waveforms

PRR ≤10 MHz; Z0=50Ω; tr≤2.5 ns; tf≤2.5 ns

Fig 6. Propagation de la y, Bn to An

002aab140

3.0 V

0 V

VMVM

002aab141

3.0 V

0 V

VOH

VOL

tPLH tPHL

Vref

1.5 V 1.5 Vinput

output

002aab142

PLH

PHL

1.5 V1.5 V

ref

input

output

Product data sheet Rev. 3 — 14 June 2012 11 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

12. Test information

RL — Load resistor

CL — Load capacit ance; includes jig and probe capacitance

RT — Termination resistance; should be equal to output impedance of pulse generators.

Fig 7. Load circuitry for switching times

Fig 8. Load circuit fo r B outputs

PULSE

GENERATOR

50 pF

002aab006

500 Ω

DUT

PULSE

GENERATOR DUT VO

30 pF

25 Ω

002aab143

VCC

VTT

Product data sheet Rev. 3 — 14 June 2012 12 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

13. Package outline

Fig 9. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 3 — 14 June 2012 13 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 3 — 14 June 2012 14 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 10) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enoug h that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 10.

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 3 — 14 June 2012 15 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 10. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 12. Abbreviations

Acronym Description

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

CPU Central Processing Unit

ESD ElectroStatic Discharge

GTL Gunning Transceiver Logic

HBM Human Body Model

LVTTL Low Voltage Transistor-Transistor Logic

PRR Pulse Rate Repetition

TTL Transistor-Transistor Logic

Product data sheet Rev. 3 — 14 June 2012 16 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

16. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

GTL2014 v.3 20120614 Product data sheet - GTL2014 v.2

Modifications: •Section 1 “General description”, first paragraph, first sentence: added phra se “where

GTL−/GTL/GTL+ refers to the reference voltage of the GTL bus and the input/output voltage

thresholds associated with it”

•Added (new) Figure 4 “GT L Vth+ and Vth- versus Vref”

GTL2014 v.2 20120306 Product data sheet - GTL2014 v.1

GTL2014 v.1

(9397 750 13534) 20050519 Produ ct data sheet - -

Product data sheet Rev. 3 — 14 June 2012 17 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

17. Legal information

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[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 14 June 2012 18 of 19

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product i s automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automo tive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

17.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors GTL2014

4-bit LVTTL to GTL transceiver

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 June 2012

Document identifier: GTL2014

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

11.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 11

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Soldering of SMD packages . . . . . . . . . . . . . . 13

14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 13

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 13

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 13

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 14

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

18 Contact information. . . . . . . . . . . . . . . . . . . . . 18

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19