081315 DALLAS SEMICONDUCTOR PRELIMINARY DS1315 Phantom Time Chip FEATURES Realtime clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years Adjusts for months with fewer than 31 days Automatic leap year correction No address space required to communicate with RTC Provides nonvolatile controller functions for battery backup of SRAM Supports redundant battery attachment for high-reli- ability applications Full 410% Vcc operating range PIN ASSIGNMENT x O14 "16 I Veet x2 [] 2 15 0) Veco we C] 3 14 5 BAT2 pati C] 4 13 RST and (J 5 12 OE oT] 6 "1 CEI aQ7 10 CEO Gnp (J 8 9 ROM/RAM 16-PIN DIP (300 MIL) x1 1 16 OD Vee @ 5 volt operation aon 5 i Pa meee BATICI 4 13 [1D Rst OPTIONS GNDOIL] 5 v2 fo OE @ Industrial (-45C to +85C) operating temperature an ; 10 = 5 ranges GNOOT 8 9 ROM/RAM 3 volt operating range 16-PIN SOIC (300 MIL) Packaging: 16-pin DIP, 16 pin SOIC and 20 pin TSSOP x O]1 VY 201) Veer x2 [J | 2 91 Veco ORDERING INFORMATION Ne ; : = oo DS1315XX-XX pati (] | 5 is] AST 7 eno (] |6 15[] O A 3V-3 voit operation* nc C]|7 140 Ne 5V-5 volt operation oUls 130 Cel blank-commercial temp range ais 12[0 CEO N-industrial temp range ano [] | 10 1110 ROMAAM $16-pin SOIC 20-PIN TSSOP E-20-pin TSSOP *Contact factory for availability 110695 1/22 an eopyrant 1995 by Dallas Semiconductor Corporation 332 Rights . patents and other intellectual DallasDS1315 PIN DESCRIPTION In the absence of power, an external battery maintains X1, X2 32.768 KHz Crystal Connection the timekeeping operation and provides power for a WE Write Enable CMOS static RAM. The watch keeps track of hun- BAT1 ~ Battery 1 Input dredths of seconds, seconds, minutes, hours, day, date, GND Ground month, and year information. The last day of the month D Data Input is automatically adjusted for months with less than 31 Q Data Output days, including leap year correction. The watch oper- ROM/RAM ~ ROM/RAM Mode Select ates in one of two formats: a 12-hour mode with an AM/ CEO Chip Enable Output PM indicator or a 24-hour mode. The nonvolatile con- CEI ~ Chip Enable Input troller supplies all the necessary support circuitry to OE ~ Output Enable convert a CMOS RAM to a nonvolatile memory. The RST ~ Reset DS1215 can be interfaced with either RAM or ROM BAT2 - Battery 2 Input without leaving gaps in memory. Voco Switched Supply Output Veci Power Supply Input OPERATION DESCRIPTION The block diagram of Figure 1 illustrates the main ele- The DS1315 Phantom Time Chip is a combination ofa Ments of the Time Chip. The following paragraphs CMOS timekeeper anda nonvolatile memory controller, describe the signals and functions. TIMING BLOCK DIAGRAM Figure 1 Xx | 32.768 KHz [__] CLOCK/CALENDAR LOGIC ROM/AAM I CEG ' UPDATE __ READ cel - 5E WRITE OE _ CONTROL TIMEKEEPING REGISTER WE - POWER-FAIL RST ACCESS ENABLE | ENABLE COMPARISON REGISTER DETECTOR DBD e DATA Q VO BUFFERS [ INTERNAL Voc Veer POWER-FAIL Veco oo DETECT -___ LOGIC BAT, BAT2 110695 2/22 333081315 Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64bit pattern are directed to memory via the chip enable out- put pin (CEO). After recognition is established, the next 64 read or write cycles either extract or update data in the Time Chip and CEO remains high during this time, disabling the con- nected memory. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input (CEI), output enable (OE), and write enable (WE). Initially, a read cycle using the CEI andOE control of the Time Chip starts the pattern recognition sequence by moving pointer to the first bit of the 64 bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip. When the first write cycle is executed, it is compared to bit 1 of the 64~bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. Ifa match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle oc- curs at any time during pattern recognition, the present sequence is aborted and the comparison register point- eris reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (This bit pat- tern is shown in Figure 2.) With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles wili cause the Time Chip to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the Time Chip. A standard 32,768 KHz quartz crystal can be directly connected to the 0S1315 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load ca- pacitance (C_) of 12.5 pF. For more information on crys- tal selection and crystal layout considerations, please consult Application Note 58, Crystal Considerations with Dallas Real Time Clocks. 110695 3/22 334TIME CHIP COMPARISON REGISTER DEFINITION Figure 2 3 091315 7 6 5 4 2 1 0 BYTE O 1 1 0 0 0 1 0 1 le - cs BYTE 1 9 1 1 1 0 1 0 bk - 3A BYTE 2 1 0 1 0 0 0 1 1 + A3 BYTE 3 | 0 1 0 1 1 1 0 0 fe 5C BYTE 4 1 1 0 0 9 1 0 1 je cs BYTES 0 0 1 1 1 0 1 0 fe 3A BYTE 6 1 0 1 0 0 0 1 1 fe A3 BYTE7 | 2 1 0 1 1 1 0 0 j 5C NOTE: The pattern recognition in Hexis C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 10!9. NONVOLATILE CONTROLLER OPERATION The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/RAM select pin. When ROM/RAN is connected to ground, the controller is set in the RAM mode and per- forms the circuit functions required to make CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery inputs or Vcc) to Veco with a maximum voltage drop of 0.3 volts. The Veco output pin is used to supply uninterrupted power to CMOS SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the bat- tery with the highest voltage is automatically switched to Veco. If only one battery is used in the system, the un- used battery input should be connected to ground. The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection. Power-fail detection occurs when Vcc, falls below Vp which is set by an internal bandgap reference. The DS1315 con- stantly monitors the Voc; supply pin. When Vcc is less than Vpr, power-fail circuitry forces the chip enable out- put (CEO) to Vcc) or Vear-0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a maximum propagation delay of 5 ns. Internally, the DS1315 aborts any data transfer in progress without changing any of the Time Chip regis- ters and prevents future access until Vcc; exceeds Vpr. A typical RAM/Time Chip interface is illustrated in Figure 3. 335 110695 4/22081315 When the ROM/RAM pin is connected to Veco, the con- troller is set in the ROM mode. Since ROM is a read-only device that retains data in the absence of power, battery backup and write protection is not required. As a result, the chip enable logic will force CEO low when power fails. However, the Time Chip does retain the same in- ternal nonvolatility and write protection as described in the RAM mode. A typical ROM/Time Chip interface is illustrated in Figure 4. DS1315 TO RAM/TIME CHIP INTERFACE Figure 3 CMOS STATIC RAM vt Vv AQ - AN | AO-AN DATA V/O WE >] WE OE * OF cE Voe DS1315 CEO Veco | OE D We Qa ce CEI Veet Ast > ast OM BAT, BAT X1 Xe + BAT, | WO 32.768 KHz + | BATo 110695 5/22 336081315 ROM/TIME CHIP INTERFACE Figure 4 FOM Voc be_ Vcc Ai, A3-AN DATA /O ~ AZ AQ CE DS1315 CEG OE Q WE Veci Vec ce ____| Rg} > CEI = Veco ROM AST Ram BAT, _BAT2 x1 X2 + + TT (o 7, 32.768 KHz TIME CHIP REGISTER INFORMATION with logic high being PM. In the 24-hour mode, bit 5 is Time Chip information is contained in eight registers of 8 the second 10-hour bit (20 -23 hours). bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time Chip regis- ters, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could pro- duce erroneous results. These read/write registers are defined in Figure 5. OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other in- puts. Bit 5 controls the oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to increment. Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. AM-PM/12/24 MODE ZERO BITS Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12hour mode, bit 5 is the AM/PM bit Registers 1, 2,3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. 110695 6/22 337DS1315 TIME CHIP REGISTER DEFINITION Figure 5 REGISTER RANGE (BCD) 7 6 5 4 2 1 0 0.1 SEC 0.01 SEC 00-99 1 0 10 SEC SECONDS 00-59 2 0 10 MIN MINUTES 00-59 42/24 0 10 HR Hou! 01-12 3 AP R 00-23 4 0 0 osc RST DAY 01-07 5 0 0 10 DATE DATE 01-31 6 0 0 0 10 MONTH Ot-12 MONTH 7 10 YEAR YEAR 00-99 110895 7/22081315 ABSOLUTE MAXIMUM RATINGS* Voitage on any Pin Relative to Ground Operating Temperature, commercial range Operating Temperature, industrial range Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C 45C to +85C -55C to +126C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) Ei 339 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage 5 Volt Voc 45 5.0 5.5 Vv 1 Operation Power Supply Voitage 3 Volt Voc 2.7 3.0 3.3 Vv 1 Operation Input Logic 1 Vin 2.2 Voc + 0.3 Vv 1 Input Logic 0 Vit -0.3 +0.6 Vv 1 Battery Voltage Vgari or Vaar2 Veati 25 3.7 Veat2 DC OPERATING ELECTRICAL CHARACTERISTICS (0C to 70C; Voc = 5.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Average Vcc Power Supply lees 5 mA 6 Current Voc Power Supply Current, lecot 150 mA 7 (Veco = Vecr-0.3) TTL Standby Current (CEI = Vin) lece 3 mA 6 CMOS Standby Current locs 1 mA (CEI = Veci-0.2) Input Leakage Current (any input) hit -1 +1 pA 10 Output Leakage Current (any lot ~1 +1 HA output) Output Logic 1 Voltage Vox 2.4 Vv 2 (lout =~-1.0 mA) Output Logic 0 Voltage Voi 0.4 Vv 2 (lout = 4.0 mA) Power Fail Trip Point Ver 4.25 4.5 Vv Battery Switch Voltage Vsw Veatt, VeaT2 110695 8/22DS1315 DC POWER DOWN ELECTRICAL CHARACTERISTICS (0C to 70C; Vec < 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEO Output Voltage VcEo Veol-0.2 V 8 or Veart.2 ~0.2 Veari OF Veate Battery Current IBaT 0.5 pA 6 Battery Backup Current loco2 10 pA @ Vcco = Veat0.2V AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = GND (OC to 70C; Vcc = 5.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tac 65 ns CEI Access Time tco 55 ns OE Access Time toe 55 ns CEI to Output Low Z tcoE 5 ns OE to Output Low Z tocEe 5 ns CEI to Output High Z top 25 ns OE to Output High Z topo 25 ns Read Recovery tar 10 ns Write Cycle two 65 ns Write Pulse Width twp 55 ns Write Recovery twa 10 ns 4 Data Setup tos 30 ns 5 Data Hold Time tbH 0 ns 5 CEI Puise Width tow 60 ns OE Pulse Width tow 55 ns RST Pulse Width trast 65 ns CEI Propagation Delay tep 5 ns 2,3, 11 CEI High to Power-Fail ter 0 ns 11 110605 9/22 340081315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = Veco (0C to 70C; Voc = 5.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycie Time trac 65 ns CEI Access Time tco 55 ns OE Access Time toe 55 ns CEI to Output Low Z tcoe 5 ns OE to Output Low Z toge 5 ns CEI to Output High Z top 25 ns OE to Output High Z topo 25 ns Address Setup Time tas 5 ns Address Hold Time taH 5 ns Read Recovery tar 10 ns Write Cycle two 65 ns CEI Pulse Width tow 55 ns OE Pulse Width tow 55 ns Write Recovery twr 10 ns 4 Data Setup tos 30 ns 5 Data Hold Time tox 0 ns 5 RST Pulse Width tast 65 ns CEI Propagation Delay tpp 5 ns 2,3, 11 CEI High to Power-Fail tpr 0 ns 1 3VOLT DEVICE OPERATING RANGE CHARACTERISTICS DC OPERATING ELECTRICAL CHARACTERISTICS (0C to 70C; Voc = 3.0 + 10%) 341 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Average Vcc Power Supply loc1 3 mA 6 Current Average Vcc Power Supply Iecot 100 mA 7 Current, (Veco = Veci-0.3) TTL Standby Current (CEI = Vi) loca 2 mA 6 CMOS Standby Current loca 1 mA 6 (CEI = Vec}-0.2) Input Leakage Current (any input) Iie ~1 +1 pA Output Leakage Current (any ILo -1 +1 pA output) 110695 10/22DS1315 DC OPERATING ELECTRICAL CHARACTERISTICS (cont'd) (0C to 70C; Voc = 3.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Output Logic 1 Voltage Vou 2.4 Vv 2 (lout = 0.4 mA) Output Logic 0 Voltage VoL 0.4 Vv 2 (lout = 1.6 mA) Power Fail Trip Point VprF 2.5 2.7 v Battery Switch Voltage Vsw Veat1; Veat2 DC POWER DOWN ELECTRICAL CHARACTERISTICS (0C to 70C; Voc > 2.7V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEO Output Voltage VcEO Veci or Vv VBATI,2 0.2 Veati OF Veate Battery Current IBaT 0.3 pA Battery Backup Current leco2 10 pA @ Voco = Vpat -0.2 110695 11/22 342DS1315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = GND (0C to 70C; Voc = 5.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tac 120 ns CEI Access Time tco 100 ns OE Access Time toe 100 ns CEI to Output Low Z tcoe 5 ns GE to Output Low Z toce 5 ns Ei CEI to Output High Z top 40 ns OE to Output High Z topo 40 ns Read Recovery tar 20 ns Write Cycle twe 120 ns Write Pulse Width twp 100 ns Write Recovery twr 20 ns 4 Data Setup tos 45 ns 5 Data Hold Time tou 0 ns 5 CE! Pulse Width tow 105 ns OE Pulse Width tow 100 ns RST Pulse Width tast 120 ns CEI Propagation Delay tep 10 ns 2,3, 12 CEi High to Power-Fail tpr 0 ns 12 110695 12/22 343081315 AC ELECTRICAL OPERATING CHARACTERISTICS ROM/RAM = Veco (0C to 70C; Veg = 3.0 + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tac 120 ns CEI Access Time tco 100 ns GE Access Time toe 100 ns CEI to Output Low Z tcoe 5 ns OE to Output Low Z toce 5 ns CEI to Output High Z top 40 ns OE to Output High Z topo 40 ns Address Setup Time tas 10 ns Address Hold Time taH 10 ns Read Recovery tar 20 ns Write Cycle twe 120 ns CE! Pulse Width tow 100 ns OE Pulse Width tow 100 ns Write Recovery twr 20 ns 4 Data Setup tos 45 ns 5 Data Hold Time tou 0 ns 5 RST Pulse Width tast 120 ns CEI Propagation Delay tpp 5 ns 2,3, 12 CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES input Capacitance Cin 10 pF Output Capacitance Court 10 pF 110695 13/22 344TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND Figure 6 WE = Vin tac - CEI le_ tar ~ ico S tow a __ top ___ OE toe - tow CWA M_._ tong _ CH OUTPUT DATA VALID ) TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND Figure 7 a OE = Vin i two WE pa twR or M$ twp _ t twr CEl leg to See Ww t_ tps * tow 081315 345 110895 14/22DS1315 TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = Veco Figure 8 tag __| tar CEI OE WE Q OUTPUT DATA VALID TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = Vcco Figure 9 two >| < tow ~ + twa GE Lt L MA ' } twa t two _ NY + ae OE ___ tow _ N SY c / \ tas- < tay f# tas pa tay WE QQ tos > oH ~- tos e toy =a D OO DATA IN STABLE Te 110695 15/22 346DS1315 TIMING DIAGRAM: RESET PULSE Figure 10 AST ast _ V 5V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS, Ei ROM/RAM = Veco OR GND (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Recovery Time at tREC 2 mS 11 Power-Up Voc>4.5 Voc Slew Rate Power tr 300 mS 11 Down 4.0< Voc < 4.5 Voc Slew Rate Power tes 10 mS 11 Down 3.0< Voc < 4.0 Voc Slew Rate Power tr 0 mS 1 UP 4.5< Vcc < 4.0 CEI High to PowerFail tpr 0 ms 11 5V DEVICE POWER-UP CONDITION Figure 11 Ka Voc} ___* BAT - 0.2V. ~ ted ROMRAM=GND CEO "NE e ROWRAM=Voco CEO _/ \ 110695 16/22 347DS1315 5V DEVICE POWER-DOWN CONDITION Figure 12 El toe ipo ROM/RAM = GND CEO tce ROMRAM =Vecg CEO Veer e ter PA Veat - 0.2V 3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS, ROM/RAM = Veco OR GND (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Recovery Time at tREc 2 ms 12 PowerUp Vec>2.7 Voc Slew Rate Power te 300 ms 12 Down 2.6< Voc < 2.7 Vcc Slew Rate Power tr 0 ms 12 UP 2.7< Vcc < 2.6 CEI High to Power-Fail tpr 0 ms 12 110695 17/22 3480S1315 3V DEVICE POWER-UP CONDITION Figure 13 BAT - 0.2V. e| le tpp ROM/RAM = GND CEO ROM/RAM =Veco CEO _/ \ 3V DEVICE POWER-DOWN CONDITION Figure 14 tce _] EUGKEG Aa feo a tp Vear - 0.2V ROM/RAM = GND CEO tee wv ROMRAM=Vcco CEQ P\ Veci a7 2.6V 2.5V Lg 110695 18/22 349081315 NOTES: 1. oN OP FF YS N All voltages are referenced to ground. Measured with load shown in Figure 15. Input pulse rise and fall times equal 10 ns. twr is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. tpH and tpg are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. Measured without RAM connected. loco: is the maximum average load current the DS1315 can supply to external memory. Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to Veco, CEO will go to a low level as Vcc; falls below Vear. Iccoz is the maximum average !oad current that the DS1315 can supply to memory in the battery backup mode. 10. Applies to all input pins except RST. RST is pulled internally to Voc). 11. See Figures 11 and 12. 12. See Figures 13 and 14. OUTPUT LOAD Figure 15 50 pF 110695 19/22 350DS1315 TIME CHIP 16PIN DIP Peer ee be) oo DS1315 PKG 16-PIN DIM MIN MAX A IN. 0.740 0.780 MM B IN. 0.240 0.260 MM Cc IN. 0.120 0.140 MM D IN. 0.300 0.325 MM E IN. 0.015 0.040 MM F IN. 0.110 0.140 MM G IN. 0.090 0.110 MM IN. 0.300 0.370 MM JIN. 0.008 0.012 MM K IN. 0.015 0.021 MM 351 110695 20/22DS1315 DS1315 TIME CHIP 16-PIN SOIC Km Gi ht FAs sth RAAB BHES | BEBE rene BH . F r |e E phi J L PKG 16-PIN DIM MIN MAX AIN. 0.402 0.412 MM 10.21 10.46 BIN. 0.290 | 0.300 MM 7.37 7.65 CIN. 0.089 | 0.095 MM 2.26 2.41 EIN. 0.004 | 0.012 MM 0.102 0.30 FIN. 0.094 | 0.105 MM 2.38 2.68 GIN. 0.050 BSC MM 1.27 BSC HIN 0.398 | 0.416 MM 10.11 10.57 JIN 0.009 0.013 MM 0.229 0.33 KIN. 0.013 | 0.019 uM 0.33 0.48 LIN 0.016 0.040 MM 0.40 1.02 PHI o 8 110695 21/22 352081315 DS1315 TIME CHIP 20-PIN TSSOP D LINO NNO D WU UUU UGE DIM MIN | MAX Amm [| - 1.10 AimMM | 0.05 | - A2MM | 0.75 | 1.05 cum [0.09 | 0.18 LMM | 050 | 0.70 e1MM 0.65 BSC BMM | 0.18 | 0.30 DMM | 6.40 | 6.90 EMM 4.40 NOM GMM 0.25 REF HMM | 625 | 655 phi | o 8 56-G2010-000 SEE DETAILA el DETAIL A 110695 22/22 353