LM6132
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SNOS751D –APRIL 2000–REVISED FEBRUARY 2013
LM6132/LM6134 Dual and Quad Low Power 10 MHz Rail-to-Rail I/O Operational Amplifiers
Check for Samples: LM6132
1FEATURES DESCRIPTION
The LM6132/34 provides new levels of speed vs.
2• (For 5V Supply, Typ Unless Noted) power performance in applications where low voltage
• Rail-to-Rail Input CMVR −0.25V to 5.25V supplies or power limitations previously made
• Rail-to-Rail Output Swing 0.01V to 4.99V compromise necessary. With only 360 μA/amp supply
current, the 10 MHz gain-bandwidth of this device
• High Gain-Bandwidth, 10 MHz at 20 kHz supports new portable applications where higher
• Slew Rate 12 V/μspower devices unacceptably drain battery life.
• Low Supply Current 360 μA/Amp The LM6132/34 can be driven by voltages that
• Wide Supply Range 2.7V to over 24V exceed both power supply rails, thus eliminating
• CMRR 100 dB concerns over exceeding the common-mode voltage
range. The rail-to-rail output swing capability provides
• Gain 100 dB with RL= 10k the maximum possible dynamic range at the output.
• PSRR 82 dB This is particularly important when operating on low
supply voltages. The LM6132/34 can also drive large
APPLICATIONS capacitive loads without oscillating.
• Battery Operated Instrumentation Operating on supplies from 2.7V to over 24V, the
• Instrumentation Amplifiers LM6132/34 is excellent for a very wide range of
applications, from battery operated systems with
• Portable Scanners large bandwidth requirements to high speed
• Wireless Communications instrumentation.
• Flat Panel Display Driver
Connection Diagram
Figure 1. 8-Pin SOIC/PDIP (Top View) Figure 2. 14-Pin SOIC/PDIP (Top View)
See Package Number D and P See Package Number D and NFF0014A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM6132
SNOS751D –APRIL 2000–REVISED FEBRUARY 2013
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Absolute Maximum Ratings(1)(2)
ESD Tolerance(3) 2500V
Differential Input Voltage 15V
Voltage at Input/Output Pin (V+)+0.3V, (V−)−0.3V
Supply Voltage (V+–V−) 35V
Current at Input Pin ±10 mA
Current at Output Pin(4) ±25 mA
Current at Power Supply Pin 50 mA
Lead Temp. (soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature(5) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human body model, 1.5 kΩin series with 100 pF.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings(1)
Supply Voltage 1.8V ≤V+≤24V
Junction Temperature Range LM6132, LM6134 −40°C ≤TJ≤+85°C
Thermal resistance (θJA) P Package, 8-pin PDIP 115°C/W
D Package, 8-pin SOIC 193°C/W
NFF0014A Package, 14-pin PDIP 81°C/W
D Package, 14-pin SOIC 126°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical characteristics.
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5.0V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5.0V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
Boldface limits apply at the temperature extremes LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
VOS Input Offset Voltage 0.25 2 6 mV
4 8 max
TCVOS Input Offset Voltage Average Drift 5μV/C
IBInput Bias Current 0V ≤VCM ≤5V 110 140 180 nA
300 350 max
IOS Input Offset Current 3.4 30 30 nA
50 50 max
RIN Input Resistance, CM 104 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤4V 100 75 75
70 70 dB
min
0V ≤VCM ≤5V 80 60 60
55 55
PSRR Power Supply Rejection Ratio ±2.5V ≤V+≤±12V 82 78 78 dB
75 75 min
VCM −0.25 0 0
Input Common-Mode Voltage Range V
5.25 5.0 5.0
AVLarge Signal Voltage Gain RL= 10k 100 25 15 V/mV
8 6 min
VOOutput Swing 100k Load 4.992 4.98 4.98 V
4.93 4.93 min
0.007 0.017 0.017 V
0.019 0.019 max
10k Load 4.952 4.94 4.94 V
4.85 4.85 min
0.032 0.07 0.07 V
0.09 0.09 max
5k Load 4.923 4.90 4.90 V
4.85 4.85 min
0.051 0.095 0.095 V
0.12 0.12 max
ISC Output Short Circuit Current Sourcing 4 2 2 mA
LM6132 2 1 min
Sinking 3.5 1.8 1.8 mA
1.8 1 min
ISC Output Short Circuit Current Sourcing 3 2 2 mA
LM6134 1.6 1 min
Sinking 3.5 1.8 1.8 mA
1.3 1 min
ISSupply Current Per Amplifier 400 400 μA
360 450 450 max
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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5.0V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5.0V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
Boldface limits apply at the temperature extremes LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
SR Slew Rate ±4V @ VS= ±6V 8 8 V/μs
14
RS< 1 kΩ7 7 min
GBW Gain-Bandwidth Product f = 20 kHz 7.4 7.4 MHz
10 7 7 min
θm Phase Margin RL= 10k 33 deg
GmGain Margin RL= 10k 10 dB
enInput Referred Voltage Noise f = 1 kHz 27 nV/√Hz
inInput Referred Current Noise f = 1 kHz 0.18 pA/√Hz
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
2.7V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
Boldface limits apply at the temperature extreme LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
VOS Input Offset Voltage 0.12 2 6 mV
8 12 max
IBInput Bias Current 0V ≤VCM ≤2.7V 90 nA
IOS Input Offset Current 2.8 nA
RIN Input Resistance 134 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤2.7V 82 dB
PSRR Power Supply Rejection Ratio ±1.35V ≤V+≤±12V 80 dB
VCM Input Common-Mode Voltage Range 2.7 2.7 V
0 0
AVLarge Signal Voltage Gain RL= 10k 100 V/mV
VOOutput Swing RL= 100k 0.08 0.08 V
0.03 0.112 0.112 max
2.65 2.65 V
2.66 2.25 2.25 min
ISSupply Current Per Amplifier 330 μA
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
GBW Gain-Bandwidth Product RL= 10k, f = 20 kHz 7 MHz
θmPhase Margin RL= 10k 23 deg
GmGain Margin 12 dB
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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24V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 24V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
Boldface limits apply at the temperature extreme LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
VOS Input Offset Voltage 1.7 3 7 mV
5 9 max
IBInput Bias Current 0V ≤VCM ≤24V 125 nA
IOS Input Offset Current 4.8 nA
RIN Input Resistance 210 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤24V 80 dB
PSRR Power Supply Rejection Ratio 2.7V ≤V+≤24V 82 dB
VCM Input Common-Mode Voltage Range −0.25 0 0 V min
24.25 24 24 V max
AVLarge Signal Voltage Gain RL= 10k 102 V/mV
VOOutput Swing RL= 10k V
max
0.075 0.15 0.15
23.86 23.8 23.8 V
min
ISSupply Current Per Amplifier 450 450 μA
390 490 490 max
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
24V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 24V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
LM6134AI LM6134BI
Typ LM6132AI LM6132BI
Symbol Parameter Conditions Units
(1) Limit Limit
(2) (2)
GBW Gain-Bandwidth Product RL= 10k, f = 20 kHz 11 MHz
θmPhase Margin RL= 10k 23 deg
GmGain Margin RL= 10k 12 dB
THD + N Total Harmonic Distortion and Noise AV= +1, VO= 20VP-P 0.0015 %
f = 10 kHz
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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Typical Performance Characteristics
TA= 25°C, RL= 10 kΩunless otherwise specified
Supply Current Offset Voltage
vs. vs.
Supply Voltage Supply Voltage
Figure 3. Figure 4.
dVOS dVOS
vs. vs.
VCM VCM
Figure 5. Figure 6.
dVOS IBIAS
vs. vs.
VCM VCM
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
IBIAS IBIAS
vs. vs.
VCM VCM
Figure 9. Figure 10.
Input Bias Current Negative PSRR
vs. vs.
Supply Voltage Frequency
Figure 11. Figure 12.
Positive PSSR dVOS
vs. vs.
Frequency Output Voltage
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
dVOS dVOS
vs. vs.
Output Voltage Output Voltage
Figure 15. Figure 16.
CMRR Output Voltage
vs. vs.
Frequency Sinking Current
Figure 17. Figure 18.
Output Voltage Output Voltage
vs. vs.
Sinking Current Sinking Current
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Output Voltage Output Voltage
vs. vs.
Sourcing Current Sourcing Current
Figure 21. Figure 22.
Output Voltage Noise Voltage
vs. vs.
Sourcing Current Frequency
Figure 23. Figure 24.
Noise Current NF
vs. vs.
Frequency Source Resistance
Figure 25. Figure 26.
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Gain and Phase Gain and Phase
vs. vs.
Frequency Frequency
Figure 27. Figure 28.
Gain and Phase GBW
vs. vs.
Frequency Supply Voltage at 20 kHz
Figure 29. Figure 30.
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LM6132/34 APPLICATION INFORMATION
The LM6132 brings a new level of ease of use to op amp system design.
With greater than rail-to-rail input voltage range concern over exceeding the common-mode voltage range is
eliminated.
Rail-to-rail output swing provides the maximum possible dynamic range at the output. This is particularly
important when operating on low supply voltages.
The high gain-bandwidth with low supply current opens new battery powered applications, where high power
consumption, previously reduced battery life to unacceptable levels.
To take advantage of these features, some ideas should be kept in mind.
ENHANCED SLEW RATE
Unlike most bipolar op amps, the unique phase reversal prevention/speed-up circuit in the input stage eliminates
phase reversal and allows the slew rate to be very much a function of the input signal amplitude.
Figure 32 shows how excess input signal is routed around the input collector-base junctions directly to the
current mirrors.
The LM6132/34 input stage converts the input voltage change to a current change. This current change drives
the current mirrors through the collectors of Q1–Q2, Q3–Q4 when the input levels are normal.
If the input signal exceeds the slew rate of the input stage and the differential input voltage rises above a diode
drop, the excess signal bypasses the normal input transistors, (Q1–Q4), and is routed in correct phase through
the two additional transistors, (Q5, Q6), directly into the current mirrors.
This rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 31).
As the overdrive increases, the op amp reacts better than a conventional op amp. Large fast pulses will raise the
slew- rate to around 25V to 30 V/μs.
Slew Rate vs. Differential VIN
VS= ±12V
Figure 31.
This effect is most noticeable at higher supply voltages and lower gains where incoming signals are likely to be
large.
This speed-up action adds stability to the system when driving large capacitive loads.
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DRIVING CAPACITIVE LOADS
Capacitive loads decrease the phase margin of all op amps. This is caused by the output resistance of the
amplifier and the load capacitance forming an R-C phase lag network. This can lead to overshoot, ringing and
oscillation. Slew rate limiting can also cause additional lag. Most op amps with a fixed maximum slew-rate will lag
further and further behind when driving capacitive loads even though the differential input voltage raises. With the
LM6132, the lag causes the slew rate to raise. The increased slew-rate keeps the output following the input
much better. This effectively reduces phase lag. After the output has caught up with the input, the differential
input voltage drops down and the amplifier settles rapidly.
Figure 32.
These features allow the LM6132 to drive capacitive loads as large as 500 pF at unity gain and not oscillate. The
scope photos (Figure 33 and Figure 34) above show the LM6132 driving a 500 pF load. In Figure 33 , the lower
trace is with no capacitive load and the upper trace is with a 500 pF load. Here we are operating on ±12V
supplies with a 20 VPP pulse. Excellent response is obtained with a Cfof 39 pF. In Figure 34, the supplies have
been reduced to ±2.5V, the pulse is 4 VPP and CFis 39 pF. The best value for the compensation capacitor should
be established after the board layout is finished because the value is dependent on board stray capacity, the
value of the feedback resistor, the closed loop gain and, to some extent, the supply voltage.
Another effect that is common to all op amps is the phase shift caused by the feedback resistor and the input
capacitance. This phase shift also reduces phase margin. This effect is taken care of at the same time as the
effect of the capacitive load when the capacitor is placed across the feedback resistor.
The circuit shown in Figure 35 was used for these scope photos.
Figure 33.
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Figure 34.
Figure 35.
Figure 36 shows a method for compensating for load capacitance (CO) effects by adding both an isolation
resistor ROat the output and a feedback capacitor CFdirectly between the output and the inverting input pin.
Feedback capacitor CFcompensates for the pole introduced by ROand CO, minimizing ringing in the output
waveform while the feedback resistor RFcompensates for dc inaccuracies introduced by RO. Depending on the
size of the load capacitance, the value of ROis typically chosen to be between 100Ωto 1 kΩ.
Figure 36.
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Typical Applications
3 OP AMP INSTRUMENTATION AMP WITH RAIL-TO-RAIL INPUT AND OUTPUT
Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made.
These features make these instrumentation amplifiers ideal for single supply systems.
Some manufacturers use a precision voltage divider array of 5 resistors to divide the common-mode voltage to
get an input range of rail-to-rail or greater. The problem with this method is that it also divides the signal, so to
even get unity gain, the amplifier must be run at high closed loop gains. This raises the noise and drift by the
internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMR
as well. Using the LM6134, all of these problems are eliminated.
In this example, amplifiers A and B act as buffers to the differential stage (Figure 37). These buffers assure that
the input impedance is over 100 MΩand they eliminate the requirement for precision matched resistors in the
input stage. They also assure that the difference amp is driven from a voltage source. This is necessary to
maintain the CMR set by the matching of R1–R2 with R3–R4.
Figure 37.
FLAT PANEL DISPLAY BUFFERING
Three features of the LM6132/34 make it a superb choice for TFT LCD applications. First, its low current draw
(360 μA per amplifier @ 5V) makes it an ideal choice for battery powered applications such as in laptop
computers. Second, since the device operates down to 2.7V, it is a natural choice for next generation 3V TFT
panels. Last, but not least, the large capacitive drive capability of the LM6132 comes in very handy in driving
highly capacitive loads that are characteristic of LCD display drivers.
The large capacitive drive capability of the LM6132/34 allows it to be used as buffers for the gamma correction
reference voltage inputs of resistor-DAC type column (Source) drivers in TFT LCD panels. This amplifier is also
useful for buffering only the center reference voltage input of Capacitor-DAC type column (Source) drivers such
as the LMC750X series.
Since for VGA and SVGA displays, the buffered voltages must settle within approximately 4 μs, the well known
technique of using a small isolation resistor in series with the amplifier's output very effectively dampens the
ringing at the output.
With its wide supply voltage range of 2.7V to 24V), the LM6132/34 can be used for a diverse range of
applications. The system designer is thus able to choose a single device type that serves many sub-circuits in
the system, eliminating the need to specify multiple devices in the bill of materials. Along with its sister parts, the
LM6142 and LM6152 that have the same wide supply voltage capability, choice of the LM6132 in a design
eliminates the need to search for multiple sources for new designs.
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REVISION HISTORY
Changes from Revision C (February 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM6132AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61
32AIM
LM6132AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61
32AIM
LM6132AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61
32AIM
LM6132AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61
32AIM
LM6132BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61
32BIM
LM6132BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61
32BIM
LM6132BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61
32BIM
LM6132BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM61
32BIM
LM6132BIN NRND PDIP P 8 40 TBD Call TI Call TI -40 to 85 LM6132
BIN
LM6132BIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LM6132
BIN
LM6134AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134AIM
LM6134AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM
LM6134AIMX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LM6134AIM
LM6134AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134AIM
LM6134BIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134BIM
LM6134BIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM
LM6134BIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM6134BIM
LM6134BIN NRND PDIP NFF 14 25 TBD Call TI Call TI -40 to 85 LM6134BIN
LM6134BIN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LM6134BIN
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM6132AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6134AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LM6134AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LM6134BIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM6132AIMX SOIC D 8 2500 367.0 367.0 35.0
LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM6132BIMX SOIC D 8 2500 367.0 367.0 35.0
LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM6134AIMX SOIC D 14 2500 367.0 367.0 35.0
LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
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