CY2305
CY2309
Low-Cost 3.3V Zero Delay Buffer
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document #: 38-07140 Rev. *I Revised September 18, 2008
Features
10 MHz to 100-/133 MHz operating range, compatible with CPU
and PCI bus frequencies
Zero input-output propagation delay
60 ps typical cycle-to-cycle jitter (high drive)
Multiple low-skew outputs
85 ps typical output-to-output skew
One input drives five outputs (CY2305)
One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
Compatible with Pentium-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309 only
[see “Select Input Decoding” on page 3])
Available in space-saving 16-pin 150-mil SOIC or 4.4-mm
TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package
(CY2305)
3.3V operat i o n
Industrial temperature available
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at up
to 100-/133 MHz frequencies, and have higher drive than the -1
devices. All part s have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 3. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the input
clock to be directly applied to the outputs for chip and system
testing purposes.
The CY2305 and CY2309 PLLs enter a power down mode when
there are no rising edges on the REF input. In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25.0 μA current draw for these parts. The CY2309 PLL
shuts down in one additional case as shown in the table below.
Multiple CY2305 and CY2309 devices can accept the same input
clock and distribute it. In this case, the skew between the outputs
of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two/three different
configurations, as shown in the ordering informa tion (page 10).
The CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
Logic Block Diagram
PLL MUX
Select Input
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
CLKOUT
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 2 of 15
Pinouts
Figure 1. Pin Diagram - CY2305
Figure 2. Pin Diagram - CY2309
Table 1. Pin Description for CY2305
Pin Signal Description
1REF[1] Input reference frequency, 5V-tolerant inp ut
2CLK2[2] Buffered clock output
3CLK1[2] Buffered clock output
4 GND Ground
5CLK3[2] Buffered clock output
6V
DD 3.3V supply
7CLK4[2] Buffered clock output
8 CLKOUT[2] Buffered clock output, internal feedback on this pin
Table 2. Pin Description for CY2309
Pin Signal Description
1REF[1] Input reference freque ncy, 5V-tolerant input
2CLKA1[2] Buffered clock output, Bank A
3CLKA2[2] Buffered clock output, Bank A
4V
DD 3.3V supply
5 GND Ground
6CLKB1[2] Buffered clock output, Bank B
7CLKB2[2] Buffered clock output, Bank B
8S2[3] Select input, bit 2
9S1[3] Select input, bit 1
10 CLKB3[2] Buffered clock output, Bank B
11 CLKB4[2] Buffered clock output, Bank B
12 GND Ground
1
2
3
45
8
7
6
REF
CLK2
CLK1
GND V
DD
CLKOUT
CLK4
CLK3
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Notes
1. Weak pull down.
2. Weak pull down on all out puts.
3. Weak pull ups on these inputs.
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 3 of 15
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input-output delay. Thi s is shown in the above graph.
For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not
used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate loading differences betwe en the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers.”
13 VDD 3.3V supply
14 CLKA3[2] Buffered clock output, Bank A
15 CLKA4[2] Buffered clock output, Bank A
16 CLKOUT[2] Buffered output, internal feedback on this pin
Select Input Decoding for CY2309
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT[4] Output Source PLL Shutdown
0 0 Three-state Three-state Driven PLL N
0 1 Driven Three-state Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
Table 2. Pin Description for CY2309
Pin Signal Description
Notes
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 4 of 15
Absolute Maximum Conditions
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
DC Input Voltage REF............... .. ........................–0.5V to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................> 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial T emperature Devices
Parameter Description Min Max Unit
VDD Supply Voltage 3.0 3.6 V
TAOperating Temperature (Ambient Temperature) 0 70 °C
CLLoad Capacitance, below 100 MHz 30 pF
CLLoad Capacitance, from 100 MHz to 133 MHz 10 pF
CIN Input Capacitance 7 pF
tPU Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic) 0.05 50 ms
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature
Devices
Parameter Description Test Conditions Min Max Unit
VIL Input LOW Voltage[5] –0.8V
VIH Input HIGH Voltage[5] 2.0 V
IIL Input LOW Current VIN = 0V 50.0 μA
IIH Input HIGH Current VIN = VDD –100.0μA
VOL Output LOW Voltage[6] IOL = 8 mA (–1)
IOH = 12 mA (–1H) –0.4V
VOH Output HIGH Voltage[6] IOH = –8 mA (–1)
IOL = –12 mA (–1H) 2.4 V
IDD (PD mode) Power Down Supply Current REF = 0 MHz 25.0 μA
IDD Supply Current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD 32.0 mA
Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature
Devices
Parameter[7] Name Test Conditions Min Typ. Max Unit
t1 Output Frequency 30-pF load
10 pF load 10
10 100
133.33 MHz
MHz
tDC Duty Cycle[6] = t2 ÷ t1Measured at 1.4V, Fout = 66.67
MHz 40.0 50.0 60.0 %
t3 Rise Time[6] Measured between 0.8V and
2.0V 2.50 ns
t4Fall Time[6] Measured between 0.8V and
2.0V 2.50 ns
t5Output to Output Skew[6] All outputs equally loaded 85 250 ps
t6A Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2 0 ±350 ps
Notes
5. REF input has a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 5 of 15
t6B Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309
device only.
158.7 ns
t7Device to Device Skew[6] Measured at VDD/2 on the
CLKOUT pins of devices 700 ps
tJCycle to Cycle Jitter[6] Measured at 66.67 MHz, loaded
outputs 70 200 ps
tLOCK PLL Lock Time[6] Stable power supply, valid clock
presented on REF pin ––1.0 ms
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature
Devices
Parameter[7] Name Description Min Typ. Max Unit
t1 Output Frequency 30 pF load
10 pF load 10
10 –100
133.33 MHz
MHz
tDC Duty Cycle[6] = t2 ÷ t1Measured at 1.4V, Fout = 66.67 MHz 40.0 50.0 60.0 %
t3 Rise Time[6] Measured between 0.8V and 2.0V 1.50 ns
t4Fall Time[6] Measured between 0.8V and 2.0V 1.50 ns
t5Output to Output Skew[6] All outputs equally loaded 85 250 ps
t6A Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2 ±350 ps
t6B Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2. Measured in
PLL Bypass Mode, CY2309 device
only.
158.7ns
t7Device to Device Skew[6] Measured at VDD/2 on the CLKOUT
pins of devices ––700ps
t8Output Slew Rate[6] Measured between 0.8V and 2.0V
using Test Circuit #2 1– V/ns
tJCycle to Cycle Jitter[6] Measured at 66.67 MHz, loaded
outputs –60200ps
tLOCK PLL Lock Time[6] Stable power supply, valid clock
presented on REF pin ––1.0ms
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter Description Min Max Unit
VDD Supply Voltage 3.0 3.6 V
TAOperating Temperature (Ambient Temperature) –40 85 °C
CLLoad Capacitance, below 100 MHz 30 pF
CLLoad Capacitance, from 100 MHz to 133 MHz 10 pF
CIN Input Capacitance 7 pF
Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature
Devices
Parameter[7] Name Test Conditions Min Typ. Max Unit
Note
7. All parameters specified with loaded outputs.
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 6 of 15
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter Description Test Conditions Min Max Unit
VIL Input LOW Voltage[5] –0.8V
VIH Input HIGH Voltage[5] 2.0 V
IIL Input LOW Current VIN = 0V 50.0 μA
IIH Input HIGH Current VIN = VDD –100.0μA
VOL Output LOW Voltage[6] IOL = 8 mA (–1)
IOH =12 mA (–1H) –0.4V
VOH Output HIGH Voltage[6] IOH = –8 mA (–1)
IOL = –12 mA (–1H) 2.4 V
IDD (PD mode) Power down Supply Current REF = 0 MHz 25.0 μA
IDD Supply Current Unloaded outputs at 66.67
MHz, SEL inputs at VDD 35.0 mA
Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter[7] Name Test Conditions Min Typ. Max Unit
t1 Output Frequency 30 pF load
10 pF load 10
10 –100
133.33 MHz
MHz
tDC Duty Cycle[6] = t2 ÷ t1Measured at 1.4V, Fout = 66.67 MHz 40.0 50.0 60.0 %
t3 Rise Time[6] Measured between 0.8V and 2.0V 2.50 ns
t4Fall Time[6] Measured between 0.8V and 2.0V 2.50 ns
t5Output to Output Skew[6] All outputs equally loaded 85 250 ps
t6A Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2 ±350 ps
t6B Delay, REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2. Measured in PLL
Bypass Mode, CY2309 device only. 158.7ns
t7Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins
of devices ––700ps
tJCycle to Cycle Jitter[6] Measured at 66.67 MHz, loaded outputs 70 200 ps
tLOCK PLL Lock Time[6] Stable power supply, valid clock
presented on REF pin ––1.0ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial T emperature Devices
Parameter[7] Name Description Min Typ. Max Unit
t1Output Frequency 30 pF load
10 pF load 10
10 –100
133.33 MHz
MHz
tDC Duty Cycle[6] = t2 ÷ t1Measured at 1.4V, Fout = 66.67 MHz 40.0 50.0 60.0 %
t3Rise Time[6] Measured between 0.8V and 2.0V 1.50 ns
t4Fall Time[6] Measured between 0.8V and 2.0 V 1.50 ns
t5Output to Output Skew[6] All outputs equally loaded 85 250 ps
t6A Delay , REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2 ±350 ps
t6B Delay , REF Rising Edge to
CLKOUT Rising Edge[6] Measured at VDD/2. Measure d in PLL
Bypass Mode, CY2309 device only. 158.7ns
t7Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins
of devices ––700ps
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 7 of 15
t8Output Slew Rate[6] Measured between 0.8V and 2.0V using
Test Circuit #2 1–V/ns
tJCycle to Cycle Jitter[6] Measured at 66.67 MHz, loaded outputs 60 200 ps
tLOCK PLL Lock Time[6] Stable power supply, valid clock
presented on REF pin ––1.0ms
Switching Waveforms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial T emperature Devices
Parameter[7] Name Description Min Typ. Max Unit
t1
t2
1.4V 1.4V 1.4V
Figure 4. Duty Cycle Timing
OUTPUT
t3
3.3V
0V
0.8V
2.0V 2.0V
0.8V
t4
Figure 5. All Outputs Rise/Fall Time
1.4V
1.4V
t5
OUTPUT
OUTPUT
Figure 6. Output-Out put Skew
VDD/2
t6
INPUT
OUTPUT
VDD/2
Figure 7. Input-Outp ut Prop agation Delay
VDD/2
VDD/2
t7
CLKOUT, Device 1
CLKOUT, Device 2
Figure 8. Device-Device Skew
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 8 of 15
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1 and CY2309-1
Dut y Cy cle Vs VD D
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
D uty C ycle (%)
33 MHz
66 MHz
100 M Hz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Fre que ncy (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Number of L oa ded O utput s
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
Notes
8. Duty Cycle is taken from t ypical chip measured at 1.4V.
9. IDD dat a is calculated from IDD = I CORE + nCVf , where ICORE is the unloade d current. (n = # of output s; C = Cap acit a nce load per outp ut (F); V = Supply Voltage (V);
f = frequency (Hz)).
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 9 of 15
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H
Dut y Cy cle Vs VD D
(for 30 pF L oads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 MHz
66 MHz
100 M Hz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (%)
33 M Hz
66 M Hz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Fre quency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
Duty Cyc le V s Frequency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Freque ncy (MHz)
Du ty Cy cl e (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loa ds over Frequency - 3.3V , 25C)
0
20
40
60
80
100
120
140
160
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V , 25C)
0
20
40
60
80
100
120
140
160
0123456789
# of Loaded Outputs
IDD (mA)
33 MHz
66 MHz
100 MHz
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 10 of 15
Test Circuits
Ordering Information for CY2305
Ordering Code Package Type Operating Range
CY2305SC-1[10] 8-pin 150-mil SOIC Commercial
CY2305SC-1T[10] 8-pin 150-mil SOIC – Tape and Reel Commercial
CY2305SI-1[10] 8-pin 150-mi l SOIC Industrial
CY2305SI-1T[10] 8-pin 150-mil SOIC – Tape and Reel Industrial
CY2305SC-1H[10] 8-pin 150-mil SOIC Commercial
CY2305SC-1HT[10] 8-pin 150-mil SOIC – Tape and Reel Commercial
CY2305SI-1H[10] 8-pin 150-mi l SOIC Industrial
CY2305SI-1HT[10] 8-pin 150-mil SOIC – Tape and Reel Industrial
Pb-Free
CY2305SXC-1 8-pin 150-mil SOIC Commercial
CY2305SXC-1T 8-pin 150-mil SOIC – Tape and Reel Commercial
CY2305SXI-1 8-pin 150-mil SOIC Industrial
CY2305SXI-1T 8-pin 150-mil SOIC – Tape and Reel Industrial
CY2305SXC-1H 8-pin 150-mil SOIC Commercial
CY2305SXC-1HT 8-pin 150-mil SOIC – Tape and Reel Commercial
CY2305SXI-1H 8-pin 150-mil SOIC Industrial
CY2305SXI-1HT 8-pin 150-mil SOIC – Tape and Reel Industrial
Ordering Information for CY2309
Ordering Code Package Type Operating Range
CY2309SC-1[10] 16-pin 150-mil SOIC Commercial
CY2309SC-1T[10] 16-pin 150-mil SOIC – Tape and Reel Commercial
CY2309SI-1[10] 16-pin 150-mil SOIC Industrial
CY2309SI-1T[10] 16-pin 150-mil SOIC – Tape and Reel Industrial
CY2309SC-1H[10] 16-pin 150-mil SOIC Commercial
0.1 μF
VDD
0.1 μF
VDD
CLK out
CLOAD
OUTPUTS
GNDGND
0.1 μF
VDD
0.1 μF
VDD
10 pF
OUTPUTS
GND
GND
1 kΩ
1 kΩ
Test Circuit # 1 Test Circuit # 2
For parameter t8 (output slew rate) on -1H devices
Note
10.Not recommended for new designs.
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 11 of 15
CY2309SC-1HT[10] 16-pin 150-mil SOIC – Tape an d Reel Commercial
CY2309ZC-1H[10] 16-pin 4.4-mm TSSOP Commercial
CY2309ZC-1HT[10] 16-pin 4.4-mm TSSOP – Tape and Reel Commercial
CY2309SI-1H[10] 16-pin 150-mil SOIC Industrial
CY2309SI-1HT[10] 16-pin 150-mil SOIC – Tape and Reel Industrial
Pb-Free
CY2309SXC-1 16-pin 150-mil SOIC Commercial
CY2309SXC-1T 16-pin 150-mil SOIC – Tape and Reel Commercial
CY2309SXI-1 16-pin 150-mil SOIC Industrial
CY2309SXI-1T 16-pin 150-mil SOIC – Tape and Reel Industrial
CY2309SXC-1H 16-pin 150-mil SOIC Commercial
CY2309SXC-1HT 16-pin 150-mil SOIC – Tape and Reel Commercial
CY2309SXI-1H 16-pin 150-mil SOIC Industrial
CY2309SXI-1HT 16-pin 150-mil SOIC – Tape an d Reel Industrial
CY2309ZXC-1H 16-pin 4.4-mm TSSOP Commercial
CY2309ZXC-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Commercial
CY2309ZXI-1H 16-pin 4.4-mm TSSOP Industrial
CY2309ZXI-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Industrial
Ordering Information for CY2309 (continued)
Ordering Code Package Type Operating Range
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 12 of 15
Package Drawing and Dimensions
SEATING PLANE
PIN1ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
~8°
0.016[0.406]
0.010[0.254] X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
8 Lead (150 Mil) SOIC - S08
14
58
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066-*C
Figure 8. 8-Pin (150-Mil) SOIC S8
PIN 1 ID
~8°
16 Lead (150 Mil) SOIC
18
916
SEATING PLANE
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.386[9.804]
0.393[9.982]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.016[0.406]
0.010[0.254] X 45°
0.004[0.102]
REFERENCE JEDEC MS-012
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
PACKAGE WEIGHT 0.15gms
51-85068-*B
Figure 9. 16-Pin (150-Mil) SOIC S16
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 13 of 15
Package Drawing and Dimensions (continued)
4.90[0.193]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
16
PIN1ID
6.50[0.256]
SEATING
PLANE
1
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
BSC.
5.10[0.200]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
BSC
0.25[0.010]
-8°
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
PLANE
GAUGE
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
51-85091-*A
Figure 10. 16-Pin TSSOP 4.40 MM Body Z16.173
[+] Feedback
CY2305
CY2309
Document #: 38-07140 Rev. *I Page 14 of 15
Document History Page
Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer
Document Number: 38-07140
REV. ECN Orig. of
Change Submission
Date Description of Change
** 110249 SZV 10/19/01 Change from Spec number: 38-00530 to 38-07140
*A 111117 CKN 03/01/02 Added t6B row to the Switching Characteristics Table; also added the letter
“A” to the t6A row
Corrected the table title from CY2305SC-IH and CY23 09SC-IH to
CY2305SI-IH and CY2309SI-IH
*B 117625 HWT 10/21/02 Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the
ordering information table.
Added the Tape and Reel option to all the existing packages:
CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT,
CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT,
CY2309SI-1HT, CY2309ZC-1HT, CY23 09ZI-1HT
*C 121828 RBI 12/14/02 Po wer up requirements added to Operating Conditions information
*D 131503 RGL 12/12/03 Added Lead-free for all the devices in the ordering informa tion table
*E 214083 RGL See ECN Added a Lead-free with the new coding for all SOIC devices in the ordering
information table
*F 291099 RGL See ECN A dded TSSOP Lead-free devices
*G 390582 RGL See ECN Added typical values for jitter
*H 2542461 AESA 07/23/08 Updated template. Added Note “Not recommended for new designs.”
Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1,
CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H,
CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1,
CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H,
CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT , CY2309EZXI-1H,
and CY2309EZXI-1HT in orderi ng information table.
Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1,
CY2305SZI-1T, CY2305SZC-1H, CY2305SZC-1H T, CY230 5SZI-1H,
CY2305SZI-1HT, CY2309SZC-1, CY2309SZC-1T, CY2309SZI-1,
CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1H T, CY230 9SZI-1H,
CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H,
CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering
Information table.
Changed Lead-Free to Pb-Free.
*I 2565153 AESA 09/18/08 Removed part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1,
CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H,
CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1,
CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H,
CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT , CY2309EZXI-1H,
and CY2309EZXI-1HT in orderi ng information table.
Removed note references to note 10 in Pb-Free sections of ordering infor-
mation table.
Changed IDD (PD mode) from 12.0 to 25.0 μA for commercial temperature
devices
Deleted Du ty Cycle pa rameters for Fout < 50 MHz commercial and industrial
devices.
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Document #: 38-07140 Rev. *I Revised September 18, 2008 Page 15 of 15
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CY2305
CY2309
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