1
®
FN6099.1
ISL84780
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Quad 2:1 Analog
Multiplexer
The Intersil ISL84780 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.6V to +3.6V
supply. Targeted applications include battery-powered
equipment that benefit from low on-resistance, and fast
switching speeds (tON =12ns, t
OFF = 8ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This family of parts may be used to
“mux-in” additional functionality while reducing ASIC design
risk. The ISL84780 is offered in small form factor packages,
alleviating board space limitations.
The ISL84780 is a committed Quad SPDT that consists of
four normally open (NO) and four normally closed (NC)
switches. This configuration can also be used as a diff dual 2-
to-1 multiplexer/demultiplexer or a quad 2-to1
multiplexer/demultiplexer. The ISL84780 is pin compatible
with the MAX4780.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Features
• Pin Compatible Replacement for the MAX4780
• ON Resistance (RON)
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.36Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54Ω
•R
ON Matching between Channels . . . . . . . . . . . . . . . . .0.13Ω
•R
ON Flatness Across Signal Range . . . . . . . . . . . . . . .0.05Ω
• Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW
• Fast Switching Action
-t
ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
-t
OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Available in 16 lead 3x3 thin QFN and 16 lead TSSOP
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free Available (RoHS Compliant)
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
TABLE 1. FEATURES AT A GLANCE
ISL84780
Number of Switches 4
SW Quad SPDT (Dual DPDT)
3.0V RON 0.36Ω
3.0V tON/tOFF 12ns/8ns
1.8V RON 0.54Ω
1.8V tON/tOFF 19ns/11ns
Packages 16Ld 3x3 TQFN, 16Ld TSSOP
Data Sheet
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
December 27, 2004
2FN6099.1
December 27, 2004
Pinouts (Note 1)
ISL84780 (TSSOP)
TOP VIEW
ISL84780 (3X3 THIN QFN)
TOP VIEW
NOTE:
1. Switches Shown for Logic “0” Input.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
NO1
COM1
NC1
IN1-2
NO2
COM2
GND
NC2
V+
COM4
NO4
IN3-4
NC3
COM3
NO3
NC4
1
3
4
1516 14 13
2
12
10
9
11
6578
NO1
COM1
NC2
NO2
NC1
IN1-2
V+
IN3-4
NC4
NO4
COM4
NC3
COM2
GND
COM3
NO3
Ordering Information
PART NO.
(BRAND)
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
ISL84780IR
(780I)
-40 to 85 16 Ld 3x3 Thin QFN L16.3x3A
ISL84780IR-T
(780I)
-40 to 85 16 Ld 3x3 Thin QFN
Tape and Reel
L16.3x3A
ISL84780IRZ
(780I) (Note)
-40 to 85 16 Ld 3x3 Thin QFN
(Pb-free)
L16.3x3A
ISL84780IRZ-T
(780I) (Note)
-40 to 85 16 Ld 3x3 Thin QFN
Tape and Reel (Pb-free)
L16.3x3A
ISL84780IV
(84780IV)
-40 to 85 16 Ld TSSOP M16.173
ISL84780IV-T
(84780IV)
-40 to 85 16 Ld TSSOP
Tape and Reel
M16.173
ISL84780IVZ
(84780IV) (Note)
-40 to 85 16 Ld TSSOP
(Pb-free)
M16.173
ISL84780IVZ-T
(84780IV) (Note)
-40 to 85 16 Ld TSSOP
Tape and Reel (Pb-free)
M16.173
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Truth Table
LOGIC NC SW NO SW
0ONOFF
1OFFON
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
PIN FUNCTION
V+ System Power Supply Input (+1.6V to +3.6V)
GND Ground Connection
IN Digital Control Input
COM Analog Switch Common Pin
NO Analog Switch Normally Open Pin
NC Analog Switch Normally Closed Pin
ISL84780
3FN6099.1
December 27, 2004
Absolute Maximum Ratings Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Resistance (Typical, Note 3) θJA (°C/W)
16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN TYP
(NOTE 5)
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
25 - 0.4 0.6 Ω
Full - - 0.7 Ω
RON Matching Between Channels,
∆RON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max RON, (Note 9)
25 - 0.13 0.2 Ω
Full - - 0.2 Ω
RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 7)
25 - 0.05 0.15 Ω
Full - - 0.15 Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 -3 - 3 nA
Full -20 - 20 nA
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or Floating
25 -4 - 4 nA
Full -30 - 30 nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
25 - 12 20 ns
Full - - 25 ns
Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1, Note 8)
25 - 8 14 ns
Full - - 17 ns
Break-Before-Make Time Delay, tDV+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3, Note 8)
Full 1 3 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -97 - pC
OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25 - 68 - dB
Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25 - -98 - dB
Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P
, RL = 32Ω25 - 0.002 - %
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 62 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 125 - pF
ISL84780
4FN6099.1
December 27, 2004
POWER SUPPLY CHARACTERISTICS
Power Supply Range Full 1.6 - 3.6 V
Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 - - 0.05 µA
Full - - 1.5 µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL Full - - 0.5 V
Input Voltage High, VINH Full 1.4 - - V
Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ (Note 8) Full -0.5 - 0.5 µA
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed not tested.
9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4, 6),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN TYP
(NOTE 5)
MAX UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - V+ V
ON Resistance, RON V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
See Figure 5
25 - 0.54 0.9 Ω
Full - - 1 Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8
25 - 19 25 ns
Full - - 30 ns
Turn-OFF Time, tOFF V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 1, Note 8
25 - 11 17 ns
Full - - 22 ns
Break-Before-Make Time Delay, tDV+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
See Figure 3, Note 8
Full 1 5 - ns
Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - -52 - pC
OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 4
25 - 68 - dB
Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
See Figure 6
25 - -98 - dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 62 - pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 125 - pF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL Full - - 0.4 V
Input Voltage High, VINH Full 1.0 - - V
Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 8) Full -0.05 - 0.05 µA
Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN TYP
(NOTE 5)
MAX UNITS
ISL84780
5FN6099.1
December 27, 2004
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
FIGURE 3A. MEASUREMENT POINTS
CL includes fixture and stray capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
50%
tr < 5ns
tf < 5ns
tOFF
90%
V+
0V
VNO
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
VOUT V(NO or NC)
RL
RLRON()
+
------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL CL
COM
NO or NC
IN
50Ω35pF
GND
V+ C
VOUT
∆VOUT
ON OFF ON
Q = ∆VOUT x CL
SWITCH
OUTPUT
LOGIC
INPUT
V+
0V
CL
VOUT
RG
VGGND
COM
NO or NC
V+ C
LOGIC
INPUT
IN
90%
V+
0V
tD
LOGIC
INPUT
SWITCH
OUTPUT 0V
VOUT
LOGIC
INPUT
IN
COM
RLCL
VOUT
35pF
50Ω
NO
NC
V+
GND
VNX
C
ISL84780
6FN6099.1
December 27, 2004
Detailed Description
The ISL84780 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.6V to 3.6V supply with low on-
resistance (0.36Ω) and high speed operation (tON = 12ns,
tOFF = 8ns). The device is especially well suited for portable
battery-powered equipment due to its low operating supply
voltage (1.6V), low power consumption (5.4µW max), low
leakage currents (30nA max), and the tiny TQFN and TSSOP
packages. The ultra low on-resistance and Ron flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ resistor
in series with the input (See Figure 8). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (See Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch signal range is
reduced and the resistance may increase, especially at low
supply voltages.
FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
ANALYZER
RL
SIGNAL
GENERATOR
V+ C
0V or V+
NO or NC
COM
IN
GND
V+
C
0V or V+
NO or NC
COM
IN
GND
VNX
V1
RON = V1/1mA
1mA
0V or V+
ANALYZER
V+
C
NO or NC
SIGNAL
GENERATOR
RLGND
IN1
COM 50Ω
N.C.
COM NC or NO
V+ C
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or V+
ISL84780
7FN6099.1
December 27, 2004
Power-Supply Considerations
The ISL84780 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL84780 4.7V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V
the VIH level is about 1.27V. This is still below the 1.8V
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 104MHz (See
Figure 15). The frequency response is very consistent over a
wide V+ range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from the switch input to its output. Off Isolation
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 16 details the high Off Isolation and
Crosstalk rejection provided by this part. At 100kHz, Off
Isolation is about 68dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One
of these diodes conducts if any analog signal exceeds V+
or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
FIGURE 8. OVERVOLTAGE PROTECTION
GND
VCOM
VNO or NC
OPTIONAL PROTECTION
V+
INX
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
ISL84780
8FN6099.1
December 27, 2004
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE
RON (Ω)
VCOM (V)
01234
ICOM = 100mA
0.3
0.35
0.4
0.45
0.5
0.55
V+ = 3V
V+ = 2.7V
V+ = 1.8V
V+ = 3.6V
RON (Ω)
VCOM (V)
00.511.522.53
V+ = 3V
ICOM = 100mA
0.25
0.3
0.35
0.4
25°C
85°C
-40°C
0 0.5 1 1.5 2
RON (Ω)
VCOM (V)
85°C
-40°C
V+ = 1.8V
ICOM = 100mA
25°C
0.3
0.35
0.4
0.45
0.5
0.55
0.6
00.511.522.53
Q (pC)
VCOM (V)
-150
-100
-50
0
50
100
V+ = 1.8V
V+ = 3V
tON (ns)
V+ (V)
11.522.533.544.5
0
10
20
30
40
50
85°C
-40°C
25°C
tOFF (ns)
V+ (V)
11.522.533.544.5
0
5
10
15
20
25°C
85°C
-40°C
ISL84780
9FN6099.1
December 27, 2004
FIGURE 15. FREQUENCY RESPONSE FIGURE 16. CROSSTALK AND OFF ISOLATION
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: To Ground or Float)
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
0
-20
NORMALIZED GAIN (dB)
GAIN
PHASE
V+ = 3V
0
20
40
60
80
100
PHASE (DEGREES)
1 10 100 600
VIN = 0.2VP-P to 2VP-P
RL = 50Ω
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V+ = 3V
V+ (V)
VINH AND VINL (V)
11.522.533.544.5
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
VINH
VINL
ISL84780
10 FN6099.1
December 27, 2004
ISL84780
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowab le dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004) c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
α0o8o0o8o-
Rev. 1 2/02
11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6099.1
December 27, 2004
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
)
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E
A
2X
0.15
B
C
0.10 BAMC
A
N
SEATING PLANE
N
6
3
2
2
3
e
1
1
0.08
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
CC
SECTION "C-C"
NX b
A1
C
2X
C
0.15
0.15
2X
B
0
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
4X P
A
C
C
4X P
B
2X
AC0.15
A2
A3
D2
D2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
C
LC
L
ee
E1
2
NX k
NX b
8
NX L
8
8
9
AREA
9
4X 0.10 C
/ /
9
(DATUM B)
(DATUM A)
AREA
INDEX
6
AREA
N9
CORNER
OPTION 4X
L1
L
10 L1
L
10
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.70 0.75 0.80 -
A1 - - 0.05 -
A2 - - 0.80 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5, 8
D 3.00 BSC -
D1 2.75 BSC 9
D2 1.35 1.50 1.65 7, 8, 10
E 3.00 BSC -
E1 2.75 BSC 9
E2 1.35 1.50 1.65 7, 8, 10
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N162
Nd 4 3
Ne 4 3
P- -0.609
θ--129
Rev. 0 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2
and D2 MAX dimension.
ISL84780
