www.ti.com SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 FEATURES * * * * * * DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments WidebusTM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 1Q7 GND 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2Q10 2OE DESCRIPTION This 20-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16841 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers. The SN74ALVCH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 1D7 GND 1D8 1D9 1D10 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2D10 2LE A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16841 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995-2004, Texas Instruments Incorporated SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 FUNCTION TABLE (each 10-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC SYMBOL(1) 1 1OE 1LE 56 28 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 (1) This 2 29 55 EN2 C1 EN4 C3 1D 54 2 2 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 3D 4 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2Q10 symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1 2OE 56 2LE C1 1D1 55 1D 2 28 29 C1 1Q1 2D1 To Nine Other Channels 42 15 1D 2Q1 To Nine Other Channels ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range -0.5 4.6 V range (2) -0.5 4.6 V -0.5 VCC + 0.5 VI Input voltage VO Output voltage range (2) (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through each VCC or GND JA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) V -50 mA -50 mA 50 mA 100 mA DGG package 81 DL package 74 -65 UNIT 150 C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. 3 SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current t/v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V 0.65 x VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 x VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 V 0 VCC V 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 A 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 A IOH = -12 mA II(hold) 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 1.65 V 25 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 V (2) ICC VI = VCC or GND, IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND (1) (2) Outputs V 5 VI = 1.07 V VO = VCC or GND Co 0.55 VI = 0.58 V VI = 0 to 3.6 Data inputs 0.4 3V 3.6 V IOZ Control inputs 2.7 V VI = VCC or GND VI = 2 V Ci V 1.65 V to 3.6 V IOL = 24 mA UNIT 1.2 IOL = 4 mA IOL = 12 mA II MAX VCC - 0.2 IOH = -4 mA VOH VOL MIN TYP (1) VCC A A 3.6 V 500 3.6 V 10 A 3.6 V 40 A 3 V to 3.6 V 750 A VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V 4.5 pF 6.5 7 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 1.8 V MIN MAX VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN UNIT MAX Pulse duration, LE high or low (1) 3.3 3.3 3.3 ns tsu Setup time, data before LE (1) 0.9 0.7 1.1 ns th Hold time, data after LE (1) 1.2 1.5 1.1 ns tw (1) This information was not available at the time of publication. 5 SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) FROM (INPUT) PARAMETER D tpd (1) LE TO (OUTPUT) VCC = 1.8 V Q TYP VCC = 2.5 V 0.2 V MIN VCC = 3.3 V 0.3 V VCC = 2.7 V MAX MIN MAX MIN MAX (1) 1 5 4.7 1.2 3.9 (1) 1 5.6 5.1 1 4.3 UNIT ns ten OE Q (1) 1 6.2 6 1 4.9 ns tdis OE Q (1) 1.1 5.3 4.3 1.3 4.1 ns This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25C PARAMETER Cpd (1) 6 Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF, This information was not available at the time of publication. f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 12 20 (1) 1 3 UNIT pF SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 x VCC S1 1 k From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 k S1 Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 7 SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC S1 500 From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 S1 Open 2 x VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 x VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES043E - JULY 1995 - REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 6V S1 500 From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control (low-level enabling) 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPHL tPLH 1.5 V Output Waveform 2 S1 at GND (see Note B) tPHZ 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ALVCH16841DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16841DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16841DLG4 ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16841DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16841DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16841DL ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16841DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 20 Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ALVCH16841DGGR TSSOP SN74ALVCH16841DLR SSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH16841DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74ALVCH16841DLR SSOP DL 56 1000 346.0 346.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0-8 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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