Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DMilitary Operating Temperature Range:
−55°C to 125°C
DIndustrial Operating Temperature Range:
−40°C to 85°C
DFast Instruction Cycle Time (30 ns and
40 ns) and 25 ns for Industrial Temp Range
DSource-Code Compatible With All
TMS320C1x and TMS320C2x Devices
DRAM-Based Operation
− 9K × 16-Bit Single-Cycle On-Chip
Program/Data RAM
− 1056 × 16-Bit Dual-Access On-Chip
Data RAM
D2K × 16-Bit On-Chip Boot ROM
D224K × 16-Bit Maximum Addressable
External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
D32-Bit Arithmetic Logic Unit (ALU)
− 32-bit Accumulator (ACC)
− 32-Bit Accumulator Buffer (ACCB)
D16-Bit Parallel Logic Unit (PLU)
D16 × 16-Bit Multiplier, 32-Bit Product
D11 Context-Switch Registers
DTwo Buffers for Circular Addressing
DFull-Duplex Synchronous Serial Port
DTime-Division Multiplexed Serial Port (TDM)
DTimer With Control and Counter Registers
D16 Software-Programmable Wait-State
Generators
DDivide-by-One Clock Option
DIEEE 1149.1‡ Boundary Scan Logic
DOperations Are Fully Static
DEnhanced Performance Implanted CMOS
(EPIC) Technology Fabricated by Texas
Instruments
DPackaging
− 132-Lead Plastic Quad Flat Package
(PQ Suffix)
description
The SM320C50-EP digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.72-µm double-level metal CMOS technology. The C50 is the first DSP from TI designed as
a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high
performance, making it ideal for applications such as battery-operated communications systems, satellite
systems, and advanced control algorithms.
PQ PACKAGE
(TOP VIEW)
1
17
18
117
116
50
51 83
84
132
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
Copyright 2006, Texas Instruments Incorporated
†Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡EEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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description (continued)
A number of enhancements to the basic C2x architecture give the C50 a minimum 2× performance over the
previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The
addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using
the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional
clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 µA. A low-logic
level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The SM320C50-EP is available with a clock speed of 66 MHz providing a 30-ns cycle time and a clock speed
of 80 MHz providing a 25-ns cycle time. The available options are listed in Table 1.
Table 1. Available Options
PART NUMBER SPEED SUPPLY
VOLTAGE
TOLERANCE PACKAGE
SM320C50PQM66EP 30 ns cycle time ±5% Plastic Quad flat package
SM320C50PQI80EP 25 ns cycle time ±5% Plastic Quad flat package
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functional block diagram
BMAR
MUX
PC(16)
Stack
(8 ×16)
PASR BRAF
IPTR INT# INTM IMR IFR
MP/MC CNF RAM
Program MemoryPAERCompare
BRCR
MUX
MUX
MUX
MUX
TRM
TREG0TREG1TREG2
COUNT
Prescaler
OVM SXM
Multiplier
PREG(32)
PM
P-Scaler
ALU(32)
ACC(32)ACCB(32)
Post-Scaler OV TC C
DBMR
BIM
MUX
PLU(16)
MUX
MUX
MUX
CBERMUX INDX ARCR
ARP
ARB
NDX CBSR
DP(9) dma(7)
AUXREGS
(8 × 16)
CBCR
XF
ARAU(16)
Data Memory GREG
BRCNF OVLY
Program Bus (Address) Program Bus (Data)
Data Bus (Address)
Data Bus (Data)
Data Bus (Data)
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terminal assignments
Table 2. Terminal Assignments (PQ PKG)
TERMINAL TERMINAL TERMINAL TERMINAL
NAME NO. NAME NO. NAME NO. NAME NO.
NC†18 A2 57 X2/CLKIN 96 TCLKX 123
NC†19 A3 58 X1 97 CLKX 124
VSS3 20 A4 59 VDD11 98 TFSR/TADD 125
VSS4 21 A5 60 VDD12 99 TCLKR 126
NC†22 A6 61 TDO 100 RS 127
D7 23 A7 62 VSS13 101 READY 128
D6 24 A8 63 VSS14 102 HOLD 129
D5 25 A9 64 CLKMD2 103 BIO 130
D4 26 VDD7 65 FSX 104 VDD15 131
D3 27 VDD8 66 TFSX/TFRM 105 VDD16 132
D2 28 TDI 67 DX 106 IAQ 1
D1 29 VSS9 68 TDX 107 TRST 2
D0(LSB) 30 VSS10 69 HOLDA 108 VSS1 3
TMS 31 NC†70 XF 109 VSS2 4
VDD3 32 CLKMD1 71 CLKOUT1 110 MP/MC 5
VDD4 33 A10 72 NC†111 D15(MSB) 6
TCK 34 A11 73 IACK 112 D14 7
VSS5 35 A12 74 VDD13 113 D13 8
VSS6 36 A13 75 VDD14 114 D12 9
NC†37 A14 76 NC†115 D11 10
INT1 38 A15(MSB) 77 NC†116 D10 11
INT2 39 NC†78 NC†117 D9 12
INT3 40 NC†79 EMU0 118 D8 13
INT4 41 VDD9 80 EMU1/OFF 119 VDD1 14
NMI 42 VDD10 81 VSS15 120 VDD2 15
DR 43 RD 82 VSS16 121 NC†16
TDR 44 WE 83 TOUT 122 NC†17
FSR 45 NC†84
CLKR 46 NC†85
VDD5 47 VSS11 86
VDD6 48 VSS12 87
NC†49 NC†88
NC†50 DS 89
NC†51 IS 90
NC†52 PS 91
VSS7 53 R/W 92
VSS8 54 STRB 93
A0 55 BR 94
A1 56 CLKIN2 95
†NC = No internal connection
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Terminal Functions
TERMINAL
DESCRIPTION
NAME TYPE†
DESCRIPTION
ADDRESS AND DATA BUSES
A15 (MSB)
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
I/O/Z
Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0−A15 are in the
high-impedance state in hold mode and when OFF is active (low). These signals are used as inputs for external DMA
access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low
externally.
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I/O
devices. D0−D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when
OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM.
MEMORY CONTROL SIGNALS
DS
PS
IS O/Z Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external
space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low).
READY I Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device
is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus
grant to an external device after a BR (bus request) signal.
R/W I/O/Z
Read/write. R/W indicates transfer direction during communication to an external device and is normally in read
mode (high) unless asserted for performing a write operation. R/W is in the high-impedance state in hold mode or
when OF F is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the
data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low).
STRB I/O/Z Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the
hold mode or when OFF is active (low). Used in external DMA access of the on-chip single-access RAM and while
HOLDA and IAQ are active (low), STRB is used to select the memory access.
RD O/Z Read select. RD indicates an active external read cycle and can connect directly to the output enable (OE) of external
devices. This signal is active on all external program, data, and I/O reads. RD is in the high-impedance state in hold
mode or when OFF is active (low).
†I = Input, O = Output, Z = High-Impedance
NOTE: All input pins that are unused should be connected to VDD or an external pullup resistor. The BR pin has an internal pullup for performing
DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1
require external pullups to support emulation.
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Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME TYPE†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
WE O/Z Write enable. The falling edge indicates that the device is driving the external data bus (D15−D0). Data can be
latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O
writes. WE is in the high-impedance state in hold mode or when OFF is active (low).
MULTIPROCESSING SIGNALS
HOLD I Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the C50,
these lines go to the high-impedance state.
HOLDA O/Z Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and memory control lines are in the high-impedance state so that they are available to the external
circuitry for access to local memory. This signal also goes to the high-impedance state when OFF is active (low).
BR I/O/Z
Bus request. BR is asserted during access of external global data memory space. READY is asserted when the
global data memory is available for the bus transaction. BR can be used to extend the data memory address space
by up to 32K words. BR goes to the high-impedance state when OFF is active low. BR is used in external DMA access
of the on-chip single-access RAM. While HOLDA is active (low), BR is externally driven (low) to request access to
the on-chip single-access RAM.
IAQ O/Z
Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the
high-impedance state when OFF is active (low). IAQ is also used in external DMA access of the on-chip
single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for access of the on-chip
single-access RAM and stops indicating instruction acquisition.
BIO I Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional
instruction. BIO must be active during the fetch of the conditional instruction.
XF O/Z External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status
register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose
output. XF goes to the high-impedance state when OFF is active (low) and is set high at reset.
IACK O/Z Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector
location designated by A15−A0. IACK goes to the high-impedance state when OFF is active (low).
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
INT4
INT3
INT2
INT1
IExternal interrupts. INT1−INT4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode
bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.
NMI I Nonmaskable interrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated,
the processor traps to the appropriate vector location.
RS I Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought
to a high level, execution begins at location zero of program memory.
MP/MC I
Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal
program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is
mapped externally. This signal is sampled only during reset, and the mode that is set at reset can be overridden via
the software control bit MP/MC in the PMST register.
OSCILLATOR/TIMER SIGNALS
CLKOUT1 O/Z Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine
cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF is active
(low).
†I = Input, O = Output, Z = High-Impedance
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Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME TYPE†
DESCRIPTION
OSCILLATOR/TIMER SIGNALS (CONTINUED)
CLKMD1
CLKMD2 I
CLKMD1 CLKMD2 Clock mode
0 0 External clock with divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator and PLL are disabled.
0 1 Reserved for test purposes
1 0 External divide-by-one option. Input clock is provided to CLKIN2. Internal oscillator is
disabled and internal PLL is enabled.
1 1 Internal or external divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator is enabled and internal PLL is disabled.
X2/CLKIN I Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock can be input to the
device on X2/CLKIN. The internal machine cycle is half this clock rate.
X1 O Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 must be left unconnected.
This signal does not go to the high-impedance state when OFF is active (low).
CLKIN2 I Divide-by-one input clock for driving the internal machine rate.
TOUT O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle
wide.
SUPPLY PINS
VDD1
VDD2
VDD3
VDD4
IPower supply for data bus
VDD5
VDD6 IPower supply for address bus
VDD7
VDD8 IPower supply for inputs and internal logic
VDD9
VDD10 IPower supply for address bus
VDD11
VDD12 IPower supply for memory control signals
VDD13
VDD14 IPower supply for inputs and internal logic
VDD15
VDD16 IPower supply for memory control signals
VSS1
VSS2 IGround for memory control signals
VSS3
VSS4
VSS5
VSS6
IGround for data bus
VSS7
VSS8
VSS9
VSS10
IGround for address bus
VSS11
VSS12 IGround for memory control signals
VSS13
VSS14
VSS15
VSS16
IGround for inputs and internal logic
†I = Input, O = Output, Z = High-Impedance
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Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME TYPE†
DESCRIPTION
SERIAL PORT SIGNALS
CLKR
TCLKR I
Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data receive) into the
RSR (serial port receive shift register). Must be present during serial port transfers. If the serial port is not being used,
these signals can be sampled as an input via the IN0 bit of the serial port control (SPC) or TDR serial port control
(TSPC) registers.
CLKX
TCLKX I/O/Z
Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX (TDM data
transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set to 0. It can also be driven
by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1. If the serial port is not being used, this
pin can be sampled as an input via the IN1 bit of the SPC or TSPC register . This signal goes into the high-impedance
state when OFF is active (low).
DR
TDR ISerial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.
DX
TDX O/Z Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX. This signal
is in the high-impedance state when not transmitting and when OFF is active (low).
FSR
TFSR/TADD I
I/O/Z
Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive process, which
begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the serial port is operating in the
TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output the address of the port. This signal goes
into the high-impedance state when OFF is active (low).
FSX
TFSX/TFRM I/O/Z
Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit process, which
begins the clocking of the XSR. Following reset, the default operating condition of FSX/TFSX is an input. This pin
may be selected by software to be an output when the TXM bit in the serial control register is set to 1. This signal
goes to the high-impedance state when OFF is active (low). When operating in TDM mode (TDM bit = 1), TFSX
becomes TFRM, the TDM frame-synchronization pulse.
TEST SIGNALS
TCK I Boundary scan test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test
access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test
data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
TDI I Boundary scan test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO O/Z Boundary scan test data output. The contents of the selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. This signal
also goes to the high-impedance state when OFF is active (low).
TMS I Boundary scan test mode select. This serial control input is clocked into the test access port (TAP) controller on the
rising edge of TCK.
TRST I Boundary scan test reset. Asserting this signal gives the JTAG scan system control of the operations of the device.
If this signal is not connected or is driven low, the device operates in its functional mode and the boundary scan
signals are ignored.
EMU0 I/O/Z Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see EMU1/OFF).
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output
put via boundary scan.
EMU1/OFF I/O/Z
Emulator 1/OFF. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and
is defined as input/output via boundary scan. When TRST is driven low, EMU1/OFF is configured as OFF. When
the OFF signal is active (low), all output drivers are in the high-impedance state. OFF is used exclusively for testing
and emulation purposes (not for multiprocessing applications). For the OFF condition, the following conditions apply:
• TRST = Low
• EMU0 = High
• EMU1/OFF = Low
RESERVED N/C Reserved. This pin must be left unconnected.
†I = Input, O = Output, Z = High-Impedance
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absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) − 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range − 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range − 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC − 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg − 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VDD Supply voltage 4.75 5 5.25 V
VSS Supply voltage 0 V
CLKIN, CLKIN2 3 VDD + 0.3 V
V
IH
High-level input voltage CLKX, CLKR, TCLKX, TCLKR 2.5 VDD + 0.3 V
VIH
High-level input voltage
All others 2.2 VDD + 0.3 V
VIL Low-level input voltage −0.3 0.6 V
IOH High-level output current −300‡µA
IOL Low-level output current 2 mA
TC
Operating case temperature (see Note 2)
Mil Temp Parts −55 125 °C
T
C
Operating case temperature (see Note 2)
Industrial Temp Range −40 85 °C
‡This IOH can be exceeded when using a 1-kΩ pulldown resistor on the TDM serial port TADD output; however, this output still meets VOH
specifications under these conditions.
NOTE 2: TC MAX at maximum rated operating conditions at any point on case. TC MIN at initial (time zero) power up.
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS§MIN TYP¶MAX UNIT
VOH High-level output voltage#IOH = MAX 2.4 3 V
VOL Low-level output voltage¶IOL = MAX 0.3 0.6 V
IOZ
High-impedance output
BR (with internal pullup) −500 || 30
A
IOZ
High-impedance output
current (VDD = MAX) All others −30 || 30 µA
TRST (with internal pulldown) −30 || 800
II
Input current
TMS, TCK, TDI (with internal pullups) −500 || 30 µA
II
Input current
(VI = VSS to VDD)X2/CLKIN −50 || 50
µA
(VI = VSS to VDD)
All other inputs −30 || 30 µA
IDDC
Supply current, core CPU
Operating, TA = 25°C, VDD = 5.25 V, fx = 66 MHz 60 225
mA
IDDC Supply current, core CPU Operating, TA = 25°C, VDD = 5.25 V, fx = 66 MHz 94 mA
IDDP
Supply current, pins
Operating, TA = 25°C, VDD = 5.25 V, fx = 66 MHz 40 225
mA
IDDP Supply current, pins Operating, TA = 25°C, VDD = 5.25 V, fx = 66 MHz 63 mA
IDD
Supply current, standby
IDLE instruction, TC = 125°C, VDD = 5.25 V, fx = 66 MHz 30 mA
IDD Supply current, standby IDLE2 instruction, Clocks shut off, VDD = 5.25 V, TC = 125°C7µA
CiInput capacitance 15 40 pF
CoOutput capacitance 15 40 pF
§For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
¶All typical or nominal values are at VDD = 5 V, TA (ambient air temperature)= 25°C.
#All input and output voltage levels are TTL-compatible. Figure 1 shows the test load circuit; Figure 2 and Figure 3 show the voltage reference
levels.
|| These values are not specified pending detailed characterization.
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PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50 Ω
Where: IOL = 2.0 mA (all outputs)
IOH = 300 µA (all outputs)
VLOAD = 1.5 V
CT= 80 pF typical load circuit capacitance
Figure 1. Test Load Circuit
signal transition levels
Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a
maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.
0.6 V
1 V
2 V
2.4 V
Figure 2. TTL-Level Outputs
TTL-output transition times are specified as follows:
DFor a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level
at which the output is said to be low is 1 V.
DFor a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level
at which the output is said to be high is 2 V.
Figure 3 shows the TTL-level inputs.
2.2 V
0.6 V
Figure 3. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
DFor a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 2 V, and the level at which the input is said to be low is 0.8 V.
DFor a low to high transisiton on an input signal, the level at which the input is said to be no longer low
is 0.8 V, and the level at which the input is said to be high is 2 V.
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CLOCK CHARACTERISTICS AND TIMING
The C50 can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the CLKMD1 and CLKMD2 pins. Table 3 outlines the selection of the clock mode by these pins.
Table 3. Clock Mode Selection
CLKMD1 CLKMD2 CLOCK SOURCE
1 0 External divide-by-one clock option
0 1 Reserved for test purposes
1 1 External divide-by-two option or internal divide-by-two clock option
with an external crystal
0 0 External divide-by-two option with the internal oscillator disabled
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half the crystal oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be
specified a t a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows
an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
MIN NOM MAX UNIT
fxInput clock frequency 0†66 MHz
C1, C2 Load capacitance 10 pF
†This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements.
X1 X2/CLKIN
C1 C2
Crystal
Figure 4. Internal Clock Option
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external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected, CLKMD1 set high, and CLKMD2 set high. The external frequency is divided by two to generate
the internal machine cycle. The external frequency injected must conform to specifications listed in the timing
requirements table (see Figure 5 for more details).
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
PARAMETER MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT1 30 2tc(CI) †ns
td(CIH-COH/L) Delay time, X2/CLKIN high to CLKOUT1 high/low 311 20 ns
tf(CO) Fall time, CLKOUT1 5 ns
tr(CO) Rise time, CLKOUT1 5 ns
tw(COL) Pulse duration, CLKOUT1 low H − 3 HH + 2 ns
tw(COH) Pulse duration, CLKOUT1 high H − 3 HH + 2 ns
†This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
timing requirements
MIN MAX UNIT
tc(CI) Cycle time, X2/CLKIN 15 †ns
tf(CI) Fall time, X2/CLKIN 5* ns
tr(CI) Rise time, X2/CLKIN 5* ns
tw(CIL) Pulse duration, X2/CLKIN low 7†ns
tw(CIH) Pulse duration, X2/CLKIN high 7†ns
†This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
*This parameter is not production tested.
tr(CO)
tf(CO)
tw(COH)
CLKOUT1
CLKIN
tw(COL)
td(CIH-COH/L)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
tc(CO)
tc(CI)
Figure 5. External Divide-by-Two Clock Timing
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external divide-by-one clock option
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to VDD. This external frequency is divided by one to generate the internal
machine cycle. The divide-by-one option is used when CLKMD1 is strapped high and CLKMD2 is strapped low.
The external frequency injected must conform to specifications listed in the timing requirements table (see
Figure 6 for more details).
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
PARAMETER MIN TYP MAX UNIT
tc(CO) Cycle time, CLKOUT1 30 tc(CI) 75* ns
td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 2 9 16 ns
tf(CO) Fall time, CLKOUT1 5 ns
tr(CO) Rise time, CLKOUT1 5 ns
tw(COL) Pulse duration, CLKOUT1 low H − 3* HH + 2* ns
tw(COH) Pulse duration, CLKOUT1 high H − 3* HH + 2* ns
td(TP) Delay time, transitory phase−PLL synchronized after CLKIN2 supplied 1000tc(C2)* ns
*This parameter is not production tested.
timing requirements over recommended ranges of supply voltage and operating case temperature
MIN MAX UNIT
tc(C2) Cycle time, CLKIN2 30 75†ns
tf(C2) Fall time, CLKIN2 5* ns
tr(C2) Rise time, CLKIN2 5* ns
tw(C2L) Pulse duration, CLKIN2 low 9 tc(C2)−9 ns
tw(C2H) Pulse duration, CLKIN2 high 9 tc(C2)−9 ns
*This parameter is not production tested.
†Clocks can be stopped only while the device executes IDLE2 when using the external divide-by-one clock option. Note that tp (the transitory
phase) occurs when restarting clock from IDLE2 in this mode.
tr(C2)
tw(C2L)
tw(C2H)
td(TP)
tc(CO)
tc(C2)
tw(COH) tf(CO) tr(CO)
tf(C2)
CLKIN2
CLKOUT1
td(C2H-COH)
tw(COL)
Unstable
Figure 6. External Divide-by-One Clock Timing
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MEMORY AND PARALLEL I/O INTERFACE READ
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER MIN MAX UNIT
tsu(AV-RDL) Setup time, address valid before RD low H−10†‡ ns
th(RDH-AV) Hold time, address valid after RD high 0†‡ ns
tw(RDL) Pulse duration, RD low H−2§* ns
tw(RDH) Pulse duration, RD high H−2§* ns
td(RDH-WEL) Delay time, RD high to WE low 2H−5 ns
†A15−A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
‡See Figure 8 for address-bus timing variation with load capacitance.
§STRB and RD t iming i s − 3/+5 ns from C LKOUT1 t iming o n r ead c ycles, f ollowing t he first cycle after r eset, w hich i s a lways a s even w ait-state c ycle.
*This parameter is not production tested.
timing requirements [H = 0.5 tc(CO)]
MIN MAX UNIT
ta(RDAV) Access time, read data valid from address valid 2H−15‡ns
ta(RDL-RD) Access time, read data valid after RD low H−10 ns
tsu(RD-RDH) Setup time, read data valid before RD high 10 ns
th(RDH-RD) Hold time, read data valid after RD high 0 ns
‡See Figure 8 for address-bus timing variation with load capacitance.
MEMORY AND PARALLEL I/O INTERFACE WRITE
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER MIN MAX UNIT
tsu(AV-WEL) Setup time, address valid before WE low H − 5†‡ ns
th(WEH-AV) Hold time, address valid after WE high H − 10†‡ ns
tw(WEL) Pulse duration, WE low 2H − 4¶* 2H + 2¶* ns
tw(WEH) Pulse duration, WE high 2H − 2¶ns
td(WEH-RDL) Delay time, WE high to RD low 3H − 10 ns
tsu(WDV-WEH) Setup time, write data valid before WE high 2H − 20¶* 2H¶#* ns
th(WEH-WDV) Hold time, write data valid after WE high H − 5¶* H+10¶* ns
ten(WE-BUd) Enable time, WE to data bus driven −5* ns
†A15−A0,PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
‡See Figure 8 for address-bus timing variation with load capacitance.
¶STRB and WE edges are 0−4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting
pulse durations is ± 2 ns, not ± 4 ns.
#This value holds true for zero or one wait state only.
*This parameter is not production tested.
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MEMORY AND PARALLEL I/O INTERFACE WRITE
WE
RD
DATA
R/W
ADDRESS
tsu(AV-RDL)
th(WEH-WDV)
th(WEH-AV)
tw(WEL)
tsu(RD-RDH)
th(RDH-RD)
STRB
tsu(AV-WEL)
tsu(WDV-WEH)
tw(RDH)
ta(RDAV)
td(WEH-RDL)
tw(WEH)
tw(RDL)
td(RDH-WEL)
ta(RDL-RD)
th(RDH-AV)
ten(WE-BUd)
NOTE A: All timings are for 0 wait states. However , external writes always require two cycles to prevent external bus conflicts. The above diagram
illustrates a one-cycle read and a two-cycle write and is not drawn to scale. All external writes immediately preceded by an external
read or immediately followed by an external read require three machine cycles.
Figure 7. Memory and Parallel I/O Interface Read and Write Timing
2
1
0.75
0.50
0.25
1.25
1.50
1.75
10 30 55 70 85
Change in Load Capacitance − pF
15 20 25 4535 40 50 8060 65 75 90 95
Change in Address Bus Timing − ns
Figure 8. Address Bus Timing Variation With Load Capacitance
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READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
timing requirements [H = 0.5tc(CO)] (see Figure 9 and Figure 10)
MIN MAX UNIT
tsu(RY-COH) Setup time, READY before CLKOUT1 rises 10 ns
th(CO-RYH) Hold time, READY after CLKOUT1 rises 0 ns
tsu(RY-RDL) Setup time, READY before RD falls 10 ns
th(RDL-RY) Hold time, READY after RD falls 0 ns
tv(WEL-RY) Valid time, READY after WE falls H − 15 ns
th(WEL-RY) Hold time, READY after WE falls H + 5 ns
READY
ADDRESS
CLKOUT1
tsu(RY-COH)
RD
Wait State
Generated
by READY
Wait State
Generated
Internally
th(CO-RYH)
tsu(RY-RDL)
th(RDL-RY)
Figure 9. Ready Timing for Externally Generated Wait States During an External Read Cycle
READY
ADDRESS
CLKOUT1
Wait State Generated by READY
tv(WEL-RY)
WE
th(CO-RYH)
tsu(RY-COH)
th(WEL-RY)
Figure 10. Ready Timing for Externally Generated Wait States During an External Write Cycle
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RESET, INTERRUPT, AND BIO
timing requirements [H = 0.5tc(CO)] (see Figure 11)
MIN MAX UNIT
tsu(IN-COL) Setup time, INT1−INT4, NMI, before CLKOUT1 low †15 ns
th(COL-IN) Hold time, INT1−INT4, NMI, after CLKOUT1 low †0 ns
tw(INL)SYN Pulse duration, INT1−INT4, NMI low, synchronous 4H+15‡ns
tw(INH)SYN Pulse duration, INT1−INT4, NMI high, synchronous 2H+15‡* ns
tw(INL)ASY Pulse duration, INT1−INT4, NMI low, asynchronous 6H+15‡* ns
tw(INH)ASY Pulse duration, INT1−INT4, NMI high, asynchronous 4H+15‡* ns
tsu(RS-X2L) Setup time, RS before X2/CLKIN low 10 ns
tw(RSL) Pulse duration, RS low 12H ns
td(RSH) Delay time, RS high to reset vector fetch 34H ns
tw(BIL)SYN Pulse duration, BIO low, synchronous 15 ns
tw(BIL)ASY Pulse duration, BIO low, asynchronous H+15* ns
tsu(BI-COL) Setup time, BIO before CLKOUT1 low 15 ns
th(COL-BI) Hold time, BIO after CLKOUT1 low 0 ns
†These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to assure internal synchronization.
‡If in IDLE2, add 4H to these timings.
*This parameter is not production tested.
tsu(IN-COL)
BIO
RS
X2/CLKIN tsu(RS-X2L)
tsu(BI-COL)
tsu(IN-COL)
th(COL-BI)
t
w(INH)SYN
A15−A0
tw(INL)SYN
tsu(IN-COL) th(COL-IN
)
tw(BIL)SYN
td(RSH)
CLKOUT1
tw(RSL)
INT4−
INT1
Figure 11. Reset, Interrupt, and BIO Timings
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INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 12)
PARAMETER MIN MAX UNIT
tsu(AV-IQL) Setup time, address valid before IAQ low†H−12‡ns
th(IQL-AV) Hold time, address valid after IAQ low H−10‡ns
tw(IQL) Pulse duration, IAQ low H−10‡ns
td(CO-TU) Delay time, CLKOUT1 falling to TOUT −6 6 ns
tsu(AV-IKL) Setup time, address valid before IACK low§H−12‡ns
th(IKH-AV) Hold time, address valid after IACK high §H−10‡ns
tw(IKL) Pulse duration, IACK low H−10‡ns
tw(TUH) Pulse duration, TOUT high 2H−12 ns
td(CO-XFV) Delay time, XF valid after CLKOUT1 0 12 ns
†IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on, or code is executing off-chip)
§IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 − A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
CLKOUT1
STRB
IACK
IAQ
ADDRESS
td(CO-TU)
tw(IKL)
tsu(AV-IKL)
tsu(AV-IQL) tw(IQL)
th(IKH-AV)
th(IQL-AV)
XF
TOUT
td(CO-XFV)
tw(TUH)
td(CO-TU)
NOTE: IAQ and IACK are not affected by wait states.
Figure 12. IAQ, IACK, and XF Timings Example With Two External Wait States
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EXTERNAL DMA TIMING
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 3 and
Figure 13)
PARAMETER MIN MAX UNIT
td(HOL-HAL) Delay time, HOLD low to HOLDA low 4H †ns
td(HOH-HAH) Delay time, HOLD high before HOLDA high 2H ns
tdis(AZ-HAL) Disable time, address in the high-impedance state before HOLDA low H−15‡* ns
ten(HAH-Ad) Enable time, HOLDA high to address driven H−5*ns
td(XBL-IQL) Delay time, XBR low to IAQ low 4H*6H*ns
td(XBH-IQH) Delay time, XBR high to IAQ high 2H*4H*ns
td(XSL-RDV) Delay time, read data valid after XSTRB low 40 ns
th(XSH-RD) Hold time, read data after XSTRB high 0 ns
ten(IQL-RDd) Enable time, IAQ low to read data driven 0*§ 2H*ns
tdis(W) Disable time, XR/W low to data in the high-impedance state 0*15*ns
tdis(I-D) Disable time, IAQ high to data in the high-impedance state H*ns
ten(D-XRH) Enable time, data from XR/W going high 4*ns
†HOLD is not acknowledged until current external access request is complete.
‡This parameter includes all memory control lines.
§This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the 320C50x data lines
become valid.
* This parameter is not production tested.
NOTE 3: X preceding a name refers to the external drive of the signal.
timing requirements (see Note 3 and Figure 13)
MIN MAX UNIT
td(HAL-XBL) Delay time, HOLDA low to XBR low 0¶ns
td(IQL-XSL) Delay time, IAQ low to XSTRB low 0¶ns
tsu(AV-XSL) Setup time, Xaddress valid before XSTRB low 15 ns
tsu(DV-XSL) Setup time, Xdata valid before XSTRB low 15 ns
th(XSL-D) Hold time, Xdata hold after XSTRB low 15 ns
th(XSL-WA) Hold time, write Xaddress hold after XSTRB low 15 ns
tw(XSL) Pulse duration, XSTRB low 45 ns
tw(XSH) Pulse duration, XSTRB high 45 ns
tsu(RW-XSL) Setup time, R/W valid before XSTRB low 20 ns
th(XSH-RA) Hold time, read Xaddress after XSTRB high 0 ns
¶XBR, XR/W, and XSTRB lines should be pulled up with a 10-kΩ resistor to assure that they are in an inactive (high) state during the transition
period between the 320C50x driving them and the external circuit driving them.
NOTE 3: X preceding a name refers to the external drive of the signal.
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EXTERNAL DMA TIMING
XDATA(WR)
DATA(RD)
XADDRESS
XR/W
XSTRB
IAQ
XBR
Address
Bus/
Control
Signals†
HOLDA
HOLD
tsu(DV-XSL)
tdis(W)
th(XSH-RD)
td(IQL-XSL)
td(XBL-IQL)
td(HAL-XBL)
ten(HAH-Ad)
tdis(AZ-HAL)
td(HOH-HAH)
td(HOL-HAL)
tsu(AV-XSL)
ten(I-B)
tw(XSH)
tsu(RW-XSL)
tw(XSL)
td(XBH-IQH)
ten(IQL-RDd) ten(D-XRH)
tdis(I-D)
th(XSH-RA)
ten(IQL-RDd)
tsu(AV-XSL)
th(XSL-WA)
th(XSL-D)
td(XSL-RDV)
†A15−A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address bus/control signals.
Figure 13. External DMA Timing
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SERIAL-PORT RECEIVE
timing requirements [H = 0.5tc(CO)] (see Figure 14)
MIN MAX UNIT
tc(SCK) Cycle time, serial-port clock 5.2H †ns
tf(SCK) Fall time, serial-port clock 8* ns
tr(SCK) Rise time, serial-port clock 8* ns
tw(SCK) Pulse duration, serial-port clock low/high 2.1H ns
tsu(FS-CK) Setup time, FSR before CLKR falling edge 10 ns
th(CK-FS) Hold time, FSR after CLKR falling edge 10 ns
tsu(DR-CK) Setup time, DR before CLKR falling edge 10 ns
th(CK-DR) Hold time, DR after CLKR falling edge 10 ns
†The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
* This parameter is not production tested.
Bit
DR
FSR
CLKR
8 or 16
(see Note A)
7 or 15
(see Note A)
21
tsu(DR-CK)
tsu(FS-CK)
th(CK-FS) tw(SCK) tr(SCK)
tf(SCK)
tw(SCK)
th(CK-DR)
tc(SCK)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 14. Serial-Port Receive Timing
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SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 4 and Figure 15)
PARAMETER MIN MAX UNIT
td(CXH-DXV) Delay time, DX valid after CLKX high 25 ns
tdis(CXH-DX) Disable time, DX valid after CLKX high 40*ns
th(CXH-DXV) Hold time, DX valid after CLKX high −5 ns
* This parameter is not production tested.
NOTE 4: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
timing requirements [H = 0.5tc(CO)] (see Note 4 and Figure 15)
MIN MAX UNIT
tc(SCK) Cycle time, serial-port clock 5.2H †ns
tf(SCK) Fall time, serial-port clock 8*ns
tr(SCK) Rise time, serial-port clock 8*ns
tw(SCK) Pulse duration, serial-port clock low/high 2.1H ns
td(CXH-FXH) Delay time, FSX after CLKX high edge 2H−8 ns
th(CXL-FXL) Hold time, FSX after CLKX falling edge 10 ns
th(CXH-FXL) Hold time, FSX after CLKX high edge 2H−8‡* ns
†The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
‡If the FSX pulse does not meet this specification, the first bit of serial data is driven on the DX pin until the falling edge of FSX. After the falling
edge o f FSX, data is shifted out on the DX pin. The transmit-buf fer-empty interrupt is generated when the th(FS) and th(FS)H specification is met.
NOTE 4: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
* This parameter is not production tested.
DX Bit
FSX
CLKX
8 or 16
(see Note A)
7 or 15
(see Note A)
21
th(CXH-DXV)
td(CXH-DXV)
tw(SCK)
tr(SCK)
tf(SCK)
tw(SCK)
tc(SCK)
td(CXH-FXH))
th(CXL-FXL)
tdis(CXH-DX)
th(CXH-FXL)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet
Figure 15. Serial-Port Transmit Timing of External Clocks and External Frames
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SERIAL-PORT TRANSMIT, INTERNAL CLOCKS AND INTERNAL FRAMES
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 4 and
Figure 16)
PARAMETER MIN TYP MAX UNIT
td(CX-FX) Delay time, CLKX rising to FSX 25 ns
td(CX-DX) Delay time, CLKX rising to DX 25 ns
tdis(CX-DX) Disable time, CLKX rising to DX 40*ns
tc(SCK) Cycle time, serial-port clock 8H ns
tf(SCK) Fall time, serial-port clock 5 ns
tr(SCK) Rise time, serial-port clock 5 ns
tw(SCK) Pulse duration, serial-port clock low/high 4H − 20 ns
th(CXH-DXV) Hold time, DX valid after CLKX high − 6 ns
* This parameter is not production tested.
NOTE 4: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
DX
Bit
FSX
CLKX
21
th(CXH-DXV)
tr(SCK)
tf(SCK)
tw(SCK)
tc(SCK)
td(CX-FX)
td(CX-FX) td(CX-DX)
tdis(CX-DX)
tw(SCK)
8 or 16
(see Note A)
7 or 15
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet
Figure 16. Serial-Port Transmit Timing of Internal Clocks and Internal Frames
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SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements [H = 0.5tc(CO)] (see Figure 17)
MIN MAX UNIT
tc(SCK) Cycle time, serial-port clock 5.2H †ns
tf(SCK) Fall time, serial-port clock 8*ns
tr(SCK) Rise time, serial-port clock 8*ns
tw(SCK) Pulse duration, serial-port clock low/high 2.1H ns
tsu(TD-TCH) Setup time, TDAT/TADD before TCLK rising 30 ns
th(TCH-TD) Hold time, TDAT/TADD after TCLK rising −3 ns
tsu(TA-TCH) Setup time, TDAT/TADD before TCLK rising‡20 ns
th(TCH-TA) Hold time, TDAT/TADD after TCLK rising‡− 3 ns
tsu(TF-TCH) Setup time, TRFM before TCLK rising edge§10 ns
th(TCH-TF) Hold time, TRFM after TCLK rising edge§10 ns
†The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
‡These parameters apply only to the first bits in the serial bit string.
§TFRM timing and waveforms shown in Figure 17 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 18.
* This parameter is not production tested.
A7
B2B8 B7
A3
B12
A2A0 A1
B0B1
B13B14
B15
B0
tw(SCK)
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TA-TCH)
th(TCH-TA)
tr(SCK)
tf(SCK)
tc(SCK)
TFRM
TADD
TDAT
TCLK
th(TCH-TF)
tsu(TF-TCH)
th(TCH-TA)
Figure 17. Serial-Port Receive Timing in TDM Mode
SGUS040A − AUGUST 2002 − REVISED JANUARY 2006
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SERIAL-PORT TRANSMIT TIMING IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 18)
PARAMETER MIN MAX UNIT
th(TCH-TDV) Hold time, TDAT/TADD valid after TCLK rising 0 ns
td(TCH-TFV) Delay time, TFRM valid after TCLK rising†H 3H+10 ns
td(TC-TDV) Delay time, TCLK to valid TDAT/TADD 20 ns
†TFRM timing and waveforms shown in Figure 18 are for internal TFRM. TFRM can also be configured as external, and the TFRM external case
is illustrated in the receive timing diagram in Figure 17.
timing requirements [H = 0.5tc(CO)] (see Figure 18)
MIN TYP MAX UNIT
tc(SCK) Cycle time, serial-port clock 5.2H 8H‡§ns
tf(SCK) Fall time, serial-port clock 8*ns
tr(SCK) Rise time, serial-port clock 8*ns
tw(SCK) Pulse duration, serial-port clock low/high 2.1H ns
‡When SCK is generated internally.
§The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
* This parameter is not production tested.
A7
B2B8 B7
A3
B12
A2
A0
A1
B0B1
B13B14B0
tw(SCK)
tw(SCK)
td(TC-TDV)
th(TCH-TDV)
tr(SCK)
tf(SCK)
td(TCH-TFV)
TFRM
TADD
TDAT
TCLK
th(TCH-TDV)
B15
tc(SCK) td(TCV-TDV)
td(TCH-TFV)
Figure 18. Serial-Port Transmit Timing in TDM Mode
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SM320C50PQI80EP NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
SM320C50PQM66EP NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
V62/03613-01XE NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
V62/03613-02XE NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SM320C50-EP :
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 2
•Catalog: SM320C50
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK
100 LEAD SHOWN
88
0.012 (0,30)
0.008 (0,20)
64
0.025 (0,635)
Seating Plane
132
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
4040045/C 11/95
100113
6339
”D2” SQ
”D1” SQ
”D” SQ
14
”D3” SQ
38
DIM
”D”
”D2”
”D3”
”D1”
NOM
MIN
MAX
MIN
MAX
MIN
MAX
LEADS ***
0.180 (4,57) MAX
100
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
0.004 (0,10)
M
0.006 (0,15)
0.010 (0,25)
0.020 (0,51) MIN
0.130 (3,30)
0.150 (3,81)
0.006 (0,16) NOM
Gage Plane
0.036 (0,91)
0.046 (1,17)
0°–8°
89
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
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