LM78L05ACZ/LFT3 - TEXAS INSTRUMENTS

March, 2015 − Rev. 1 1Publication Order Number:

TCP−3168H/D

TCP-3168H

6.8 pF Passive Tunable

Integrated Circuits (PTIC)

Introduction

ON Semiconductor’s PTICs have excellent RF performance and

power consumption, making them suitable for any mobile handset or

radio application. The fundamental building block of our PTIC

product line is a tunable material called ParaScant, based on Barium

Strontium Titanate (BST). PTICs have the ability to change their

capacitance from a supplied bias voltage generated by the Control IC.

The 6.8 pF PTICs are available as wafer-level chip scale packages

(WLCSP).

Key Features

•High Tuning Range and Operation up to 20 V

•Usable Frequency Range: from 700 MHz to 2.7 GHz

•High Quality Factor (Q) for Low Loss

•High Power Handling Capability

•Compatible with PTIC Control IC TCC-10x, 20x

•WLCSP Package: 0.652 x 1.134 x 0.285 mm (12 bump)

•These devices are Pb−Free and RoHS Compliant

Typical Applications

•Multi-band, Multi-standard, Advanced and Simple Mobile Phones

•Tunable Antenna Matching Networks

•Tunable RF Filters

•Active Antennas

Device Package Shipping†

ORDERING INFORMATION

www.onsemi.com

TCP−3168H−DT WLCSP12

(Pb−Free) 4000 Units /

7” Tape & Reel

FUNCTIONAL BLOCK DIAGRAM

PTIC Functional Block Diagram

MARKING DIAGRAM

PTIC

Bias

RF1 RF2

WLCSP12

1.13x0.65

CASE 567KG

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer t o our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

TCP−3168H

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Figure 1. PTIC Functional Block Diagram

Table 1. SIGNAL DESCRIPTIONS

Ball / Pad Number Pin Name Description

A1 DC BIAS DC Bias Voltage

B1 RF2 RF Input / Output

C1* RF2 RF Input / Output

A2 NC Not Connected

B2 RF1 RF Input / Output

C2* RF1 RF Input / Output

*Ball/pad contains multiple connections. Please see packaging information on last page for more information.

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TYPICAL SPECIFICATIONS

Representative Performance Data at 255C

Table 2. PERFORMANCE DATA

Parameter Min Typ Max Units

Operating Bias Voltage 2.0 20 V

Capacitance (Vbias = 2 V) 6.12 6.80 7.48 pF

Capacitance (Vbias = 20 V) 1.564 1.70 1.836 pF

Tuning Range (2 V - 20 V) 3.60 4.00 4.50

Leakage Current (WLCSP) 2.0 mA

Operating Frequency 700 2700 MHz

Quality Factor @ 700 MHz, 10 V 100

Quality Factor @ 2.4 GHz, 10 V 75

IP3 (Vbias = 2 V) [1,3] 70 dBm

IP3 (Vbias = 20 V) [1,3] 85 dBm

2nd Harmonic (Vbias = 2 V) [2,3] -70 dBm

2nd Harmonic (Vbias = 20 V) [2,3] -80 dBm

3rd Harmonic (Vbias = 2 V) [2,3] -40 dBm

3rd Harmonic (Vbias = 20 V) [2,3] -70 dBm

Transition Time (Cmin ³ Cmax) [4] 80 ms

Transition Time (Cmax ³ Cmin) [4] 70 ms

1. f1 = 850 MHz, f2 = 860 MHz, Pin 25 dBm/Tone

2. 850 MHz, Pin +34 dBm

3. IP3 and Harmonics are measured in the shunt configuration in a 50 W environment

4. RFIN and RFOUT are both connected to DC ground

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Representative performance data at 255C for 6.8 pF WLCSP Package

Figure 2. Capacitance Figure 3. Harmonic Power

Figure 4. IP3 Figure 5. Q

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Input Power +40 dBm

Bias Voltage +25 (Note 5) V

Operating Temperature Range −30 to +85 °C

Storage Temperature Range −55 to +125 °C

ESD − Human Body Model Class 1A JEDEC HBM Standard (Note 6)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

5. WLCSP: Recommended Bias Voltage not to exceed 20 V

6. Class 1A defined as passing 250 V, but may fail after exposure to 500 V ESD pulse

TCP−3168H

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ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE

The following assembly considerations should be observed:

Cleanliness

These chips should be handled in a clean environment.

Electro-static Sensitivity

ON Semiconductor’s PTICs are ESD Class 1A sensitive.

The proper ESD handling procedures should be used.

Mounting

The WLCSP PTIC is fabricated for Flip Chip solder

mounting. Connectivity to the RF and Bias terminations on

the PTIC die is established through SAC305 solder balls

with 65 mm nominal height (45 mm to 85 mm height

variation). The PTIC die is RoHS-compliant and compatible

with lead-free soldering profile.

Molding

The PTIC die is compatible for over-molding or

under-fill. Figure 6. Reflow Profile

ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES

When configuring the PTIC in your specific circuit

design, at least one of the RF terminals must be connected

to DC ground. If minimum transition times are required, DC

ground on both RF terminals is recommended. To minimize

losses, the PTIC should be oriented such that RF2 is at the

lower RF impedance of the two RF nodes. A shunt PTIC, for

example, should have RF2 connected to RF ground.

Figure 7. PTIC Orientation Functional Block

Diagram

Bias

RF ANT

RF1

(PTIC Pad)

RF2

(PTIC Pad)

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PART NUMBER DEFINITION

Table 4. PART NUMBERS

Part Number

Capacitance

Package*

2 V 20 V

TCP−3168H-DT 6.80 1.70 12-bump WLCSP

*See PTIC package dimensions on following page.

For information on device numbering and ordering codes,

please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com.

TCP−3168H

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PACKAGE DIMENSIONS

WLCSP12, 1.13x0.65

CASE 567KG

ISSUE A

SEATING

PLANE

0.05 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

4. BACKSIDE TAPE APPLIED TO IMPROVE

PIN 1 MARKING.

DIM

AMIN MAX

0.275

MILLIMETERS

D1.134 BSC

b1 0.044 0.094

e0.150 BSC

0.345

A B

PIN A1

REFERENCE

0.05 C

0.06 C

A1 C

0.045 0.085

0.652 BSC

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.05 C

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 3

e1 0.159 BSC

RECOMMENDED

PACKAGE

OUTLINE

b0.079 0.129

DETAIL A

e2 0.300 BSC

e3 0.460 BSC

e4 0.425 BSC

DET AIL A

A0.05 BC

0.03 C

10X b

DETAIL B

Fe1

10X b1

DETAIL B

A0.05 B

0.03 C

2X b1

2X b

0.13

0.590.59

0.57

0.15

0.75

0.52

0.13

0.51

DETAIL C

NOTE 4

TAPE

DETAIL C

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particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation s pecial, c onsequential o r i ncidental d amages. “Typical” p arameters w hich may b e p rovided i n S CILLC d ata s heets and/or specifications c an a nd d o v ary i n d if ferent a pplications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

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UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

TCP−3168H/D

ParaScan is a trademark of Paratek Microwave, Inc.

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