1
®CA3140, CA3140A
4.5MHz, BiMOS Operational Amplifier with
MOSFET Input/Bipolar Output
The CA3140A and CA3140 are integrated circuit operational
amplifiers that combine the advantages of high vo ltage
PMOS transistors with high voltage bipolar transistors on a
single monolithi c chip.
The CA3140A and CA3140 BiMOS operational amplifiers
feature gate protected MOSFET (PMOS) transistors in the
input circuit to provide very high input impedance, very low
input current, and high speed performance. The CA3140A
and CA3140 operate at supply voltage from 4V to 36V
(either single or dual supply). These operational amplifiers
are inter nally phase compensated to achieve stable
operation in unity gain follower operation, and additionally,
hav e access terminal for a supplementary external capacitor
if additional frequency roll-off is desired. Terminals are also
provided f or use in applications requiring input offset voltage
nulling. The use of PMOS field effect transistors in the input
stage results in common mode input voltage capability down
to 0.5V below the negative supply terminal, an importa nt
attribute for single supply applications. The output stage
uses bipolar transistors and includes built-in protection
against damage from load terminal short circuiting to either
supply rail or to ground.
The CA3140A and CA3140 are intended for operation at supply
voltages up to 36V (±18V).
Features
• MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5TΩ (Typ)
- Very Low Input Current (Il) -10pA (Typ) at ±15V
- Wide Common Mode Input V oltage Range (VlCR) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
• Directly Replaces Industry Type 741 in Most Applications
•Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers in
Automobile and Portable Instr umentation
• Sample and Hold Amplifiers
• Long Duration Timers/Multivibrators
(µseconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectors
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
• Power Supplies
• Portable Instruments
• Intrusion Alarm Systems
Pinout CA3140 (PDIP, SOIC)
TOP VIEW
INV. INPUT
NON-INV.
V-
1
2
3
4
8
7
6
5
STROBE
V+
OUTPUT
OFFSET
NULL
OFFSET
NULL
INPUT
-
+
Data Sheet July 11, 2005 FN957.10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN957.10
July 11, 2005
Ordering Information
PART NUMBER
(BRAND) TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
CA3140AE -55 to 125 8 Ld PDIP E8.3
CA3140AEZ*
(See Note) -55 to 125 8 Ld PDIP
(Pb-free) E8.3
CA3140AM
(3140A) -55 to 125 8 Ld SOIC M8.15
CA3140AM96
(3140A) -55 to 125 8 Ld SOIC Tape and Reel
CA3140AMZ
(3140A) (See Note) -55 to 125 8 Ld SOIC
(Pb-free) M8.15
CA3140AMZ96
(3140A) (See Note) -55 to 125 8 Ld SOIC Tape and Reel
(Pb-free)
CA3140E -55 to 125 8 Ld PDIP E8.3
CA3140EZ*
(See Note) -55 to 125 8 Ld PDIP
(Pb-free) E8.3
CA3140M
(3140) -55 to 125 8 Ld SOIC M8.15
CA3140M96
(3140) -55 to 125 8 Ld SOIC Tape and Reel
CA3140MZ
(3140) (See Note) -55 to 125 8 Ld SOIC
(Pb-free) M8.15
CA3140MZ96
(3140) (See Note) -55 to 125 8 Ld SOIC Tape and Reel
(Pb-free)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
CA3140, CA3140A
3FN957.10
July 11, 2005
Absolute Maximum Ratings Thermal Info rmation
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0 .5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration∞ (Note 2) . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device. This is a stress only rating and operation of the
device at these or any other conditi ons above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications VSUPPLY = ±15V, TA = 25oC
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA3140 CA3140A
Input Offset Voltage Adjustment Resistor Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
4.7 18 kΩ
Input Resistance RI1.5 1.5 TΩ
Input Capacitance CI44pF
Output Resistance RO60 60 Ω
Equiv alent Wide band Inpu t Noise Voltage
(See Figure 27) eNBW = 140kHz, RS = 1MΩ48 48 µV
Equivalent Input Noise Voltage (See Figure 35) eNRS = 100Ωf = 1kHz 40 40 nV/√Hz
f = 10kHz 12 12 nV/√Hz
Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA
IOM-Sink1818mA
Gain-Bandwidth Product, (See Figures 6, 30) fT4.5 4.5 MHz
Slew Rate, (See Figure 31) SR 9 9 V/µs
Sink Current F r om Terminal 8 To Terminal 4 to
Swing Output Low 220 220 µA
Transient Response (See Figure 28) trRL = 2kΩ
CL = 100pF Rise Time 0.08 0.08 µs
OS Overshoot 10 10 %
Settling Time at 10VP-P, (See Figure 5) tSRL = 2kΩ
CL = 100pF
Voltage Follow er
To 1mV 4.5 4.5 µs
To 10mV 1.4 1.4 µs
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL
CA3140 CA3140A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage |VIO|- 5 15- 2 5mV
Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA
Input Current II- 10 50 - 10 40 pA
CA3140, CA3140A
4FN957.10
July 11, 2005
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29) AOL 20 100 - 20 100 - kV/V
86 100 - 86 100 - dB
Common Mode Rejection Ratio
(See Figure 34) CMRR - 32 320 - 32 320 µV/V
70 90 - 70 90 - dB
Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +1 2.5 11 -15 -15.5 to + 12. 5 12 V
Power-Supply Rejection Ratio,
∆VIO/∆VS (See Figure 36) PSRR - 100 150 - 100 150 µV/V
76 80 - 76 80 - dB
Max Output Voltage (Note 4)
(See Figures 2, 8) VOM+ +12 13 - +12 13 - V
VOM- -14 -14.4 - -14 -14.4 - V
Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA
Device Dissipation PD- 120 180 - 120 180 mW
Input Offset Voltage Temperature Drift ∆VIO/∆T- 8 - - 6 -µV/oC
NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2kΩ.
4. At RL = 2kΩ.
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL
CA3140 CA3140A
UNITSMIN TYP MAX MIN TYP MAX
Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3140 CA3140A
Input Offset Voltage |VIO|5 2mV
Input Offset Current |IIO|0.1 0.1pA
Input Current II22pA
Input Resistance RI11TΩ
Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V
100 100 dB
Common Mode Rejection Ratio CMRR 32 32 µV/V
90 90 dB
Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR
∆VIO/∆VS100 100 µV/V
80 80 dB
Maximum Output Voltage (See Figures 2, 8) VOM+3 3 V
VOM- 0.13 0.13 V
Maximum Output Current: Source IOM+10 10mA
Sink IOM-1 1mA
Slew Rate (See Figure 31) SR 7 7 V/µs
Gain-Bandwidth Product (See Figure 30) fT3.7 3.7 MHz
Supply Current (See Figure 32) I+ 1.6 1.6 mA
Device Dissipation PD88mW
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 µA
CA3140, CA3140A
5FN957.10
July 11, 2005
Block Diagram
Schematic Diagram
A ≈ 10 A ≈
10,000
C1
12pF
5
A ≈ 1
1 8
4
6
7
2
3
OFFSET STROBE
NULL
OUTPUT
INPUT
+
-
200µA200µA1.6mA 2µA2mA
2mA 4mA V+
V-
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
R5
500Ω
R4
500Ω
Q11 Q12
R2
500ΩR3
500Ω
Q10
Q9
D5
D4
D3
5 1 8
STROBEOFFSET NULL
3
2
NON-INVERTING
INPUT
INVERTING
INPUT +
-
C1
12pF
Q13
Q15 Q16
Q21
Q20
D8
Q19
Q18
Q17
R11
20Ω
R9
50Ω
R8
1K
R12
12K
R14
20K
R13
5K
D7
R10
1K
OUTPUT
D6
4
V-
V+
6
7
DYNAMIC CURRENT SINKOUTPUT STAGESECOND STAGEINPUT STAGEBIAS CIRCUIT
D2
Q8
Q4
Q3
Q5
Q2
Q6
Q7
D1
Q1
R1
8K
Q14
R7
30Ω
R6
50Ω
NOTE: All resistance values are in ohms.
CA3140, CA3140A
6FN957.10
July 11, 2005
Application Information
Circuit Description
As shown in the block diagram, the input term inals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the vo ltage gain, and a
unique class AB amplifier stage provides the current gain
necessary to dr ive low-impedance loads.
A biasing circuit pro vides control of cascoded constant current
flow circuits in the first and se cond stag es. The CA3140
includes an on chip phase compensa ting capacitor th at is
sufficient f or the un ity gain voltage fo llower configuration.
Input Stage
The schematic diagram consists of a differential input stage
using PMOS field-effect tr ansistors (Q9, Q10) working into a
mirror pair of bipolar transistors (Q11, Q12) functioning as load
resistors together with resistors R2 through R5. The mirror pair
transistors also function as a differential-to-single-ended
converter to provide base current drive to the second stage
bipolar transistor (Q13). Offset nulling, when desired, can be
eff ected with a 10kΩ potentiometer connected across
Terminals 1 and 5 and with its slider arm connected to Terminal
4. Cascode-connected bipolar transistors Q2, Q5 are the
constant current source f or the input stage. The base biasing
circuit f or the constant current source is described
subsequently. The small diodes D3, D4, D5 provide gate oxide
protection against high voltage transients, e .g., static electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q13
and its cascode connected load resistance provided by
bipolar transistors Q3, Q4. On-chip phase compensation,
sufficient for a majority of the applications is provided by C1.
Additional Miller-Effect compensation (roll off) can be
accomplished, when desired, by simply connecting a small
capacitor between Terminals 1 and 8. Terminal 8 is also
used to strobe the output stage into quiescence. When
ter m inal 8 is tied to the negative supply rail (Terminal 4) by
mechanical or electrica l means, the output Termi nal 6
s wings lo w, i.e., approximately to Terminal 4 potential.
Output Stage
The CA3140 Series circuits emplo y a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follo wer cascade
circuit (Q17, Q18) is estab lished by transistors (Q14, Q15)
whose base currents are “mirrored” to current flowing through
diode D2 in the bias circuit section. When the CA3140 is
operating such that output Terminal 6 is sourcing current,
transistor Q18 functions as an emitter-follow er to source current
from the V+ bus (Terminal 7), via D7, R9, and R11. Under these
conditions, the collector potential of Q13 is sufficiently high to
permit the necessary flow of base current t o emitter f o llow er
Q17 which, in turn, drives Q18.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, tr ansistor Q16 is the current
sinking element. Transistor Q16 is mirror connected to D6, R7,
with current f ed by wa y of Q21, R12, and Q20. Transistor Q20, in
turn, is biased by current flow through R13, zener D8, and R14.
The dynamic current sink is controlled by v oltage lev el sensing.
F or purposes of explanation, it is assumed that output Terminal
6 is quiescently established at the potential midpoint between
the V+ and V- supply rails. When output current sinking mode
operation is required, the collector potential of transistor Q13 is
driven below its quiescent le v el, thereb y causing Q17, Q18 to
decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor Q21 is displaced toward the V- bus ,
thereby reducing the channel resistance of Q21. As a
consequence, there is an incremental increase in current flow
through Q20, R12, Q21, D6, R7, and the base of Q16. As a
result, Q16 sinks current from Terminal 6 in direct response to
the incremental change in output voltage caused by Q18. This
sink current flows regardless of load; any excess current is
internally supplied by the emitter-f ollow er Q18. Short circuit
protection of the output circuit is provided by Q19, which is
driven into conduction by the high v oltage drop de v eloped
across R11 under output short circuit conditions. Under these
conditions, the collector of Q19 div erts current from Q4 so as to
reduce the base current drive from Q17, thereby limiting current
flow in Q18 to the short circuited load terminal.
Bias Circuit
Quiescent current in all stages (except the dynamic current
sink) of the CA3140 is dependent upon bias current flow in R1.
The function of the bias circuit is to establish and maintain
constant current flow through D1, Q 6, Q8 and D2. D1 is a diode
connected transistor mirror connected in parallel with the base
emitter junctions of Q1, Q2, and Q3. D1 ma y be considered as a
current sampling diode that senses the emitter current of Q6
and automatically adjusts the base current of Q6 (via Q1) to
maintain a constant current through Q6, Q8, D2. The base
currents in Q2, Q3 are also determined by constant current flow
D1. Furthermore, current in diode connected transistor Q2
establishes the currents in transistors Q14 and Q15.
Typical Applications
Wide dynamic ra nge of input and ou tp ut char acte ristics with
the most desirab le high input impeda nce cha r acteristics is
achie ved in the CA3140 b y the use of an unique design based
upon the PMOS Bipolar process . Input common mode voltage
range and output swing capabilities are complementary,
allowing ope r ation with the single sup ply do w n to 4V.
The wide dynamic range of these parameters also means
that this device is suitable for many single supply
applications, such as, f or example, where one input is driven
below the potential of Terminal 4 and the phase sense of the
output signal must be maintained – a most important
consideration in comparator applications.
CA3140, CA3140A
7FN957.10
July 11, 2005
Output Circuit Considerations
Excellent interfacing with TTL circuitry is easily achiev ed with
a single 6.2V zener diode connected to Terminal 8 as shown
in Figure 1. This connection assures that the maximum
output signal swing will not go more positive than the zener
voltage minus two base-to-emitter voltage drops within the
CA3140. These voltages are independent of the operating
supply voltage.
Figure 2 shows output current sinking capabilities of the
CA3140 at various supply voltages. Output voltage swing to
the negative supply rail perm its this device to operate both
power transistors and thyristors directly wi thout the need for
level shifting circuitr y usually associated with the 741 ser ies
of operational amplifiers.
Figure 4 shows some typical configurations. Note that a
series resistor, RL, is used in both cases to limit the drive
available to the driven device. Moreover, it is recommended
that a series diode and shunt diode be used at the thyristor
input to prevent large negative transient surges that can
appear at the gate of thyristors, from damaging the
integrated circuit.
Offset Voltage Nulling
The input offset voltage can be nulled by connecting a 10kΩ
potentiometer between Terminals 1 and 5 and return ing its
wiper arm to terminal 4, see Figure 3A. This technique,
however, gives more adjustment range than required and
therefore, a considerable portion of the pote ntiometer
rotation is not fully utilized. Typical values of series resistors
(R) that may be placed at either end of the potentiometer ,
see Figure 3B, to optimize its utilization range are given in
the Electrical Specifications table.
An alter nate system is shown in Figure 3C. This circuit uses
only one additional resistor of approximately the value
shown in the table. For potentiometers, in which the
resistance does not drop to 0Ω at either end of rot a ti on , a
value of resistance 10% lower than the values shown in the
table should be used.
Low Voltage Operation
Operation at total supply voltages as low as 4V is possible
with the CA3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performa nce down to these
lower voltages.
The low voltage limitation occurs when the upper extreme of the
input common mode voltage range extends do wn to the voltage
at Terminal 4. This limit is reached at a total supply voltage just
below 4V. The output v oltage range also begins to e xtend down
to the negative supply rail, b ut is slightly higher than that of the
input. Figure 8 shows these characteristics and shows that with
2V dual supplies, the lower e xtreme of the input common mode
voltage range is below ground potential.
3
2
4
CA3140
8
6
7
V+
5V TO 36V
6.2V
≈5V
LOGIC
SUPPLY
5V
TYPICAL
TTL GATE
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT
SWING TO TTL LEVELS
10.01 0.1
LOAD (SINKING) CURRENT (mA)
1.0 10
10
100
1000
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SATURATION VOLTAGE (mV)
SUPPLY VOLTAGE (V-) = 0V
TA = 25oC
SUPPLY VOLTAGE (V +) = +5V +15V +30V
FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15
AND Q16) vs LOAD CURRENT
FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
3
2
4
CA3140
7
6
V+
5
1
V-
10kΩ
3
2
4
CA3140
7
6
V+
5
1
V-
10kΩ
RR
3
2
4
CA3140
7
6
V+
5
1
V-
10kΩ
R
CA3140, CA3140A
8FN957.10
July 11, 2005
Bandwidth and Slew Rate
For those cases where bandwidth reduction is desired, for
ex ample, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor.
Thus, a 20% reduction in bandwidth by this technique will
also reduce the slew rate by about 20%.
Figure 5 shows the typical settling time required to reach
1mV or 10mV of the final value for various levels of large
signal inputs for the voltage follower and inve rting unity gain
amplifiers.
The exceptionally f ast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth
of the CA3140; as shown in Figure 6.
Input Circuit Considerations
As mentioned previously, the ampli f i e r inpu ts can be driv en
below the Termina l 4 potential , but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiti ng resistance should be
provided between the inverting input and the output when
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
3
2
4
CA3140
7
6
LOAD
RL
RS
MT2
MT1
30V
NO LOAD
120VAC 3
2
4
CA3140
7
6
V+ +HV
LOAD
RL
FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
SETTLING TIME (µs)
0.1
INPUT VOLTAGE (V)
1.0 10
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
1mV
10mV 10mV
1mV
1mV1mV
10mV
FOLLOWER
INVERTING
LO AD RESISTANCE (RL) = 2kΩ
LO AD CAPA CITANCE (CL) = 100pF
10
8
6
4
2
0
-2
-4
-6
-8
-10
10mV
3
2
CA3140 6
SIMULATED
LOAD
4
-15V 0.1µF5.11kΩ
0.1µF
7
+15V
5kΩ
2kΩ
100pF
5kΩ
INVERTING
SETTLING POINT
200Ω
4.99kΩ
D1
1N914
D2
1N914
2
CA3140 6
SIMULATED
LOAD
4
-15V 0.1µF
0.1µF
7
+15V
2kΩ
100pF
0.05µF
2kΩ
3
10kΩ
FOLLOWER
CA3140, CA3140A
9FN957.10
July 11, 2005
the CA3140 is used as a unity gain voltage follower. This
resistance prevents the possibility of extremely large input
signal transients from forcing a signal through the input
protection network and directly driving the internal constant
current source which could result in positive f eedback via the
output ter m inal. A 3.9kΩ resistor is sufficient.
The typical input current is on the order of 10pA when the
inputs are ce ntered at nomin a l device dissipat ion. As the
output supplies load current, de vice dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 7 shows typical input terminal current versus
ambient temperature for the CA3140.
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to the application of large
differential input voltages that are sustained over long
periods at elevated temperatures.
Both applied v oltage a nd temper ature acceler ate these
changes. The process is re v ersible and offset v oltage shifts o f
the opposite polarity re verse the offset. Figure 9 shows the
typical offset v oltage change as a function of various stress
vo ltages at the maxim um r ating of 125oC (for metal can); at
low er temper ature s (met al can and pl astic), for example, at
85oC, this change in voltage is co nsider ably less. In typical
linear applications , where the di fferential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encou ntered in an oper atio nal
amplifier employing a bipolar transistor input stage .
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY FIGURE 7. INPUT CURRENT vs TEMPERATURE
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
101103104105106107108
FREQUENCY (Hz)
O
PEN L
OO
P V
O
LTA
G
E
G
AIN
(
dB
)
100
80
60
40
20
0
SUPPLY VOLTAGE: VS = ±15V
TA = 25 oC
102
OPEN LOOP PHASE
-75
-90
-105
-120
-135
-150
(DEGREES)
RL = 2k Ω,
CL = 0pF
RL = 2kΩ,
CL = 100pF
φOL
SUPPLY VOLTAGE: VS = ±15V
TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA)
1K
100
1
10K
10
SUPPLY VOLTAGE (V+, V-)
0 5 10 15 20 25
-1.5
-2.0
-1.0
-2.5
RL = ∞
+VOUT AT TA = 125oC
+VOUT AT TA = 25oC
+VOUT AT TA = -55oC
+VICR AT TA = 125oC
+VICR AT TA = 25oC
+VICR AT TA = -55oC
-3.0
0
-0.5
INPUT AND
O
UTPUT V
O
LTA
G
E EX
C
UR
S
I
O
N
S
FROM TERMINAL 7 (V+)
SUPPLY VOLTAGE (V+, V-)
0 5 10 15 20 25
-VICR AT TA = 125oC
-VICR AT TA = 25oC
-VICR AT TA = -55oC
-VOUT FOR
TA = -55oC to 125oC
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 4 (V-)
0
-0.5
0.5
-1.0
-1.5
1.5
1.0
CA3140, CA3140A
10 FN957.10
July 11, 2005
Super Sweep Function Generator
A function generator having a wide tuning range is shown in
Figure 10. The 1,0 00,000/1 adjustment range is
accomplished by a single variable potentiometer or by an
auxiliary sweeping signal. The CA3140 functions as a non-
inverting readout amplifier of the triangular signal developed
across the integrating capacitor network connected to the
output of the CA3080A current source.
Buff ered triangular output signals are then applied to a
second CA3080 functioning as a high speed h ysteresis
s witch. Output from the switch is returned directly back to the
input of the CA3080A current source, thereby, completing
the positive f eedback loop
The tri angular output level is dete rmined by the four 1N914
level limiti ng diodes of the second CA3080 and the resistor
divider network connected to Terminal No. 2 (input) of the
CA3080. These diodes establish the input trip level to this
switching stage and, therefore, indirectly determine the
amplitude of the output triangle.
Compensation for propagation delays around the entire loop
is provided by one adjustment on the input of the CA3080.
This adjustment, which provides for a constant generator
amplitude output, is most easily made while the generator is
sweeping. High frequency ramp linear ity is adjusted by the
single 7pF to 60pF capacitor in the output of the CA3080A.
It must be emphasized that only the CA3080A is
characterized for maximum output linearity in the current
generator function.
Meter Driver and Buffer Amplifier
Figure 11 shows the CA3140 connected as a meter driver
and buffer amplifier. Low driving impedance is required of
the CA3080A current source to assure smooth operation of
the Frequency Adjustment Control. This low-driving
impedance requirement is easily met by using a CA3140
connected as a voltage follower. Moreover, a meter may be
placed across the input to the CA3080A to give a logarithmic
analog indication of the function generator’s frequency.
Analog frequency readout is readily accomplished by the
means described abov e because the outp ut current of the
CA3080A v aries approximately one decade f or each 60mV
change in the applied voltage, VABC (voltage betw een
Terminals 5 and 4 of the CA3080A of the function generator).
Theref ore, six decades represent 360mV change in VABC.
Now, only the reference voltage must be established to set
the lower limit on the meter. The three remaining transistors
from the CA3086 Array used in the sweep generator are
used for this reference voltage. In addition, this reference
generator arrangement tends to trac k ambient temperature
variations, and thus compensates for the effects of the
norm al negative temperature coefficient of the CA3080A
VABC terminal voltage.
Another output voltage from the reference generator is used
to insure temperature tracking of the lower end of the
Frequency Adjustment Potentiometer. A large series
resistance simulates a current source, assuring similar
temperature coefficients at both ends of the Frequency
Adjustment Control.
To calibrate this circuit, set the Frequency Adjustment
Potentiometer at its low end. Then adjust the Minimum
Frequency Calibration Control for the lowest frequency. To
establish the upper frequency limit, set the Frequen cy
Adjustment Pote ntiometer to its upper end and then adjust
the Maximum Frequency Calibration Control for the
maximum frequency. Because there is interaction among
these controls, repetition of the adjustment procedure may
be necessary. Two adjustments are used for the meter. The
meter sensitivity control sets the meter scale width of each
decade, while the meter position control adjusts the pointer
on the scale with negligible effect on the sensitivity
adjustment. Thus, the meter sensitivity adjustment control
calibrates the meter so that it deflects 1/6 of full scale for
each decade change in frequency.
Sine Wave Shaper
The circuit shown in Figure 12 uses a CA3140 as a voltage
follower in combination with diodes from the CA3019 Array
to conv ert the triangular signal from the function generator to
a sine-wa ve output signal having typically less than 2% THD.
The basic zero crossing slope is established by the 10kΩ
potentiometer connected between Terminals 2 and 6 of the
CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer
from Terminal 2 to ground. Two break points are established
by diodes D1 through D4. Positive feedback via D5 and D6
establishes the zero slope at the maximum and minimum
lev els of the sine wav e. This technique is necessary because
the voltage follower configuration approaches unity gain
rather than the zero gain required to shape the sine wave at
the two extremes.
7
6
5
4
3
2
0
OFFSET VOLTAGE SHIFT (mV)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
TIME (HOURS)
1
DIFFERENTIAL DC VOLTAG E
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
TA = 125oC
FOR METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
CA3140, CA3140A
11 FN957.10
July 11, 2005
FIGURE 10A. CIRCUIT
Top Trace: Output at junction of 2.7Ω and 51Ω resistors;
5V/Div., 500ms/Div.
Center Trace: External output of triangular function generator;
2V/Div., 500ms/Div.
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div.
FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING
1V/Div., 1s/Div.
Three tone test signals, highest frequency ≥0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the CA3080A
and from the PC bo ard a nd compone nt lea ka ges at the 100 pA level.
FIGURE 10C. FUNCTION GENERATOR WITH FIXED
FREQUENCIES FIGURE 10D. INTERCONNECTIONS
FIGURE 10. FUNCTION GENERATOR
0.1
µF
1N914
6
7
4
2
3
0.1
µF
5.1kΩ
10kΩ
2.7kΩ
6
7
4
2
5
-15V
13kΩ
+15V
CENTERING
10kΩ
-15V
910kΩ62kΩ
11kΩ
10kΩ
EXTERNAL
OUTPUT
11kΩ
HIGH
FREQUENCY
LEVEL
7-60pF EXTERNAL
OUTPUT
TO OUTPUT
AMPLIFIER
OUTPUT
AMPLIFIER
TO
SINE WAVE
SHAPER
2kΩ
FREQUENCY
ADJUSTMENT
HIGH
FREQ.
SHAPE
SYMMETRY
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
-15V +15V
10kΩ120Ω
39kΩ
100kΩ
3
6
3
24
7
7.5kΩ+15V+15V
15kΩ
360Ω
360Ω
2MΩ
7-60
pF
-15V
-15V +15V
51
pF
+
CA3080A
-CA3140 CA3080
+
-+
-
5
-15V
FROM BUFFER METER
DRIVER (OPTIONAL)
FREQUENCY
ADJUSTMENT
METER DRIVER
AND BUFFER
AMPLIFIER
FUNCTION
GENERATOR
SINE WAVE
SHAPER
M
POWER
SUPPLY ±15V -15V
+15V
DC LEVEL
ADJUST
51Ω
WIDEBAND
LINE DRIVER
SWEEP
GENERATOR
GATE
SWEEP
V-
SWEEP
LENGTH
EXTERNAL
INPUT
OFF
V-
COARSE
RATE
FINE
RATE
EXT.
INT.
CA3140, CA3140A
12 FN957.10
July 11, 2005
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER
FIGURE 13. SWEEPING GENERATOR
FREQUENCY
CALIBRATION
MINIMUM 200µA
METER
FREQUENCY
CALIBRATION
MAXIMUM
METER
SENSITIVITY
ADJUSTMENT
METER
POSITION
ADJUSTMENT
CA3080A
6
3
24
7
+
CA3140
-
FREQUENCY
ADJUSTMENT
10kΩ
620Ω
4.7kΩ
0.1µF12kΩ
2kΩ
500kΩ
620kΩ
51kΩ
3MΩ
510Ω510Ω
2kΩ
3.6kΩ
-15V
M
11
14
13
3/5 OF CA3086
54
TO CA3080A
OF FUNCTION
GENERATOR
(FIGURE 10)
7
8
6
9
1kΩ
2.4kΩ
2.5
kΩ
+15V
SWEEP IN
10
12
6
3
24
7
+
CA3140
-
7
2856
1
43
9
5.1kΩ
0.1µF-15V
D1D4
D2
D3D6
D5
CA3019
DIODE ARRAY
EXTERNAL
OUTPUT
+15V
+15V
-15V
100
kΩ
SUBSTRATE
OF CA3019
TO
WIDEBAN
D
OUTPUT
AMPLIFIER
7.5kΩ
5.6kΩ
-15V
R3 10kΩ
10kΩ
0.1µF
1MΩ
9.1kΩ
R1
10kΩ
R2
1kΩ
430Ω
4
7
+
CA3140
-
0.1
+15V
-15V
2
3
6
µF
0.1
µF
COARSE
RATE
SAWTOOTH
SYMMETRY
0.47µF
0.047µF
4700pF
470pF
7
3
2
6
4
+
CA3140
-5
1
3
24
15
51kΩ6.8kΩ91kΩ10kΩ
100Ω390Ω
3.9Ω
25kΩ
+15V
-15V
10kΩ
10kΩ
100kΩ
30kΩ
43kΩ
LOGVIO
50kΩ
LOG
RATE
10kΩGATE
PULSE
OUTPUT
-15V
EXTERNAL OUTPUT
T O FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
TO OUTPUT
AMPLIFIER
36kΩ
51kΩ
75kΩ
50kΩ
SAWTOOTH
“LOG”
TRIANGLE
+15V
+15V
4
7
+
CA3140
-
3
2
6
+15V
TRANSISTORS
FROM CA3086
ARRAY
ADJUST
TRIANGLE
SAWTOOTH
“LOG”
8.2kΩ
100kΩ
100kΩ
FINE
RATE
SAWTOOTH
22MΩ
1MΩ
18MΩ
750kΩ
“LOG”
1N914
1N914 SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
-15V
CA3140, CA3140A
13 FN957.10
July 11, 2005
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the outpu t signal with that of a sine wave
generator . The initial slope is adjusted with the potentiometer
R1, followed by an adjustment of R2. The final slope is
established by adjusting R3, thereby adding additional
segments that are contributed by these diodes. Because
there is some interaction among these controls, repetition of
the adjustment proce dure may be necessary.
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a h ysteresis switch that determines
the starting and stopping points of the sweep. A third
CA3140 is used as a logarithmic shaping network for the log
function. Rates and slopes, as well as sawtooth, triangl e,
and logar ithmic swe eps are generated by this circuit.
Wideband Output Amplifier
Figure 14 shows a high slew rate, wideband amplifier
suitable for use as a 50Ω transmission line driver. This
circuit, when used in conjunction with the function generator
and sine wave shaper circuits shown in Figures 10 and 12
prov i d es 18VP-P output open circuited, or 9VP-P output
when terminated in 50Ω. The slew rate required of this
amplifie r is 2 8V/ µs (18VP-P x π x 0.5MHz).
Power Supplies
High input impedance, common mode capability down to the
negative supply and high output drive current capability are
key factors in the design of wide range output voltage
supplies that use a single input voltage to provide a
regulated output voltage that can be adjusted from
essentially 0V to 24V.
Unlike many regulator systems using comparators having a
bipolar transistor input stage, a high impedance reference
voltage divider from a single supply can be used in
connection with the CA3140 (see Figure 15).
Essentially, the regulators, sho wn in Figures 16 and 17, are
connected as non inv erting power oper ational amplifiers with a
gain of 3.2. An 8V reference input yields a maximum output
voltage slightly greater than 25V. As a v oltage f ollo wer, when
the ref erence input goes to 0V the output will be 0V. Because
the offset voltage is also multiplied b y the 3.2 gain f actor, a
potentiometer is needed to null the offset voltage .
Series pass transistors with high ICBO levels will also
prev ent the output voltage from reaching zero because there
is a finite voltage drop (VCESAT) across the output of the
CA3140 (see Figure 2). This saturation voltage level may
indeed set the lowest voltage obtainable.
The high impedance presented by Terminal 8 is
advantageous in eff ecting current limiting. Thus, only a small
signal transistor is required for the current-limit sensing
amplifier. Resistive decoupling is provided for this transistor
to minimize damage to it or the CA3140 in the event of
unusual input or output transients on the supply rail.
Figures 16 and 17, sho w circuits in which a D2201 high spe ed
diode is used f or the current sensor. This diode was chosen
f or its sli ghtly higher forward voltage drop characteristic, thus
giving greater sensitivity. It must be emphasiz ed that heat
sinking of this diode is essential to minimiz e variation of the
current trip point due to internal heating of the diode. That is ,
1A at 1V fo rward drop rep resents one wa tt which can result in
significant regener ative changes in the current trip point as the
diode temperature rises . Placing the small signal reference
amplifier in the pro ximity of the current se nsing dio de also
helps minimize the variability in the trip level due to the
negativ e temperature coefficient of the diode. In spite o f those
limitations , th e cu rrent limiting point can easi ly be adjusted
over the range from 10mA to 1A with a sin gle adjustment
potentiometer. If the temperature sta bility of the current
limiting system is a serious consideration, the more usual
current sampling resistor type of circuitry should be employed.
A power Darlin gton transistor (in a metal can with heatsink),
is used as the series pass element for the conventi onal
current limiting system, Figure 16, because high power
Darlington dissipation will be encountered at low output
voltage and high currents.
2
6
8
1
4
7
+
CA3140
-
50µF
25V 2.2
kΩ2N3053
1N914
2.2
kΩ
1N914
2.7Ω
2.7Ω
2N4037
+
-
+
-50µF
25V
3
SIGNAL
LEVEL
ADJUSTMENT
2.5kΩ
200Ω
2.4pF
2pF -15V
+15V
OUTPUT
DC LEVEL
ADJUSTMENT
-15V
+15V
3kΩ
200Ω1.8kΩ
51Ω
2W
OUT
NOMINAL BA NDWIDTH = 10MHz
tr = 35ns
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER
6
3
24
7
+
CA3140
-
VOLTAGE
REFERENCE
VOLTAGE ADJUSTMENT
REGULATED
OUTPUT
INPUT
FIGURE 15. B ASIC SINGLE SUPPLY VOLT A GE REGULA T OR
SHO WING VOLTA GE FOLLO WER CONFIGURATION
CA3140, CA3140A
14 FN957.10
July 11, 2005
A small heat sink VERSAWATT transistor is used as the
series pass element in the fold back current system, Figure
17, since dissipation levels will only approach 10W. In this
system, the D220 1 di o d e is used for current samplin g.
F oldback is provided by the 3kΩ and 100kΩ divider network
connected to the base of the current sensing transistor.
Both regulators provide be tter than 0.02% load re gula tion.
Because there is constant loop gain at all v oltage settings, the
regulation also remains constant. Line regulation is 0.1% per
vo lt. Hum and noise v oltage is le ss than 200µV as read with a
meter having a 10MH z bandwi dth.
Figure 18A shows the turn ON and turn OFF characteristics
of both regulators. The slow turn on rise is due to the slow
rate of rise of the reference voltage. Figure 18B shows the
transient response of the regulator with the switching of a
20Ω load at 20V output.
FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK”
CURRENT LIMITING
5V/Div., 1s/Div.
FIGURE 18A. SUPPLY TURN-ON AND TURNOFF
CHARACTERISTICS
Top Trace: Output Voltage;
200mV/Div., 5µs/Div.
Bottom Trace: Collector of load switching transistor, load = 1A;
5V/Div., 5µs/Div.
FIGURE 18B. TRANSIENT RESPONSE
FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17
1
3
75Ω
3kΩ
100Ω
2
1kΩ1kΩ
D2201
CURRENT
LIMITING
ADJUST
2N6385
PO WER DARLINGTON
2
1kΩ
1
3
8
2N2102
1kΩ
+30V
INPUT 4
CA3140
7
1
6
5
100kΩ
2
3
180kΩ56pF
1kΩ82kΩ
250µF
+
-
0.01µF
100kΩ
14
10
6
9
8
50kΩ
13
5µF
+
-
12
CA3086
2.2kΩ
3
1
5
4
62kΩ
VOLTAGE
ADJUST
10µF+
-
2.7kΩ
1kΩ
11
7
2
HUM AND NOISE OUTPUT <200µVRMS
(MEASUREMENT B ANDWIDTH ~10MHz)
LINE REGULATION 0.1%/V
LO AD RE GULATION
(NO LO A D TO FULL LO AD)
<0.02%
OUTPUT
0.1 ⇒ 24V
AT 1A
1
2
1kΩ200Ω
D2201
“FOLDBACK” CURRENT
LIMITER
2N5294
3kΩ
8
2N2102
1kΩ
+30V
INPUT 4
CA3140
7
1
6
5
100kΩ
2
3
180kΩ56pF
1kΩ82kΩ
250µF
+
-
0.01µF
100kΩ
14
10
6
9
8
50kΩ
13
5µF
+
-
12
CA3086
2.2kΩ
3
1
5
4
62kΩ
VOLTAGE
ADJUST
10µF+
-
2.7kΩ
1kΩ
11
7
2
HUM AND NOISE OUTPUT <200µVRMS
(MEASUREMENT BA NDWIDTH ~10MHz)
LINE REGULATION 0.1%/V
LO AD RE GULATION
(NO LO A D TO FULL LO AD)
<0.02%
OUTPUT ⇒ 0V T O 25V
25V AT 1A
3
100kΩ
“FOLDS B ACK”
T O 40mA
100kΩ
CA3140, CA3140A
15 FN957.10
July 11, 2005
Tone Control Circuits
High slew rate, wide bandwidth, high output voltage
capability and high input impedance are all characteristics
required of tone control amplifiers. Two tone control circuits
that e xploit these characteristics of the CA3140 are shown in
Figures 19 and 20.
The first circuit, shown in Figure 20, is the Baxandall tone
control circuit which provides unity gain at midband and
uses standard linear potentiometers. The high input
impedance of the CA3140 makes possible the use of low-
cost, low-va lue, small size capacitors, as well as reduced
load of the driving stage.
Bass treble boost and cut are ±15dB at 100Hz and 10kHz,
respectively. Full peak-to-peak output is availab le up to at
least 20kHz due to the high slew rate of the CA3140. The
amplifier gain is 3dB down from its “flat” position at 70kHz.
Figure 19 shows another tone control circuit with similar
boost and cut specifications. The wideband gain of this
circuit is equal to the ultimate boost or cut plus one, which in
this case is a gain of eleven. For 20dB boost and cut, the
input loading of this circuit is essentially equal to the value of
the resistance from Term inal No. 3 to ground. A detailed
analysis of this circuit is given in “An IC Operational
Transconductance Amplifier (O TA) With P ower Capability” by
L. Kaplan and H. Wittlinger , IEEE Transactions on Broadcast
and Television Receivers, Vol. BTR-18, No. 3, August, 1972.
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES
4
7
+
CA3140
-
+30V
3
2
0.1µF
6
0.005µF
0.1
µF
2.2MΩ
2.2MΩ
5.1
MΩ
0.012µF0.001µF
0.022µF
2µF
18kΩ
0.0022µF
200kΩ
(LINEAR)
100
pF 100pF
BOOST TREBLE CUT
BOOST BASS CUT
10kΩ1MΩ
CCW (LOG) 100kΩ
TO NE CONTR O L NETWORK
FOR SINGLE SUPPLY
-+
+15V
30.1µF
0.005µF
5.1MΩ
0.1µF
-15V
2
6
7
4
+
CA3140
-
TONE CONTROL NETWORK
FOR DUAL SUPPLIES
NOTES:
5. 20dB Flat Position Gain.
6. ±15dB Bass and Treble Boost and Cut
at 100Hz and 10kHz, respectively.
7. 25VP-P output at 20kHz.
8. -3dB at 24kHz from 1kHz reference.
4
7
+
CA3140
-
+32V
3
0.1
2.2MΩ
2.2
MΩ
FOR SINGLE SUPPLY
µF
6
2
0.1
µF
20pF
750
pF
750
pF
2.2MΩ
0.047µF
BOOST TREBLE CUT
51kΩ5MΩ
(LINEAR) 51kΩ
T ONE CONTROL NETWORK
BOOST BASS CUT
240kΩ5MΩ
(LINEAR) 240kΩ
+15V
30.1µF
0.047µF
0.1µF
-15V
2
6
7
4
+
CA3140
-
FOR DUAL SUPPLIES
ΝΟΤΕΣ:
9. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively.
10. 25VP-P Output at 20kHz.
11. -3dB at 70kHz from 1kHz Reference.
12. 0dB Flat Position Gain.
TO NE CONTR O L
NETWORK
CA3140, CA3140A
16 FN957.10
July 11, 2005
Wien Bridge Oscillator
Another application of the CA3140 that makes excellent use
of its high input impedance, high slew rate, and high voltage
qualities is the Wien Bridge sine w a ve oscilla tor . A ba sic Wien
Bridge oscillator is shown in Figure 21. When R1 = R2 = R
and C1 = C2 = C, the frequency equation reduces to the
familiar f = 1/(2πRC) and the gain required for oscillation,
AOSC is equal to 3. Note that if C2 is increased by a factor of
four and R2 is reduced by a factor of four, the gain required
for oscillation becomes 1.5, thus permitting a potentially
higher operating frequency closer to the gain bandwidth
product of the CA3140.
Oscillator stabilization takes on many forms. It must be
precisely set, otherwise the amplitude will either diminish or
reach some form of limiting with high lev els of distortion. The
element, RS, is commonly replaced with some variable
resistance element. Thus, through some control means, the
value of RS is adjusted to maintain constant oscillator output.
A FET channel resistance, a thermistor , a lamp bulb , or other
device whose resistance increases as the output amplitude
is increased are a few of the elements often utilized.
Figure 22 shows another means of stabilizing th e oscillator
with a zener diode shunting the feedback resistor (RF of
Figure 21). As the output signal amplitude increases, the
zener diode impedance decreases resulting in more
feedback with consequent reduction in gain; thus stabilizing
the amplitude of the output signal. Fu rthermore, this
combination of a monolithic zener diode and bridge rectifier
circuit tends to provide a zero temperature coefficient for this
regulating system. Because this bridge rectifier system has
no time constant, i.e., thermal time constant for the lamp
bulb, and RC time constant for filters often used in detector
networks, there is no low er frequency limit. For e xample, with
1µF polycarbonate capacitors and 22MΩ for the frequency
deter mining network, the operating frequency is 0.007Hz.
As the frequency is increased, the output amplitude must be
reduced to preve nt the output signal from becoming slew-
rate limited. An output frequency of 180kHz will reach a slew
rate of approximatel y 9V/ µs when its amplitude is 16VP-P.
Simple Sample-and-Hold System
Figure 23 shows a very simple sample-and-hold system
using the CA3140 as the readout amplifier for the storage
capacitor . The CA3080A serves as both input buff er amplifier
and low feed-through transmission switch (see Note 13).
System offset nulling is accomplished with the CA3140 via
its offset nulling terminals. A typical simulated load of 2kΩ
and 30pF is shown in the schematic.
In this circuit, the storage compensation capacitance (C1) is
only 200pF. Larger value capacitors provide longer “hold”
period s but with slower slew rates. The slew rate is:
NOTE:
13. AN6668 “Applications of the CA3080 and CA 3080A High
Performance Operational Transconductance Amplifiers”.
NOTES: f1
2πR1C1R2C2
-------------------------------------------=
AOSC 1C1
C2
-------R2
R1
-------
++=
ACL 1RF
RS
--------+=
C1
R2
R1
C2
OUTPUT
RF
RS
+
-
FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT
USING AN OPERATIONAL AMPLIFIER
8
5 4
3
1
9
6
CA3109
DIODE
ARRAY
+15V
0.1µF
0.1µF
-15V
2
6
7
4
+
CA3140
-SUBSTRATE
OF CA3019
0.1µF
7
7.5kΩ
3.6kΩ
500Ω
OUTPUT
19VP-P TO 22VP-P
THD <0.3%
3
R2
C21000pF
1000
pF
C1
R1
R1 = R2 = R
50Hz, R = 3.3MΩ
100Hz, R = 1.6MΩ
1kHz, R = 160MΩ
10kHz, R = 16MΩ
30kHz, R = 5.1MΩ
2
FIGURE 22. WIEN BRIDGE OSCILLA T OR CIRCUIT USING
CA3140
+15V
3.5kΩ
30pF
2
6
1
+
CA3140
-
SIMULATED LOAD
NOT REQUIRED
100kΩ
INPUT
0.1
0.1µF
µF
7
0.1µF
-15V 2kΩ
3
400Ω
200pF
6
4
5
7
4
+
CA3080A
-
0.1µF
+15V
-15V
200pF
2kΩ
2
3
5
2kΩ
STROBE SAMPLE
HOLD-15
0
30kΩ
1N914
1N914
2kΩ
C1
FIGURE 23. SAMPLE AND HOLD CIRCUIT
dv
dt
------ I
C
----0.5mA 200pF⁄2.5V µs⁄== =
CA3140, CA3140A
17 FN957.10
July 11, 2005
Pulse “droop” during the hold interval is 170pA/200pF which is
0.85µV/µs; (i.e ., 170pA/200pF). In this case, 170pA represents
the typical leakage current of the CA3080A when strobed off . If
C1 were increased to 2000pF, the “hold-droop” rate will
decrease to 0.085µV/µs, but the slew rate would decrease to
0.25V/µs . The parallel diode network connected between
Terminal 3 of the CA3080A and Terminal 6 of the CA3140
prevents large input signal feedthrough across the input
terminals of the CA3080A to the 200pF storage capacitor when
the CA3080A is strobed off. Figure 24 shows dynamic
characteristic wav eforms of this sample-and-hold system.
Current Amplifier
The low input terminal current needed to drive the CA3140
makes it ideal f or use in current amplifier applications such
as the one shown in Figure 25 (see Note 14). In this circuit,
low current is supplied at the input potential as the power
supply to load resistor RL. This load current is increased by
the multiplication factor R2/R1, when the load current is
monitored by the power supply meter M. Thus, if the load
current is 100nA, with values shown, the load current
presented to the supply will be 100µA; a much easier current
to measure in many systems.
Note that the input and output voltages are transf erred at the
same potential and only the output current is multiplied by
the scale factor.
The dotted components show a method of decoupling the
circuit from the effects of high output load capacitance and
the potential oscillation in this situation . Essential ly, the
necessary high frequency feedback is provided by the
capacitor with the dotted series resistor providing load
decoupling.
Full Wave Rectifier
Figure 26 shows a single supply, absolute value, ideal full-
wave rectifier with associated waveforms. During positive
excursions, the input signal is fed through the feedback
network directly to the output. Simultaneously, the positive
excursion of the input signal also drives the output termin al
(No. 6) of the inverting ampli fier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the CA3140 functions as a
normal inv erting amplifier with a gain equal to -R2/R1. When
the equality of the two equations shown in Figure 26 is
satisfied, the full wave output is symmetrical.
NOTE:
14. “Operational Amplifiers Design and Applications”, J. G. Graeme,
McGraw-Hill Book Company, page 308, “Negative Immittance
Converter Circuits”.
Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
Top Trace: Output Signal; 5V/Div, 2µs/Div.
Center Trace: Difference of Input and Output Signals through
Tektronix Amplifier 7A13; 5mV/Div., 2µs/Div.
Bottom Trace: Input Signal; 5V/Div., 2µs/Div.
LARGE SIGNAL RESPONSE AND SETTLING TIME
SAMPLING RESPONSE
Top Trace: Output; 100mV/Div., 500ns/Div.
Bottom Trace: Input; 20V/Div., 500ns/Div.
FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC
CHARACTERISTICS WAVEFORMS
+15V
21
100kΩ
0.1µF
-15V
4
5
7
+
CA3140
-0.1µF
4.3kΩ
10kΩ
6
3
R1
POWER
SUPPLY
10MΩ
R2
ILR2
R1
M
RL
IL
x
FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT
MEASUREMENT SYSTEMS
CA3140, CA3140A
18 FN957.10
July 11, 2005
+15V
3
0.1µF
8
5kΩ
7
15
6
2
R2
R1
10kΩ
R3
1N914
10kΩ
100kΩ
OFFSET
ADJUST
4
PEAK
ADJUST
10kΩ
+
CA3140
-
20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V
GAIN R2
R1
-------XR3
R1R2R3
+
-----------------------------
===
R3XX
2
+
1X–
-----------------
R1
=
FOR X 0.5 5kΩ
10kΩ
---------------R2
R1
-------
==
R310kΩ0.75
0.5
-----------
15kΩ==
OUTPUT
0
INPUT
0
FIGURE 26. SINGLE SUPPLY , ABSOL UTE V ALUE, IDEAL
FULL WAVE RECTIFIER WITH ASSOCIATED
WAVEFORMS
+15V
-15V
2
7
4
+
CA3140
-
3
0.01µF
0.01µF
6
1MΩNOISE VOLTAGE
OUTPUT
30.1kΩ
1kΩ
RS
BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT ) = 48µV (TYP)
FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENT
Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
FIGURE 28B. SMALL SIGNAL RESPONSE
(Measurement made with Tektronix 7A13 differential amplifier.)
Top Trace: Output Signal; 5V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal; 5V/Div., 5µs/Div.
FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHO WING
SETTLING TIME
FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST
CIRCUIT AND ASSOCIATED WAVEFORMS
+15V
-15V
2
7
4
+
CA3140
-
3
0.1µF
0.1µF
6
0.05µF
2kΩ
10kΩ
100pF
SIMULATED
LOAD
2kΩ
BW (-3dB) = 4.5MHz
SR = 9V/µs
FIGURE 28A. TEST CIRCUIT
INPUT
CA3140, CA3140A
19 FN957.10
July 11, 2005
Typical Performance Curves
FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VOLTAGE AND TEMPERATURE FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE
FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND
TEMPERATURE FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE AND TEMPERATURE
FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs
FREQUENCY FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY
125
100
75
50
25
OPEN-LOOP VOLTAGE GAIN (dB)
0 5 10 15 20
SUPPLY VO LTAGE (V)
125oC
25oC
TA = -55oC
RL = 2kΩ
25
0
GAIN BANDWIDTH PRODUCT (MHz)
125oC
25oC
TA = -55oC
RL = 2kΩ
20
10
0 5 10 15 20
SUPPLY VOLTAGE ( V)
25
CL = 100pF
1
125oC
25oC
TA = -55oC
RL = 2kΩ
5101520
SUPPLY VOLTAGE (V) 25
CL = 100pF
20
15
10
5
0
SLEW RATE (V/µs)
0
7
6
5
4
3
0 5 10 15 20
SUPPLY VOLTAGE (V)
125oC
TA = -55oC
RL = ∞
25
0
2
1
25oC
QUIESCENT SUPPLY CURRENT (mA)
25
20
15
10
5
0
OUTPUT SWING (VP-P)
10K 100K
FREQUENCY (Hz)
1M 4M
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC120
100
80
60
40
20
0
COMMON-MODE REJECTION RATIO (dB)
101102103104105106107
FREQUENCY (Hz)
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
CA3140, CA3140A
20 FN957.10
July 11, 2005
FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY
Typical Performance Curves (Continued)
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
FREQUENCY (Hz)
110
1102103104105
EQUIVALENT INPUT NOISE V OLTAGE (nV/√Hz)
100
10
1
1000
102103104105106107
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
100
80
60
40
20
0
+PSRR
-PSRR
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
POWER SUPPLY REJECTION RATIO
(PSRR) = ∆VIO/∆VS
101
CA3140, CA3140A
21 FN957.10
July 11, 2005
Metallization Mask Layout
Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is
par t of the wafer. When the wafer is cut into chips, the cleavage
angles are 57o instead of 90ο with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
62-70
(1.575-1.778)
4-10
(0.102-0.254)
60
50
40
30
20
10
0
58-66
(1.473-1.676)
5040302010
61
060 65
CA3140, CA3140A
22 FN957.10
July 11, 2005
CA3140, CA3140A
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
23
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN957.10
July 11, 2005
CA3140, CA3140A
Small Outline Plastic Packages (SOIC)
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α0o8o0o8o-
Rev. 0 12/93
