S29AL032D 32 Mbit, 3 V, Flash 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector This product has been retired and is not recommended for designs. For new and current designs, the S29GL064S supersedes the S29AL032D. This is the factory-recommended migration path. Please refer to the S29GL064S data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Distinctive Characteristics Architectural Advantages Performance Characteristics Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications High performance - Access times as fast as 70 ns Ultra low power consumption (typical values at 5 MHz) - 200 nA Automatic Sleep mode current - 200 nA standby mode current - 9 mA read current - 20 mA program/erase current ig n Manufactured on 200-nm process technology - Fully compatible with 0.23 m Am29LV320D, 0.32 m Am29LV033C, and 0.33 m MBM29LV320E devices Flexible sector architecture - Boot sector models: Eight 8-Kbyte sectors; sixty-three 64-Kbyte sectors; top or bottom boot block configurations available - Uniform sector models: Sixty-four 64-Kbyte sectors es Cycling endurance: 1,000,000 cycles per sector typical D Data retention: 20 years typical Sector Protection features - A hardware method of locking a sector to prevent any program or erase operations within that sector - Sectors can be locked in-system or via programming equipment - Temporary Sector Unprotect feature allows code changes in previously locked sectors ew Software Features rN CFI (Common Flash Interface) compliant - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices fo de d Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequences Erase Suspend/Erase Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Data# Polling and toggle bits - Provides a software method of detecting program or erase operation completion - Unlock Bypass Program Command Reduces overall programming time when issuing multiple program command sequences Compatibility with JEDEC standards - Pinout and software compatible with single-power supply Flash - Superior inadvertent write protection Hardware Features 48-pin TSOP 40-pin TSOP ot 48-ball FBGA Cypress Semiconductor Corporation Document Number: 002-02003 Rev. *B Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) - Hardware method to reset the device to reading array data N Package Options R ec om m en Secured Silicon Sector - 128-word sector for permanent, secure identification through an 8word random Electronic Serial Number - May be programmed and locked at the factory or by the customer - Accessible through a command sequence WP#/ACC input pin - Write protect (WP#) function allows protection of two outermost boot sectors (boot sector models only), regardless of sector protect status - Acceleration (ACC) function provides accelerated program times * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised January 08, 2016 S29AL032D General Description The S29AL032D is a 32-megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0-DQ15; byte mode data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin TSOP and 48-ball FBGA packages. Standard control pins- chip enable (CE#), write enable (WE#), and output enable (OE#)-control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the pro-gram and erase operations. ig n S29AL032D Features D es The Secured Silicon Sector is an extra sector capable of being permanently locked by Spansion or customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Note that the S29AL032D has a Secured Silicon Sector size of 128 words (256 bytes). ew Factory locked parts provide several options. The Secured Silicon Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through the Spansion programming service), or both. fo rN The S29AL032D is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. om m en de d Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. R ec The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. ot The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. N Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot-electron injection. Document Number: 002-02003 Rev. *B Page 2 of 64 S29AL032D Contents 1. Product Selector Guide ............................................... 4 2. Block Diagram.............................................................. 4 3. 3.1 3.2 3.3 Connection Diagrams.................................................. FBGA Package for Model 00 Only................................. FBGA Package for Models 03, 04 Only ......................... Special Handling Instructions......................................... 4. Pin Configuration......................................................... 7 12. 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Write Operation Status ............................................... 37 DQ7: Data# Polling ....................................................... 37 RY/BY#: Ready/Busy#.................................................. 38 DQ6: Toggle Bit I .......................................................... 39 DQ2: Toggle Bit II ......................................................... 39 Reading Toggle Bits DQ6/DQ2..................................... 39 DQ5: Exceeded Timing Limits ...................................... 40 DQ3: Sector Erase Timer.............................................. 41 5. Logic Symbols ............................................................. 8 13. Absolute Maximum Ratings....................................... 42 6. 6.1 6.2 Ordering Information ................................................... 9 S29AL032D Standard Products..................................... 9 Valid Combinations ...................................................... 10 14. Operating Ranges ....................................................... 43 7. 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 Device Bus Operations.............................................. Word/Byte Configuration (Models 03, 04 Only) ........... Requirements for Reading Array Data......................... Writing Commands/Command Sequences.................. Program and Erase Operation Status.......................... Accelerated Program Operation .................................. Standby Mode.............................................................. Automatic Sleep Mode................................................. RESET#: Hardware Reset Pin..................................... Output Disable Mode ................................................... Sector Addresss Tables............................................... Autoselect Mode .......................................................... Sector Protection/Unprotection .................................... Write Protect (WP#) -- Models 03, 04 Only ................ Temporary Sector Unprotect........................................ 16. Test Conditions ........................................................... 46 16.1 Key to Switching Waveforms ........................................ 46 8. 8.1 Secured Silicon Sector Flash Memory Region ....... 24 Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory ........................................ 25 Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory..................... 25 AC Characteristics...................................................... 47 Read Operations........................................................... 47 Hardware Reset (RESET#)........................................... 48 Word/Byte Configuration (BYTE#) (Models 03, 04 Only)......................................................49 17.4 Erase/Program Operations ........................................... 50 17.5 Temporary Sector Unprotect......................................... 53 17.6 Alternate CE# Controlled Erase/Program Operations .. 55 fo rN ew 17. 17.1 17.2 17.3 de om m en Hardware Data Protection ......................................... Low VCC Write Inhibit................................................... Write Pulse "Glitch" Protection..................................... Logical Inhibit ............................................................... Power-Up Write Inhibit ................................................. 10. Common Flash Memory Interface (CFI) ................... 27 ot 9. 9.1 9.2 9.3 9.4 N D es ig n 15. DC Characteristics...................................................... 44 15.1 Zero Power Flash.......................................................... 45 d 10 10 11 11 11 11 11 12 12 13 13 19 20 24 24 ec R 8.2 5 6 7 7 18. Erase and Programming Performance ..................... 57 19. 19.1 19.2 19.3 TSOP and BGA Pin Capacitance ............................... 57 TS040--40-Pin Standard TSOP................................... 58 TS 048--48-Pin Standard TSOP .................................. 60 VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm ...............................................................61 20. Document History Page ............................................. 62 26 26 26 26 26 11. 11.1 11.2 11.3 11.4 Command Definitions................................................ 29 Reading Array Data ..................................................... 29 Reset Command .......................................................... 29 Autoselect Command Sequence ................................. 30 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence ................................................... 30 11.5 Word/Byte Program Command Sequence................... 30 11.6 Unlock Bypass Command Sequence .......................... 30 11.7 Chip Erase Command Sequence ................................ 31 11.8 Sector Erase Command Sequence ............................. 32 11.9 Erase Suspend/Erase Resume Commands ................ 32 11.10Command Definitions Table ........................................ 34 Document Number: 002-02003 Rev. *B Page 3 of 64 S29AL032D 1. Product Selector Guide Family Part Number S29AL032D Speed Option Voltage Range: VCC = 2.7-3.6 V 70 90 Max access time, ns (tACC) 70 90 Max CE# access time, ns (tCE) 70 90 Max OE# access time, ns (tOE) 30 35 Note See AC Characteristics on page 47 for full specifications. 2. Block Diagram ig n DQ0-DQ15 (A-1), (DQ0-DQ7 Model 00) RY/BY# VCC D rN Command Register om m en PGM Voltage Generator d fo State Control de WE# Input/Output Buffers ew Erase Voltage Generator RESET# BYTE# es Sector Switches VSS CE# R ec OE# Chip Enable Output Enable Logic VCC Detector A0-A20 (A0-A21 Model 00) Document Number: 002-02003 Rev. *B Timer Address Latch N ot STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix Page 4 of 64 S29AL032D 3. Connection Diagrams Figure 3.1 40-pin Standard TSOP A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC A21 DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 fo rN ew D es ig n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 om m en R ec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ot N A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 de d Figure 3.2 48-pin Standard TSOP Document Number: 002-02003 Rev. *B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Page 5 of 64 S29AL032D 3.1 FBGA Package for Model 00 Only Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down) B6 C6 D6 E6 F6 G6 H6 A14 A13 A15 A16 A17 NC A20 VSS A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A11 A12 A19 A10 DQ6 DQ7 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC NC DQ5 NC VCC A3 B3 C3 D3 E3 F3 RY/BY# ACC NC NC DQ2 A2 B2 C2 D2 E2 A7 A18 A6 A5 A1 B1 C1 D1 A3 A4 A2 es H3 ew VCC A21 F2 rN G2 H2 DQ0 NC NC DQ1 E1 F1 G1 H1 A0 CE# OE# VSS d de D G3 fo DQ4 DQ3 N ot R ec om m en A1 ig n A6 Document Number: 002-02003 Rev. *B Page 6 of 64 S29AL032D 3.2 FBGA Package for Models 03, 04 Only Figure 3.4 Models 03, 04 48-ball FBGA (Top View, Balls Facing Down) A6 B6 C6 D6 E6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 WE# RESET# NC A19 DQ5 DQ12 VCC A3 B3 C3 D3 E3 F3 A18 A20 DQ2 B2 C2 D2 E2 A7 A17 A6 A5 DQ0 A1 B1 C1 D1 3.3 A2 ig n es DQ4 DQ10 DQ11 DQ3 F2 G2 H2 DQ8 DQ9 DQ1 F1 G1 H1 OE# VSS D H3 fo E1 d A1 H4 G3 de A4 VSS A0 CE# om m en A3 H6 BYTE# DQ15/A-1 rN A2 G6 ew RY/BY# WP#/ACC F6 Special Handling Instructions ec Special handling is required for Flash Memory products in FBGA packages. ot R Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. N 4. Pin Configuration Pin Description A0-A21 22 address inputs A0-A20 21 address inputs DQ0-DQ7 8 data inputs/outputs DQ0-DQ14 15 data inputs/outputs DQ15/A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# Selects 8-bit or 16-bit mode CE# Chip enable OE# Output enable WE# Write enable RESET# Hardware reset pin WP#/ACC Hardware Write Protect input/Programming Acceleration input. Document Number: 002-02003 Rev. *B Page 7 of 64 S29AL032D Pin Description ACC Hardware Write Protect input RY/BY# Ready/Busy output 3.0 volt-only single power supply VCC (see Product Selector Guide on page 4 for speed options and voltage supply tolerances) VSS Device ground NC Pin not connected internally 5. Logic Symbols es ig n Figure 5.1 Logic Symbols Models 03, 04 D Model 00 A0-A21 A0-A20 8 16 or 8 DQ0-DQ15 (A-1) fo rN DQ0-DQ7 CE# d CE# OE# de OE# RESET# RESET# WP#/ACC RY/BY# BYTE# N ot R ec RY/BY# om m en WE# WE# ACC ew 21 22 Document Number: 002-02003 Rev. *B Page 8 of 64 S29AL032D 6. 6.1 Ordering Information S29AL032D Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL032D 70 T A I 00 0 PACKING TYPE es ig n 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER fo rN ew D 00 = x8, VCC = 2.7 V to 3.6 V, Uniform sector device 03 = x8/x16, VCC = 2.7 V to 3.6 V, Top boot sector device, top two address sectors protected when WP#/ACC = VIL 04 = x8/x16, VCC = 2.7 V to 3.6 V, Bottom boot sector device, bottom two address sectors protected when WP#/ACC = VIL TEMPERATURE RANGE om m en de d I = Industrial (-40C to +85C) N = Extended (-40C to +125C) PACKAGE MATERIAL SET N ot R ec A = Standard F = Pb-Free PACKAGE TYPE T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION S29AL032D 3.0 Volt-only, 32 Megabit Standard Flash Memory, manufactured using 200 nm process technology Document Number: 002-02003 Rev. *B Page 9 of 64 S29AL032D S29AL032D Valid Combinations Device Number Package Type, Material, and Temperature Range Speed Option Model Number 00 TAI, TFI BAI, BFI 00, 03, 04 S29AL032D BAI, BFI, BAN, BFN VBN048 (Note 3) TS040 (Note 2) 0, 3 (Note 1) 03, 04 90 TS048 (Note 2) 0, 2, 3 (Note 1) 00 TAI, TFI, TAN, TFN TS040 (Note 2) 0, 3 (Note 1) 03, 04 70 Package Description Packing Type 00, 03, 04 TS048 (Note 2) 0, 2, 3 (Note 1) Fine-Pitch BGA TSOP Fine-Pitch BGA ig n Notes 1. Type 0 is standard. Specify other options as required. VBN048 (Note 3) TSOP es 2. TSOP package marking omits packing type designator from ordering part number. D 3. BGA package marking omits leading S29 and packing type designator from ordering part number. Valid Combinations ew 6.2 fo rN Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. d 7. Device Bus Operations om m en de This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. CE# OE# WE# RESET# WP#(Note 6)/ACC Addresses (Note 3) DQ0- DQ7 DQ8-DQ15 (Note 6) BYTE# = VIH BYTE# = VIL L H H L/H AIN DOUT DOUT L H L H (Note 4) AIN (Note 5) (Note 5) L H L H VHH AIN (Note 5) (Note 5) VCC 0.3 V X X VCC 0.3 V H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X High-Z High-Z High-Z (Note 5) X X (Note 5) X X (Note 5) (Note 5) High-Z Read Write (Note 1) Accelerated Program (Note 6) Standby Sector Protect (Note 3) Sector Unprotect (Note 3) Temporary Sector Unprotect N L ot Operation R ec Table 8. S29AL032D Device Bus Operations L H L VID L/H L H L VID (Note 4) X X X VID (Note 4) SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L AIN DQ8-DQ14 = High-Z, DQ15 = A-1 Legend L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Document Number: 002-02003 Rev. *B Page 10 of 64 S29AL032D Notes 1. When the ACC pin is at VHH, the device enters the accelerated program mode. See 2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL). 3. The sector protect and sector unprotect functions may also be implemented via programming equipment. 4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected. 5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm. 6. Models 03, 04 only 7.1 Word/Byte Configuration (Models 03, 04 Only) The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. Requirements for Reading Array Data D 7.2 es ig n If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. ew To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. d fo rN The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device-address inputs produce valid data on the device-data outputs. The device remains enabled for read access until the command register contents are altered. 7.3 om m en de See Reading Array Data on page 29 for more information. Refer to the AC Read Operations on page 47 table for timing specifications and to Figure 17.1 on page 47 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences ec To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. R For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration (Models 03, 04 Only) on page 11 for more information. N ot The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/Byte Program Command Sequence on page 30 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 8 on page 13 and Table 10 on page 15 indicate the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The Command Definitions on page 29 contains details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 19 and Autoselect Command Sequence on page 30 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics on page 47 contains timing specification tables and timing diagrams for write operations. 7.4 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 37 for more information, and to AC Characteristics on page 47 for timing diagrams. Document Number: 002-02003 Rev. *B Page 11 of 64 S29AL032D 7.5 Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC (ACC on Model 00) pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the previously mentioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 7.6 Standby Mode ig n When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. ew D es The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. 7.7 fo rN In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification. Automatic Sleep Mode om m en de d The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tASM. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in DC Characteristics on page 44 represents the automatic sleep mode current specification. Table 8. Automatic Sleep Mode Timing Description tASM Automatic Sleep Mode Max. Unit tACC+30 ns R ec Parameter RESET#: Hardware Reset Pin ot 7.8 N The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to AC Characteristics on page 47 for RESET# parameters and to Figure 17.2 on page 48 for the timing diagram. Document Number: 002-02003 Rev. *B Page 12 of 64 S29AL032D 7.9 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. 7.10 Sector Addresss Tables Table 8. Model 00 Sector Addresses (Sheet 1 of 2) A21 A20 A19 A18 A17 A16 Address Range (in hexadecimal) SA0 0 0 0 0 0 0 000000-00FFFF SA1 0 0 0 0 0 1 010000-01FFFF SA2 0 0 0 0 1 0 020000-02FFFF SA3 0 0 0 0 1 1 030000-03FFFF SA4 0 0 0 1 0 0 040000-04FFFF SA5 0 0 0 1 0 1 050000-05FFFF SA6 0 0 0 1 1 0 060000-06FFFF SA7 0 0 0 1 1 1 SA8 0 0 1 0 0 0 SA9 0 0 1 0 0 1 SA10 0 0 1 0 1 0 ew D es ig n Sector 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0 0 1 0 1 1 0B0000-0BFFFF 0 0 1 1 0 0 0C0000-0CFFFF SA13 0 0 1 1 0 1 0D0000-0DFFFF SA14 0 0 1 0 0E0000-0EFFFF SA15 0 0 1 SA16 0 1 0 SA17 0 1 0 SA18 0 1 0 SA19 0 1 SA20 0 1 SA21 0 SA22 0 SA23 SA24 om m en de SA11 SA12 d fo rN 070000-07FFFF 1 1 1 0F0000-0FFFFF 0 0 100000-10FFFF 0 0 1 110000-11FFFF 0 1 0 120000-12FFFF ec 1 0 1 1 130000-13FFFF 1 0 0 140000-14FFFF R 0 0 ot 0 1 0 1 0 1 150000-15FFFF 1 0 1 1 0 160000-16FFFF 0 1 0 1 1 1 170000-17FFFF 0 1 1 0 0 0 180000-18FFFF SA25 0 1 1 0 0 1 190000-19FFFF SA26 0 1 1 0 1 0 1A0000-1AFFFF N 1 SA27 0 1 1 0 1 1 1B0000-1BFFFF SA28 0 1 1 1 0 0 1C0000-1CFFFF SA29 0 1 1 1 0 1 1D0000-1DFFFF SA30 0 1 1 1 1 0 1E0000-1EFFFF SA31 0 1 1 1 1 1 1F0000-1FFFFF SA32 1 0 0 0 0 0 200000-20FFFF SA33 1 0 0 0 0 1 210000-21FFFF SA34 1 0 0 0 1 0 220000-22FFFF SA35 1 0 0 0 1 1 230000-23FFFF Document Number: 002-02003 Rev. *B Page 13 of 64 S29AL032D Table 8. Model 00 Sector Addresses (Sheet 2 of 2) Sector A21 A20 A19 A18 A17 Address Range (in hexadecimal) A16 SA36 1 0 0 1 0 0 240000-24FFFF SA37 1 0 0 1 0 1 250000-25FFFF SA38 1 0 0 1 1 0 260000-26FFFF SA39 1 0 0 1 1 1 270000-27FFFF SA40 1 0 1 0 0 0 280000-28FFFF SA41 1 0 1 0 0 1 290000-29FFFF 1 0 1 0 1 0 2A0000-2AFFFF 1 0 1 0 1 1 2B0000-2BFFFF SA44 1 0 1 1 0 0 2C0000-2CFFFF SA45 1 0 1 1 0 1 2D0000-2DFFFF ig n SA42 SA43 1 0 1 1 1 0 2E0000-2EFFFF 1 0 1 1 1 1 2F0000-2FFFFF 0 0 0 0 0 0 0 1 SA50 1 1 0 0 1 0 SA51 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 1 1 0 1 1 0 360000-36FFFF SA55 1 1 0 1 1 1 370000-37FFFF 1 1 1 1 1 1 1 1 1 1 1 1 SA60 1 1 1 SA61 1 1 1 R 1 0 380000-38FFFF 1 390000-39FFFF 0 1 0 3A0000-3AFFFF 0 1 1 3B0000-3BFFFF 1 0 0 3C0000-3CFFFF 1 0 1 3D0000-3DFFFF 1 1 1 0 3E0000-3EFFFF ot 1 1 0 0 1 1 1 3F0000-3FFFFF 1 1 N SA62 SA63 0 0 ec SA58 SA59 om m en SA56 SA57 de SA54 d fo SA52 SA53 D 1 1 ew 1 1 rN SA48 SA49 es SA46 SA47 Note All sectors are 64 Kbytes in size. Table 9. Model 00 Secured Silicon Sector Addresses Sector Address A21-A7 Sector Size (bytes) (x8) Address Range 000000000000000 128 000000h-00007fh 000000000001000 128 000400h-00047Fh Document Number: 002-02003 Rev. *B Page 14 of 64 S29AL032D Table 10. Model 03 Sector Addresses (Sheet 1 of 2) Sector Sector Address A20-A12 Sector Size (Kbytes/ Kwords) (x8) Address Range (x16) Address Range SA0 000000xxx 64/32 000000h-00FFFFh 000000h-07FFFh SA1 000001xxx 64/32 010000h-01FFFFh 008000h-0FFFFh SA2 000010xxx 64/32 020000h-02FFFFh 010000h-17FFFh SA3 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh SA4 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh SA5 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh SA6 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh SA8 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh es ig n SA7 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh D SA9 SA10 001011xxx 64/32 0B0000h-0BFFFFh 001100xxx 64/32 0C0000h-0CFFFFh 058000h-05FFFFh SA13 001101xxx 64/32 0D0000h-0DFFFFh SA14 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh rN ew SA11 SA12 060000h-067FFFh 068000h-06FFFFh 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh SA17 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh SA18 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh om m en de d fo SA15 SA16 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh SA20 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA21 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA22 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA25 011001xxx SA26 011010xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh 64/32 180000h-18FFFFh 0C0000h-0C7FFFh R 011000xxx 64/32 ot 010111xxx SA24 N SA23 ec SA19 64/32 190000h-19FFFFh 0C8000h-0CFFFFh 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA27 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA28 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA29 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA30 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA31 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA32 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh SA33 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh SA34 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh SA35 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh SA36 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh SA37 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh SA38 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh SA39 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh SA40 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh Document Number: 002-02003 Rev. *B Page 15 of 64 S29AL032D Table 10. Model 03 Sector Addresses (Sheet 2 of 2) Sector Sector Address A20-A12 Sector Size (Kbytes/ Kwords) (x8) Address Range (x16) Address Range SA41 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh SA42 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA43 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA44 101100xxx 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA45 101101xxx 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA46 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh ig n SA47 SA48 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh 330000h-33FFFFh 340000h-34FFFFh SA53 110101xxx 64/32 350000h-35FFFFh SA54 110110xxx 64/32 360000h-36FFFFh 198000h-19FFFFh D 64/32 64/32 1A0000h-1A7FFFh 1A8000h-1AFFFFh ew 110011xxx 110100xxx rN SA51 SA52 es SA49 SA50 1B0000h-1B7FFFh 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA56 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA57 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA58 111010xxx 64/32 3A0000h-3AFFFFh de d fo SA55 1D0000h-1D7FFFh 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA60 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA61 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh SA62 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh 3F6000h-3F7FFFh 1FB000h-1FBFFFh 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh ec om m en SA59 111111010 111111011 SA67 111111100 SA68 111111101 SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh R SA65 SA66 N ot 8/4 Note The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). Table 11. Model 03 Secured Silicon Sector Addresses Sector Address A20-A12 Sector Size (bytes/words) (x8) Address Range (x16) Address Range 111111111 256/128 3FFF00h-3FFFFFh 1FFF80h-1FFFFFh Document Number: 002-02003 Rev. *B Page 16 of 64 S29AL032D Table 12. Model 04 Sector Addresses (Sheet 1 of 2) Sector Address A20-A12 Sector Size (Kbytes/ Kwords) (x8) Address Range (x16) Address Range SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh SA8 000001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh SA9 000010xxx 64/32 020000h-02FFFFh SA10 000011xxx 64/32 030000h-03FFFFh es ig n Sector D 010000h-017FFFh ew 018000h-01FFFFh 000100xxx 64/32 040000h-04FFFFh 000101xxx 64/32 050000h-05FFFFh SA13 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh SA14 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh fo rN SA11 SA12 020000h-027FFFh 028000h-02FFFFh 001000xxx 64/32 080000h-08FFFFh SA16 001001xxx 64/32 090000h-09FFFFh SA17 001010xxx 64/32 0A0000h-0AFFFFh SA18 001011xxx 64/32 0B0000h-0BFFFFh SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh SA23 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh SA24 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh SA25 010010xxx SA26 010011xxx N ot R ec om m en de d SA15 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 64/32 120000h-12FFFFh 090000h-097FFFh 64/32 130000h-13FFFFh 098000h-09FFFFh SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh SA39 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh Document Number: 002-02003 Rev. *B Page 17 of 64 S29AL032D Table 12. Model 04 Sector Addresses (Sheet 2 of 2) Sector Address A20-A12 Sector Size (Kbytes/ Kwords) (x8) Address Range (x16) Address Range SA40 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh SA41 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh SA42 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh SA43 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh SA44 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh SA45 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh SA46 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh SA47 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh SA48 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh SA51 101100xxx 64/32 2C0000h-2CFFFFh SA52 101101xxx 64/32 2D0000h-2DFFFFh SA53 101110xxx 64/32 2E0000h-2EFFFFh D es ig n Sector 160000h-167FFFh rN ew 168000h-16FFFFh 170000h-177FFFh 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA55 111000xxx 64/32 300000h-30FFFFh 180000h-187FFFh SA56 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh SA57 110010xxx 64/32 320000h-32FFFFh SA58 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh om m en de d fo SA54 190000h-197FFFh 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA64 111001xxx SA65 111010xxx SA66 111011xxx SA67 111100xxx SA68 SA69 SA70 ec SA62 390000h-39FFFFh 1C8000h-1CFFFFh 3A0000h-3AFFFFh 1D0000h-1D7FFFh 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh R 64/32 N ot 64/32 Note The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). Table 13. Model 04 Secured Silicon Sector Addresses Sector Address A20-A12 Sector Size (bytes/words) (x8) Address Range (x16) Address Range 000000000 256/128 000000h-0000FFh 00000h-0007Fh Document Number: 002-02003 Rev. *B Page 18 of 64 S29AL032D 7.11 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 8. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 8 on page 13 and Table 10 on page 15). Table 8 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 13 on page 35. This method does not require VID. See Command Definitions for details on using the autoselect mode. A11 to A10 A9 A8 to A7 A6 A5 to A4 L L H X X VID X L X Byte L L H X X VID X L Device ID: S29AL032D (Model 03) Word L L H L H X Byte L X VID Device ID: S29AL032D (Model 04) Word L L H X X Sector Protection Verification Secured Silicon Sector Indicator Bit (DQ7) L L X 01h N/A A3h 22h F6h X F6h 22h F9h X F9h L L H L X L L H X X L L H rN X d X L H L L H SA X VID X L X L H L L L H X X VID X L X L H H L L R X X VID X L X L H H H X X VID X L X L H H ot H N (Model 03) Secured Silicon Sector Indicator Bit (DQ7) L L (Model 00) Secured Silicon Sector Indicator Bit (DQ7) DQ7 to DQ0 de Byte DQ8 to DQ15 L VID om m en Device ID: S29AL032D (Model 00) A0 A1 ec Manufacturer ID: Spansion A3 to A2 ig n A21 to A12 es WE# Mode D OE# Description ew CE# fo Table 8. S29AL032D Autoselect Codes (High Voltage Method) L L (Model 04) X 01h (protected) X 00h (unprotected) X 85 (factory locked) X 05 (not factory locked) X 8D (factory locked) X 1D (not factory locked) X 9D (factory locked) X 0D (not factory locked) Legend L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Note The autoselect codes may also be accessed in-system via command sequences. See Table 13 on page 35. Document Number: 002-02003 Rev. *B Page 19 of 64 S29AL032D 7.12 Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through the Spansion ExpressFlashTM Service. Contact a Spansion representative for further details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 10.1 on page 23 shows the algorithms and Figure 18.3 on page 55 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. D es ig n The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0-volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion representative to request a copy. 000000 Sector/Sector Block Size rN A21-A16 SA0 SA1-SA3 000001, 000010, 000011 SA4-SA7 000100, 000101, 000110, 000111 fo Sector/Sector Block ew Table 8. Sector Block Addresses for Protection/Unprotection -- Model 00 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 001000, 001001, 001010, 001011 256 (4x64) Kbytes 001100, 001101, 001110, 001111 256 (4x64) Kbytes SA16-SA19 010000, 010001, 010010, 010011 256 (4x64) Kbytes SA20-SA23 010100, 010101, 010110, 010111 256 (4x64) Kbytes om m en de d SA8-SA11 SA12-SA15 011000, 011001, 011010, 011011 256 (4x64) Kbytes 011100, 011101, 011110, 011111 256 (4x64) Kbytes SA32-SA35 100000, 100001, 100010, 100011 256 (4x64) Kbytes SA36-SA39 100100, 100101, 100110, 100111 256 (4x64) Kbytes SA40-SA43 101000, 101001, 101010, 101011 256 (4x64) Kbytes 101100, 101101, 101110, 101111 256 (4x64) Kbytes 110000, 110001, 110010, 110011 256 (4x64) Kbytes 110100, 110101, 110110, 110111 256 (4x64) Kbytes SA56-SA59 111000, 111001, 111010, 111011 256 (4x64) Kbytes SA60-SA62 111100, 111101, 111110 192 (4x64) Kbytes SA63 111111 64 Kbytes SA52-SA55 R ot SA48-SA51 N SA44-SA47 ec SA24-SA27 SA28-SA31 Table 9. Sector Block Addresses for Protection/Unprotection -- Model 03 (Sheet 1 of 2) Sector / Sector Block A20-A12 Sector/Sector Block Size SA0-SA3 000000XXX, 000001XXX, 000010XXX, 000011XXX 256 (4x64) Kbytes SA4-SA7 0001XXXXX 256 (4x64) Kbytes SA8-SA11 0010XXXXX 256 (4x64) Kbytes SA12-SA15 0011XXXXX 256 (4x64) Kbytes SA16-SA19 0100XXXXX 256 (4x64) Kbytes Document Number: 002-02003 Rev. *B Page 20 of 64 S29AL032D Table 9. Sector Block Addresses for Protection/Unprotection -- Model 03 (Sheet 2 of 2) Sector / Sector Block A20-A12 Sector/Sector Block Size SA20-SA23 0101XXXXX 256 (4x64) Kbytes 0110XXXXX 256 (4x64) Kbytes 0111XXXXX 256 (4x64) Kbytes SA32-SA35 1000XXXXX 256 (4x64) Kbytes SA36-SA39 1001XXXXX 256 (4x64) Kbytes SA40-SA43 1010XXXXX 256 (4x64) Kbytes SA44-SA47 1011XXXXX 256 (4x64) Kbytes SA48-SA51 1100XXXXX 256 (4x64) Kbytes SA52-SA55 1101XXXXX 256 (4x64) Kbytes ig n SA24-SA27 SA28-SA31 1110XXXXX 256 (4x64) Kbytes SA60-SA62 111100XXX, 111101XXX, 111110XXX 192 (3x64) Kbytes SA63 111111000 SA64 111111001 SA65 111111010 SA66 111111011 SA67 111111100 SA68 111111101 SA69 111111110 SA70 111111111 es SA56-SA59 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes A20-A12 Sector/Sector Block Size SA70-SA67 111111XXX, 111110XXX, 111101XXX, 111100XXX 256 (4x64) Kbytes SA66-SA63 om m en de d fo rN ew D 8 Kbytes 1110XXXXX 256 (4x64) Kbytes 1101XXXXX 256 (4x64) Kbytes 1100XXXXX 256 (4x64) Kbytes Table 10. Sector Block Addresses for Protection/Unprotection -- Model 04 ec Sector / Sector Block SA58-SA55 256 (4x64) Kbytes 256 (4x64) Kbytes 1001XXXXX 256 (4x64) Kbytes 1000XXXXX 256 (4x64) Kbytes SA38-SA35 0111XXXXX 256 (4x64) Kbytes SA34-SA31 0110XXXXX 256 (4x64) Kbytes SA30-SA27 0101XXXXX 256 (4x64) Kbytes SA26-SA23 0100XXXXX 256 (4x64) Kbytes SA22-SA19 0011XXXXX 256 (4x64) Kbytes SA18-SA15 0010XXXXX 256 (4x64) Kbytes SA14-SA11 0001XXXXX 256 (4x64) Kbytes SA10-SA8 000011XXX, 000010XXX, 000001XXX 192 (3x64) Kbytes SA7 000000111 8 Kbytes SA6 000000110 8 Kbytes SA5 000000101 8 Kbytes SA46-SA43 ot 1011XXXXX 1010XXXXX SA50-SA47 N SA54-SA51 R SA62-SA59 SA42-SA39 Document Number: 002-02003 Rev. *B Page 21 of 64 S29AL032D Table 10. Sector Block Addresses for Protection/Unprotection -- Model 04 A20-A12 Sector/Sector Block Size SA4 000000100 8 Kbytes SA3 000000011 8 Kbytes SA2 000000010 8 Kbytes SA1 000000001 8 Kbytes SA0 000000000 8 Kbytes N ot R ec om m en de d fo rN ew D es ig n Sector / Sector Block Document Number: 002-02003 Rev. *B Page 22 of 64 S29AL032D Figure 10.1 In-System Sector Protect/Unprotect Algorithms START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 ms Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 ms First Write Cycle = 60h? First Write Cycle = 60h? No es Yes ew D Set up first sector address Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Data = 01h? Yes fo d R N ot Protect another sector? No PLSCNT = 1000? Yes Device failed Write reset command Sector Protect complete Read from sector address with A6 = 1, A1 = 1, A0 = 0 No Remove VID from RESET# Sector Protect Algorithm Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT Yes Device failed Wait 15 ms de ec Yes Reset PLSCNT = 1 om m en No PLSCNT = 25? Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 rN Wait 150 s No All sectors protected? ig n Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Yes Yes Set up sector address Increment PLSCNT No Set up next sector address No Data = 00h? Yes Last sector verified? No Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Document Number: 002-02003 Rev. *B Page 23 of 64 S29AL032D 7.13 Write Protect (WP#) -- Models 03, 04 Only The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 8-Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in Sector Protection/ Unprotection on page 20. The two outermost 8-Kbyte boot sectors are the two sectors containing the lowest addresses in a bottomboot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8-KByte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in Sector Protection/Unprotection on page 20. 7.14 ig n Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector Unprotect ew D es This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure , shows the algorithm, and Figure 18.1 on page 53 shows the timing diagrams, for this feature. fo rN Figure 7.2 Temporary Sector Unprotect Operation de d START om m en RESET# = VID (Note 1) RESET# = VIH N ot R ec Perform Erase or Program Operations Temporary Sector Unprotect Completed (Note 2) Notes 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. 8. Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory-locked part. This ensures the security of the ESN once the product is shipped to the field. Document Number: 002-02003 Rev. *B Page 24 of 64 S29AL032D Spansion offers the device with the Secured Silicon Sector either factory-locked or customer-lockable. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Secured Silicon Sector through a command sequence (see Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 30). After the system writes the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory ig n 8.1 D es In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. The device is available pre-programmed with one of the following: A random, secure ESN only. ew Customer code through the ExpressFlash service. rN Both a random, secure ESN and customer code through the ExpressFlash service. de d fo In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses 00000h-0000Fh in byte mode (or 00000h-00007h in word mode). In the Top Boot device, the ESN is in sector 70 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode). In the Uniform device, the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h in word mode). Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory ec 8.2 om m en Customers may opt to have their code programmed by Spansion through the Spansion ExpressFlash service. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Secured Silicon Sector permanently locked. Contact a Spansion representative for details on using the Spansion ExpressFlash service. ot R The customer lockable version allows the Secured Silicon Sector to be programmed once, and then permanently locked after it ships from Spansion. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. N The Secured Silicon Sector area can be protected using the following procedures: Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 10.1 on page 23, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 8.1 on page 26. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Document Number: 002-02003 Rev. *B Page 25 of 64 S29AL032D Figure 8.1 Secured Silicon Sector Protect Verify START If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. RESET# = VIH or VID Wait 1 ms Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 ig n Remove VIH or VID from RESET# D SecSi Sector Protect Verify complete es Write reset command de 9. Hardware Data Protection d fo rN ew Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 om m en The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 13 on page 35 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. N ot R ec 9.1 9.2 Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 9.3 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. 9.4 Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Document Number: 002-02003 Rev. *B Page 26 of 64 S29AL032D 10. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be deviceindependent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 11-14. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 11-14. The system must write the reset command to return the device to the autoselect mode. ig n For further information, please contact a Spansion representative for a copy of this document. es Table 11. CFI Query Identification String Addresses (Models 03, 04 Byte Mode Only) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string QRY 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) D Addresses om m en de d fo rN ew Description Addresses (Models 03, 04 Byte Mode Only) R Addresses ec Table 12. System Interface String Data Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 38h 0036h VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N s 20h 40h 0000h Typical timeout for Min. size buffer write 2N s (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) 36h N 1Ch ot 0027h 1Bh Document Number: 002-02003 Rev. *B Page 27 of 64 S29AL032D Table 13. Device Geometry Definition Addresses Addresses (Models 03, 04 Byte Mode Only) Data 27h 4Eh 0016h Device Size = 2N byte 28h 29h 50h 52h 000xh 0000h Flash Device Interface description (refer to CFI publication 100) (0 = Model 00, 2 = Models 03, 04) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 000xh Number of Erase Block Regions within device (1 = Model 00, 2 = Models 03, 04) 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 00xxh 0000h 00x0h 000xh Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) (003F, 0000, 0000, 0001) = Model 00 31h 32h 33h 34h 62h 64h 66h 68h 00xxh 0000h 0020h 000xh Erase Block Region 2 Information (0000, 0000, 0000, 0000) = Model 00 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information ig n Description D es (0007, 0000, 0020, 0000) = Models 03, 04 om m en de d fo rN ew (003E, 0000, 0000, 0001) = Models 03, 04 Table 14. Primary Vendor-Specific Extended Query (Sheet 1 of 2) Addresses (Models 03, 04 Byte Mode Only) 40h 41h 42h 80h 82h 84h 43h 44h Data Description Query-unique ASCII string "PRI" 86h 0031h Major version number, ASCII 88h 0031h Minor version number, ASCII 45h 8Ah 000xh Address Sensitive Unlock 0 = Required (Models 03, 04), 1 = Not Required (Model 00) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, 01 = Supported ot R ec 0050h 0052h 0049h N Addresses Document Number: 002-02003 Rev. *B Page 28 of 64 S29AL032D Table 14. Primary Vendor-Specific Extended Query (Sheet 2 of 2) Addresses Addresses (Models 03, 04 Byte Mode Only) Data 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 00B5h 4Eh 9Ch 00C5h 4Fh 9Eh 000xh Description ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum ig n 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag D es (0 = Model 00, 3 = Model 03, 2 = Model 04) ew 11. Command Definitions rN Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 on page 35 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Reading Array Data om m en 11.1 de d fo All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams under AC Characteristics. The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. ec After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 32 for more information on this mode. ot R The system must issue the reset command in order to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See Reset Command on page 29. N See also Requirements for Reading Array Data on page 11 for more information. The Read Operations on page 47 provides the read parameters, and Figure 17.1 on page 47 shows the timing diagram. 11.2 Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Document Number: 002-02003 Rev. *B Page 29 of 64 S29AL032D 11.3 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether a sector is protected. Table 13 on page 35 shows the address and data requirements. This method is an alternative to that shown in Table on page 19, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address 0XXX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 8 on page 13 and Table 10 on page 15 for valid sector addresses. Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence es 11.4 ig n The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence de 11.5 d fo rN ew D The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 12 on page 34 and Table 13 on page 35 show the addresses and data requirements for both command sequences. Note that the ACC function and unlock bypass modes are not available when the device enters the Secured Silicon Sector. See also Secured Silicon Sector Flash Memory Region on page 24 for further information. om m en Models 03, 04 may program the device by word or byte, depending on the state of the BYTE# pin. Model 00 may program the device by byte only. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 13 on page 35 shows the address and data requirements for the byte program command sequence. R ec When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 37 for information on these status bits. N ot Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. 11.6 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 on page 35 shows the requirements for the command sequence. Document Number: 002-02003 Rev. *B Page 30 of 64 S29AL032D During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Figure 11.1 on page 31 illustrates the algorithm for the program operation. See the Erase/Program Operations on page 50 for parameters, and to Figure 18.1 on page 50 for timing diagrams. Figure 11.1 Program Operation ig n START D es Write Program Command Sequence ew Data Poll from System Verify Data? om m en de d fo rN Embedded Program algorithm in progress N ot R ec Increment Address No Yes No Last Address? Yes Programming Completed Note See Table 13 for program command sequence. 11.7 Chip Erase Command Sequence Chip erase is a six bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 on page 35 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Document Number: 002-02003 Rev. *B Page 31 of 64 S29AL032D The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status on page 37 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 11.2 on page 33 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 50 for parameters, and to Figure 18.2 on page 51 for timing diagrams. 11.8 Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 13 on page 35 shows the address and data requirements for the sector erase command sequence. ig n The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. fo rN ew D es After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. de d The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the DQ3: Sector Erase Timer section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. om m en Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. ec When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status for information on these status bits.) Erase Suspend/Erase Resume Commands N 11.9 ot R Figure 11.2 on page 33 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 50 for parameters, and to Figure 18.2 on page 51 for timing diagrams. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50-s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if it is written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don't cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 37 for information on these status bits. Document Number: 002-02003 Rev. *B Page 32 of 64 S29AL032D After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 37 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 30 for more information. The system must write the Erase Resume command (address bits are don't care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. es ig n Figure 11.2 Erase Operation d fo rN Write Erase Command Sequence ew D START om m en de Data Poll from System No Embedded Erase algorithm in progress N ot R ec Data = FFh? Yes Erasure Completed Notes 1. See Table 13 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 41 for more information. Document Number: 002-02003 Rev. *B Page 33 of 64 S29AL032D 11.10 Command Definitions Table Cycles Table 12. S29AL032D Command Definitions -- Model 00 Command Sequence (Note 1) Bus Cycles (Notes 2-3) First Second Data 1 RA RD Reset (Note 7) Fourth Data Addr Data Addr Data 1 XXX F0 Manufacturer ID (Note 7) 4 XXX AA XXX 55 0XXXXX 90 0XXX00 01 Device ID (Note 7) 4 XXX AA XXX 55 0XXXXX 90 0XXX01 A3 Secured Silicon Sector Factory Protect (Note 14) 4 AAA AA 555 55 AAA 90 X06 85/05 Sector Protect Verify (Note 8) 4 55 0XXXXX or 2XXXXX 90 SA X02 XXX XXX 3 XXX AA XXX 55 XXX 88 Exit Secured Silicon Sector Region 4 XXX AA XXX 55 XXX 90 Byte Program 4 XXX AA XXX 55 XXX A0 Unlock Bypass 3 XXX AA XXX 55 XXX Unlock Bypass Program (Note 9) 2 XXX A0 PA PD Unlock Bypass Reset (Note 10) 2 XXX 90 XXX 00 Chip Erase 6 XXX AA XXX 55 XXX AA XXX B0 Erase Resume (Note 12) 1 XXX 30 CFI Query (Note 13) 1 XXX 98 Legend X = Don't care Data 00 01 XXX XXX 00 PA PD 80 XXX AA XXX 55 XXX 10 80 XXX AA XXX 55 SA 30 ew 20 rN fo XXX d XXX 1 Addr 55 XXX de 6 Erase Suspend (Note 11) om m en Sector Erase Data ig n XXX AA Addr Sixth es XXX Enter Secured Silicon Sector Region ec RA = Address of the memory location to be read RD = Data read from location RA during read operation PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be erased or verified. Address bits A21-A16 uniquely select any sector. N ot R PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse, whichever happens later. Notes Fifth Addr D Autoselect (Note 6) Addr Read (Note 4) Third 1. See Table 8 on page 10 for descriptions of bus operations. 2. All values are in hexadecimal. Except when reading array or autoselect data, all bus cycles are write operations. 3. Address bits are don't care for unlock and command cycles, except when PA or SA is required. 4. No unlock or command cycles required when device is in read mode. 5. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high. 6. The fourth cycle of the autoselect command sequence is a read cycle. 7. In the third and fourth cycles of the command sequence, set A21 to 0. 8. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0-31, or to 1 if verifying sectors 32-64. The data in the fourth cycle is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. Document Number: 002-02003 Rev. *B 9. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 11. The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 12. The Erase Resume command is valid only during the Erase Suspend mode. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. The data is 85h for factory locked and 05h for not factory locked. Page 34 of 64 S29AL032D Cycles Table 13. S29AL032D Command Definitions, x8 Mode -- Models 03, 04 Command Sequence (Note 1) Bus Cycles (Notes 2-5) First Second Addr Data RD Third Fourth Addr Data Addr Data Addr Fifth Data RA 1 XXX F0 Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID, Model 03 4 AAA AA 555 55 AAA 90 X02 22F6 Device ID, Model 04 4 AAA AA 555 55 AAA 90 X02 F9 Secured Silicon Sector Factory Protect, Model 03 (Note 9) 4 AAA AA 555 55 AAA 90 X06 8D/1D Secured Silicon Sector Factory Protect, Model 04 (Note 9) 4 AAA AA 555 55 AAA 90 X06 9D/0D Sector Protect Verify (Note 10) 4 AAA AA 555 55 AAA 90 (SA)X04 Enter Secured Silicon Sector Region 3 AAA AA 555 55 AAA 88 Exit Secured Silicon Sector Region 4 AAA AA 555 55 AAA 90 CFI Query (Note 11) 1 AA 98 Program 4 AAA AA 555 55 AAA A0 AAA 20 55 PA PD Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00 Chip Erase 6 AAA AA 555 55 Sector Erase 6 AAA AA 555 55 Erase Suspend (Note 14) 1 XXX B0 Erase Resume (Note 15) 1 XXX X = Don't care Data D es (Note 10) 00 PA PD AAA 80 AAA AA 555 55 AAA 10 AAA 80 AAA AA 555 55 SA 30 om m en Legend XXX ew 555 A0 Addr rN AA XXX fo AAA 2 d 3 Unlock Bypass Program (Note 12) de Unlock Bypass Sixth Data ig n 1 Reset (Note 7) Autoselect (Note 8) Read (Note 6) Addr 30 RA = Address of the memory location to be read ec RD = Data read from location RA during read operation SA = Address of the sector to be erased or verified. Address bits A19-A12 uniquely select any sector. Notes ot R PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse, whichever happens first. N 1. See Table 8 on page 10 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits A19-A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not factory locked. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence"for more information. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0h is also acceptable. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode. Document Number: 002-02003 Rev. *B Page 35 of 64 S29AL032D Cycles Table 14. S29AL032D Command Definitions, x16 Mode -- Models 03, 04 Bus Cycles (Notes 2-5) First Second Data RD Fourth Addr Data Addr Data Addr Fifth Data RA 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01 Device ID, Model 03 4 555 AA 2AA 55 555 90 X01 22F6 Device ID, Model 04 4 555 AA 2AA 55 555 90 X01 22F9 Secured Silicon Sector Factory Protect, Model 03 (Note 9) 4 555 AA 2AA 55 555 90 X03 8D/0D Secured Silicon Sector Factory Protect, Model 04 (Note 9) 4 555 AA 2AA 55 555 90 X03 9D/1D Sector Protect Verify (Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 Enter Secured Silicon Sector Region 3 555 AA 2AA 55 555 88 Exit Secured Silicon Sector Region 4 555 AA 2AA 55 555 90 CFI Query (Note 11) 1 55 98 Program 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 Unlock Bypass Program (Note 12) 2 XXX A0 PA PD Unlock Bypass Reset (Note 13) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 Sector Erase 6 555 AA 2AA 55 555 Erase Suspend (Note 14) 1 XXX B0 Erase Resume (Note 15) 1 XXX X = Don't care Sixth Data Addr Data es (Note 10) D XXX ew d de om m en Legend Addr ig n 1 Reset (Note 7) Autoselect (Note 8) Read (Note 6) rN Addr Third fo Command Sequence (Note 1) 00 PA PD 80 555 AA 2AA 55 555 10 80 555 AA 2AA 55 SA 30 20 30 RA = Address of the memory location to be read ec RD = Data read from location RA during read operation SA = Address of the sector to be erased or verified. Address bits A19-A12 uniquely select any sector. Notes ot R PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse, whichever happens first. N 1. See Table 8 on page 10 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits A19-A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not factory locked. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence"for more information. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume command is valid only during the Erase Suspend mode. Document Number: 002-02003 Rev. *B Page 36 of 64 S29AL032D 12. Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 13 on page 41 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. 12.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. es ig n During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. rN ew D During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. fo After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. om m en de d When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 18.4 on page 52, Data# Polling Timings (During Embedded Algorithms), under AC Characteristics on page 47 illustrates this. N ot R ec Figure 13 on page 41 shows the outputs for Data# Polling on DQ7. Figure 12.2 on page 40 shows the Data# Polling algorithm. Document Number: 002-02003 Rev. *B Page 37 of 64 S29AL032D Figure 12.1 Data# Polling Algorithm START Read DQ7-DQ0 Addr = VA Yes ig n DQ7 = Data? No es No ew D DQ5 = 1? rN Yes Yes om m en DQ7 = Data? de d fo Read DQ7-DQ0 Addr = VA No PASS R ec FAIL ot Notes 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. N 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 12.2 RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 13 on page 41 shows the outputs for RY/BY#. Figures Figure 17.1 on page 47, Figure 17.2 on page 48, Figure 18.1 on page 50 and Figure 18.2 on page 51 shows RY/BY# for read, reset, program, and erase operations, respectively. Document Number: 002-02003 Rev. *B Page 38 of 64 S29AL032D 12.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. ig n The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling on page 37). es If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. D DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. DQ2: Toggle Bit II d 12.4 fo rN ew Table 13 on page 41 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 40 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 39 explains the algorithm. Figure 18.5 on page 53 shows the toggle bit timing diagrams. Figure 18.6 on page 53 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. om m en de The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. ec DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13 on page 41 to compare outputs for DQ2 and DQ6. 12.5 N ot R Figure 12.2 on page 40 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 39 explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 18.5 on page 53 shows the toggle bit timing diagram. Figure 18.6 on page 53 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 12.2 on page 40 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, then the device has successfully completed the program or erase operation. If it is still toggling, then the device had not complete the operation successfully, and the system must write the reset command in order to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 12.2 on page 40). Document Number: 002-02003 Rev. *B Page 39 of 64 S29AL032D Figure 12.2 Toggle Bit Algorithm START Read DQ7-DQ0 (Note 1) ig n Read DQ7-DQ0 D es No Toggle Bit = Toggle? rN No ew Yes de om m en Yes d fo DQ5 = 1? (Notes 1, 2) Read DQ7-DQ0 Twice No N ot R ec Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. 12.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1. Document Number: 002-02003 Rev. *B Page 40 of 64 S29AL032D Under both these conditions, the system must issue the reset command to return the device to reading array data. 12.7 DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also Sector Erase Command Sequence on page 32. Table 13. Write Operation Status Embedded Erase Algorithm 0 Toggle Reading within Erase Suspended Sector 1 No toggle Reading within Non-Erase Suspended Sector Data Data Erase-Suspend-Program DQ7# d Erase Suspend Mode Toggle DQ2 (Note 2) RY/BY# 0 N/A No toggle 0 0 1 Toggle 0 0 N/A Toggle 1 Data Data Data 1 0 N/A N/A 0 D Toggle DQ3 ew DQ7# Embedded Program Algorithm de Standard Mode DQ5 (Note 1) rN DQ6 fo DQ7 (Note 2) Operation es ig n After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device accepts the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure that the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the outputs for DQ3. om m en Notes 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits on page 40 for more information. N ot R ec 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. Document Number: 002-02003 Rev. *B Page 41 of 64 S29AL032D 13. Absolute Maximum Ratings Table 14. Absolute Maximum Ratings Parameter Rating -65C to +150C Storage Temperature, Plastic Packages -65C to +125C Ambient Temperature with Power Applied -0.5 V to +4.0 V VCC (Note 1) Voltage with Respect to Ground -0.5 V to +12.5 V A9, OE#, and RESET# (Note 2) -0.5 V to VCC+0.5 V All other pins (Note 1) 200 mA ig n Output Short Circuit Current (Note 3) es Notes 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1 on page 42. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 14.2 on page 42. D 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 14.1 on page 42. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. ew 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. fo rN 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. d Figure 14.1 Maximum Negative Overshoot Waveform om m en +0.8 V 20 ns de 20 ns -0.5 V 20 ns R ec -2.0 V ot Figure 14.2 Maximum Positive Overshoot Waveform N 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns Document Number: 002-02003 Rev. *B Page 42 of 64 S29AL032D 14. Operating Ranges Table 15. Operating Ranges Parameter Range Ambient Temperature (TA) VCC Supply Voltages Industrial (I) Devices -40C to +85C Extended (N) Devices -40C to +125C VCC for standard voltage range 2.7 V to 3.6 V N ot R ec om m en de d fo rN ew D es ig n Note Operating ranges define those limits between which the functionality of the device is guaranteed. Document Number: 002-02003 Rev. *B Page 43 of 64 S29AL032D 15. DC Characteristics Table 16. DC Characteristics, CMOS Compatible Test Conditions Min ILI Input Load Current (Note 1) VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ILO VCC Active Read Current (Notes 2, 3) Max Unit 1.0 A 35 A 1.0 A 10 MHz 15 30 5 MHz 9 16 1 MHz 2 4 10 MHz 18 35 9 16 2 4 15 35 mA CE# = VIL, OE# = VIH, Byte Mode ICC1 Typ CE# = VIL, OE# = VIH, Word Mode ig n Description 5 MHz 1 MHz es Parameter mA CE# = VIL, OE# = VIH ICC3 VCC Standby Current (Notes 3, 5) CE#, RESET# = VCC0.3 V 0.2 5 A ICC4 VCC Standby Current During Reset (Notes 3, 5) RESET# = VSS 0.3 V 0.2 5 A ICC5 Automatic Sleep Mode (Notes 3, 5, 7) VIH = VCC 0.3 V; VIL = VSS 0.3 V 0.2 5 A IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH 5 10 mA ew rN fo d mA V 0.7 x VCC VCC + 0.3 V VCC = 3.0 V 10% 11.5 12.5 V Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V Input High Voltage VHH Voltage for WP#/ACC Sector Protect/ Unprotect and Program Acceleration VID VOL VCC pin R ec om m en VIH ot Output High Voltage 15 IOH = -2.0 mA, VCC = VCC min 2.4 V IOH = -100 A, VCC = VCC min VCC-0.4 V Low VCC Lock-Out Voltage (Note 4) N VLKO de 30 0.8 Input Low Voltage VOH2 ACC pin -0.5 VIL VOH1 D ICC2 VCC Active Write Current (Notes 3, 4, 6) 2.3 2.5 V Notes 1. On the ACC pin only, the maximum input load current when ACC = VIL is 5.0 A. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 3. Maximum ICC specifications are tested with VCC = VCCmax. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. At extended temperature range (>+85C), maximum current is 15 A. 6. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 7. Not 100% tested. Document Number: 002-02003 Rev. *B Page 44 of 64 S29AL032D 15.1 Zero Power Flash Figure 15.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 25 Supply Current in mA 20 15 ig n 10 0 500 1000 1500 2000 2500 D 0 es 5 3000 3500 4000 ew Time in ns Figure 15.2 Typical ICC1 vs. Frequency d fo rN Note Addresses are switching at 1 MHz. de 10 om m en 6 3.6 V 2.7 V ec Supply Current in mA 8 2 N ot R 4 0 1 2 3 Frequency in MHz 4 5 Note T = 25C Document Number: 002-02003 Rev. *B Page 45 of 64 S29AL032D 16. Test Conditions Figure 16.1 Test Setup 3.3 V 2.7 k Device Under Test CL ew D es ig n 6.2 k fo Table 17. Test Specifications Speed Option 70 90 de Output Load Capacitance, CL (including jig capacitance) Input Pulse Levels Input timing measurement reference levels 100 pF 5 ns 0.0 or VCC V 0.5 VCC V 0.5 VCC V ec Output timing measurement reference levels om m en 30 Input Rise and Fall Times Unit 1 TTL gate d Output Load R Key to Switching Waveforms Waveform N ot 16.1 rN Note Diodes are IN3064 or equivalent. Inputs Outputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) Document Number: 002-02003 Rev. *B Page 46 of 64 S29AL032D Figure 16.1 Input Waveforms and Measurement Levels VCC 0.5 VCC Input 0.5 VCC Measurement Level Output 0.0 V 17. AC Characteristics Read Operations Parameter Speed Options Description Std tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL tELQV tCE Chip Enable to Output Delay OE# = VIL tGLQV tOE Output Enable to Output Delay tEHQZ tDF Chip Enable to Output High Z (Note 1) tDF Output Enable to Output High Z (Note 1) 90 Unit 70 90 ns Max 70 90 ns Max 70 90 ns Max 30 35 ns Latency Between Read and Write Operations tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) fo Read Toggle and Data# Polling de Max 16 ns Max 16 ns Min 20 ns Min 0 ns Min 10 ns Min 0 ns om m en tAXQX 70 Min D ew rN tSR/W d tGHQZ Test Setup es JEDEC ig n 17.1 Notes 1. Not 100% tested. 2. See Figure 16.1 on page 46 and Table 17 on page 46 for test specifications. R ec Figure 17.1 Read Operations Timings tRC ot Addresses Stable N Addresses tACC CE# tDF OE# tOE tSR/W tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Document Number: 002-02003 Rev. *B Page 47 of 64 S29AL032D Hardware Reset (RESET#) Parameter JEDEC Description Std. All Speed Options Test Setup Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 s tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 s tRB RY/BY# Recovery Time Min 0 ns es ig n 17.2 D Note Not 100% tested. rN ew Figure 17.2 RESET# Timings d fo RY/BY# de CE#, OE# om m en tRH RESET# tRP ec tReady Reset Timings during Embedded Algorithms N ot R Reset Timings NOT during Embedded Algorithms tReady RY/BY# tRB CE#, OE# tRH RESET# tRP Document Number: 002-02003 Rev. *B Page 48 of 64 S29AL032D 17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only) Parameter JEDEC Speed Options Std. Description 70 tELFL/tELFH CE# to BYTE# Switching Low or High Max tFLQZ BYTE# Switching Low to Output HIGH Z Max tFHQV BYTE# Switching High to Output Active Min 90 5 ns 16 70 Unit ns 90 ns Figure 17.3 BYTE# Timings for Read Operations ig n CE# D es OE# rN tELFL Data Output (DQ0-DQ14) Data Output (DQ0-DQ7) d fo DQ0-DQ14 de DQ15/A-1 om m en BYTE# Switching from word to byte mode ew BYTE# Address Input DQ15 Output tFLQZ tELFH R DQ0-DQ14 ot BYTE# Switching from byte to word mode ec BYTE# N DQ15/A-1 Data Output (DQ0-DQ7) Address Input Data Output (DQ0-DQ14) DQ15 Output tFHQV Document Number: 002-02003 Rev. *B Page 49 of 64 S29AL032D Figure 17.4 BYTE# Timings for Write Operations CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Table 18. Erase/Program Operations tWC Write Cycle Time (Note 1) tAS Address Setup Time tWLAX tAH Address Hold Time tDVWH tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL tGHWL d Speed Options 70 Min 90 70 Min 90 0 Unit ns ns Min 45 45 ns Min 35 45 ns Min 0 ns Min 0 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns om m en tWHDX fo tAVAV tAVWL rN Description de Std. ew Parameter JEDEC es Erase/Program Operations D 17.4 ig n Note Refer to the Erase/Program Operations table for tAS and tAH specifications. tCS CE# Setup Time Min 0 ns tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations ns ot R ec tELWL tWHEH 35 Min 20 Byte Typ 9 Word Typ 11 ns tWHWH1 tWHWH1 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 s tWHWH2 tWHWH2 N Programming Operation (Note 2) 35 s Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 s tRB Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 57 for more information. Figure 18.1 Program Operation Timings Notes 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Document Number: 002-02003 Rev. *B Page 50 of 64 S29AL032D Program Command Sequence (last two cycles) tAS tWC 555h Addresses Read Status Data (last two cycles) PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# PD A0h Data es tDH Status tRB ew tBUSY DOUT D tDS ig n tWPH tCS RY/BY# rN tVCS fo VCC de d Figure 18.2 Chip/Sector Erase Operation Timings tWC 2AAh Addresses om m en Erase Command Sequence (last two cycles) Read Status Data tAS VA SA VA 555h for chip erase tCH N ot R OE# WE# tAH ec CE# tWP tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 37). 2. Illustration shows device in word mode. Document Number: 002-02003 Rev. *B Page 51 of 64 S29AL032D Figure 18.3 Back to Back Read/Write Cycle Timing tWC Addresses tRC PA RA PA tACC tAH tCPH tCE CE# PA tCP tOE tSR/W OE# tGHWL tWP tWDH tDS Data tDF tOH tDH Valid Out Valid In Valid Out ew D es Valid In ig n WE# rN Figure 18.4 Data# Polling Timings (During Embedded Algorithms) Addresses fo tRC VA VA de d tACC tCE om m en CE# tCH tOE OE# tOEH tDF ec WE# ot N DQ0-DQ6 R DQ7 VA tOH High Z Complement Complement Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Document Number: 002-02003 Rev. *B Page 52 of 64 S29AL032D Figure 18.5 Toggle Bit Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# Valid Status Valid Status (first read) (second read) Valid Data (stops toggling) D tBUSY Valid Status es DQ6/DQ2 ig n tOH High Z ew RY/BY# fo rN Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Enter Embedded Erasing Erase WE# Erase Suspend Program Erase Suspend Read Erase Complete Erase R ot DQ2 Erase Suspend Read Erase Resume ec DQ6 Enter Erase Suspend Program om m en Erase Suspend de d Figure 18.6 DQ2 vs. DQ6 for Erase and Erase Suspend Operations N Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. 17.5 Temporary Sector Unprotect Table 18. Temporary Sector Unprotect Parameter JEDEC Std. All Speed Options Description Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 s Note Not 100% tested. Figure 18.1 Temporary Sector Unprotect Timing Diagram Document Number: 002-02003 Rev. *B Page 53 of 64 S29AL032D 12 V RESET# 0 or 3 V Program or Erase Command Sequence tVIDR tVIDR CE# ig n WE# es tRSP ew D RY/BY# rN Figure 18.2 Accelerated Program Timing Diagram VIL or VIH tVHH N ot R ec tVHH de VIL or VIH om m en WP#/ACC d fo VHH Document Number: 002-02003 Rev. *B Page 54 of 64 S29AL032D Figure 18.3 Sector Protect/Unprotect Timing Diagram VID VIH RESET# Valid* Valid* Sector Protect/Unprotect Data 60h Valid* Verify 60h 40h Sector Protect: 150 s Sector Unprotect: 15 ms es 1 s Status ig n SA, A6, A1, A0 ew D CE# rN WE# d fo OE# 17.6 om m en de Note For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Alternate CE# Controlled Erase/Program Operations Table 18. Alternate CE# Controlled Erase/Program Operations ec Parameter Speed Options Std. tAVAV tWC Write Cycle Time (Note 1) Description Min tAVEL tAS Address Setup Time Min tELAX tAH ot R JEDEC N Address Hold Time 70 90 Unit 70 90 ns 45 ns 45 ns 0 Min 45 35 ns tDVEH tDS Data Setup Time Min tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min tELEH tCP CE# Pulse Width Min tCPH CE# Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 20 ns tEHEL tWHWH1 tWHWH1 Programming Operation (Note 2) Document Number: 002-02003 Rev. *B 0 35 ns 35 Byte Typ 9 Word Typ 11 ns s Page 55 of 64 S29AL032D Table 18. Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std. Description 70 90 Unit tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 s tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec Notes 1. Not 100% tested. 2. See the Erase and Programming Performance on page 57 section for more information. PA for program SA for sector erase 555 for chip erase Data# Polling es 555 for program 2AA for erase ig n Figure 18.1 Alternate CE# Controlled Write Operation Timings PA tWC D Addresses ew tAS tAH rN tWH fo WE# tGHEL CE# tWS tWHWH1 or 2 om m en tCP de d OE# tCPH tDS tBUSY ec tDH DQ7# DOUT PD for program 30 for sector erase 10 for chip erase N RESET# A0 for program 55 for erase ot tRH R Data RY/BY# Notes 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Document Number: 002-02003 Rev. *B Page 56 of 64 S29AL032D 18. Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Unit Sector Erase Time (Note 7) 0.7 10 s Chip Erase Time (Note 8) 45 Excludes 00h programming prior to erasure (Note 4) s Byte Programming Time 9 300 s Word Programming Time 11 360 s Accelerated Byte/Word Programming Time 7 210 s Chip Programming Time Byte Mode 36 108 s (Note 3) Word Mode 24 72 s Comments Excludes system level overhead (Note 5) Notes 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. ig n 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. es 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. ew D 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 7. At extended temperature range (>+85C), typical erase time is 1.75 s and maximum erase time is 25 s. fo rN 8. At extended temperature range (>+85C), typical erase time is 112 s. d 19. TSOP and BGA Pin Capacitance Parameter Description CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 om m en ec Package Typ Max Unit TSOP 6 7.5 pF BGA 4.2 5.0 pF TSOP 8.5 12 pF BGA 5.4 6.5 pF TSOP 7.5 9 pF BGA 3.9 4.7 pF R Test Setup ot Notes 1. Sampled, not 100% tested. de Parameter Symbol N 2. Test conditions TA = 25C, f = 1.0 MHz.Physical Dimensions Document Number: 002-02003 Rev. *B Page 57 of 64 S29AL032D TS040--40-Pin Standard TSOP Dwg rev AA; 10/99 N ot R ec om m en de d fo rN ew D es ig n 19.1 Document Number: 002-02003 Rev. *B Page 58 of 64 Dwg rev AA; 10/99 N ot R ec om m en de d fo rN ew D es ig n S29AL032D Document Number: 002-02003 Rev. *B Page 59 of 64 S29AL032D 19.2 TS 048--48-Pin Standard TSOP 2X 0.10 STANDARD PIN OUT (TOP VIEW) 2X (N/2 TIPS) 2X 2 0.10 0.10 1 A2 N SEE DETAIL B 3 B 1 E 5 e N +1 2 N 2 ig n C SEATING PLANE B A B N +1 2 N 2 SEE DETAIL A 0.08MM es 0.25 A1 4 D 2X (N/2 TIPS) 9 5 D1 N (0.0031") M D A REVERSE PIN OUT (TOP VIEW) 6 (c) S 7 WITH PLATING c1 de d fo 7 rN ew b C A-B om m en R b1 SECTION B-B BASE METAL (c) q 0.25MM (0.0098") BSC ec PARALLEL TO SEATING PLANE e/2 GAUGE PLANE R L X C DETAIL B N ot DETAIL A X = A OR B NOTES: Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MO-142 (D) DD MIN NOM MAX 1.20 0.15 0.05 0.95 1.00 1.05 0.20 0.23 0.17 0.17 0.22 0.27 0.10 0.16 0.10 0.21 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.50 0.60 0.70 0 8 0.08 0.20 48 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) 2 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). 7 THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. 8 LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3355 \ 16-038.10c * For reference only. BSC is an ANSI standard for Basic Space Centering. Document Number: 002-02003 Rev. *B Page 60 of 64 S29AL032D 19.3 VBN048--48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm D D1 A e 6 e 5 4 +0.20 1.00-0.50 E 7 SE E1 3 2 O0.50 1 +0.20 1.00 -0.50 B A1 ID. 6 G F E C 0.08 C SEATING PLANE 7 es A1 CORNER d fo rN A1 A ew 0.10 C B D O0.15 M C A B A2 C SD Ob O0.08 M C A D ig n H NOTES: VBN 048 N/A om m en JEDEC de PACKAGE 10.00 mm x 6.00 mm NOM PACKAGE MIN NOM MAX A --- --- 1.00 A1 0.17 --- --- A2 0.62 --- 0.73 10.00 BSC. E 6.00 BSC. 5.60 BSC. E1 4.00 BSC. MD 8 BODY SIZE BALL FOOTPRINT BALL FOOTPRINT 6 N fb BODY SIZE N ME 48 0.35 BODY THICKNESS ot D1 BALL HEIGHT R D NOTE OVERALL THICKNESS ec SYMBOL --- ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT 0.45 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT NONE DEPOPULATED SOLDER BALLS 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3425\ 16-038.25 Document Number: 002-02003 Rev. *B Page 61 of 64 S29AL032D 20. Document History Page Document Title:S29AL032D 32 Mbit, 3 V, Flash 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector Document Number: 002-02003 Rev. ECN No. Orig. of Change Submission Date Description of Change 01/31/2005 Initial release Spansion Publication Number: S29AL032D_00 03/16/2005 Distinctive Characteristics Revised Secured Silicon Sector with 128-word information. Common Flash Memory Interface -- (CFI) Modified Primary VendorSpecific Extended Query table information for 45h address.. RYSU D - om m en de d fo rN ew ** es ig n 04/19/2005 Valid Combinations Table Clarified available packing types for TSOP and FBGA package. Modified Note 1. Device Bus Operations Added Secured Silicon Sector Addresses--Model 00 table Modified Top Boot Secured Silicon Sector Addresses--Model 03 and Bottom Boot Secured Silicon Sector Addresses--Model 04 tables S29AL032D Command Definitions Model 00 table Added Secured Silicon Sector Factory Protect information. Accelerated Program Operation Added section. Secured Silicon Sector Added section. AC Characteristics Added ACC programming timing diagram - RYSU N ** ot R ec 06/13/2005 Autoselect Mode Updated Table 8 to include models 00, 03, and 04. Common Flash Memory Interface Updated table headings in table 12, 13, 14, and 15. Absolute Maximum Rating Updated figure 8. DC Characteristics Updated CMOS Compatible table. AC Characteristics Updated Erase/Program Operations table. Added new figure: Back-to-Back Read/Write Cycle Timing. Updated Alternate CE# Controlled Erase/Program Operations table. 07/29/2005 DS Status Change of DS status to "Preliminary" from "Advance Information". Output Disable Mode Updated Model 00 Secured Silicon Sector Analysis table. Autoselect Mode Updated S29AL032D Autoselect Codes (High Voltage Method) table. Document Number: 002-02003 Rev. *B Page 62 of 64 S29AL032D Document Title:S29AL032D 32 Mbit, 3 V, Flash 4 M x 8-Bit Uniform Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector Document Number: 002-02003 Rev. ECN No. Orig. of Change ** - RYSU Submission Date Description of Change 09/21/2005 DS Status Change of DS status to "Preliminary" from "Advance Information". Sector Protection/Unprotection Corrected "In-System Sector Protect/Unprotect Algorithms" figure. 05/22/2006 AC Characteristics ig n Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram. Changed maximum value for tDF and tFLQZ. fo rN ew D es 06/19/2006 Ordering Information Added extended temperature range options to valid combinations. Common Flash Memory Interface (CFI) Primary Vendor-Specific Extended Query table: Change description for data at address 4Fh (address 9Eh on Models 03, 04). DC Characteristics Changed Note 4. Read Operations Timings figure Connected end of tRC period to start of tOH period. RYSU *A 5038714 RYSU *B 5075821 RYSU 01/19/2007 Autoselect Code (High Voltage Method)table; Command Definitions, x8 Mode--Models 03, 04 table Corrected data for Secured Silicon Sector Sector Indicator Bit. 12/07/2015 Updated to cypress template ec - 01/08/2016 Added a note in blue font in page 1 showing the suggested replacement parts. Removed Spansion Revision History. N ot R ** Valid Combinations Updated table. om m en 11/02/2006 de d Erase and Programming Performance Added Notes 7 and 8 to table. Document Number: 002-02003 Rev. *B Page 63 of 64 S29AL032D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC(R) Solutions Automotive..................................cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers ................................ cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface......................................... cypress.com/go/interface Cypress Developer Community Lighting & Power Control............ cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory........................................... cypress.com/go/memory Technical Support PSoC ....................................................cypress.com/go/psoc cypress.com/go/support ig n Touch Sensing .................................... cypress.com/go/touch USB Controllers....................................cypress.com/go/USB N ot R ec om m en de d fo rN ew D es Wireless/RF .................................... cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2005-2016. 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Document Number: 002-02003 Rev. *B (R) (R) (R) (R) Revised January 08, 2016 Page 64 of 64 Cypress , Spansion , MirrorBit , MirrorBit EclipseTM, ORNANDTM, EcoRAMTM, HyperBusTM, HyperFlashTM, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.