82284 82284 Clock Driver and Ready Interface for iAPX 286 Processors PRELIMINARY DISTINCTIVE CHARACTERISTICS Generates system clock for iAPX 286 processors @ Uses crystal or TTL signal for frequency source Provides local READY and MULTIBUS* READY synchronization Generates system reset output from Schmitt Trigger input @ 18-pin package @ Single +5 V power supply GENERAL DESCRIPTION The 82284 is a clock generator/driver which provides clock signals tor iAPX 286 processors and support components. The device contains logic to supply READY to the CPU from either asynchronous or synchronous sources. It also generates a synchronous reset signal from an asynchro- nous input with hysteresis. BLOCK DIAGRAM RESET RES > ff SYNCHRONIZER t- * XTAL Xo osc MUX CLK EFI >, Fe wg APOVEN eae SYNCHRONIZER ARDY + T OVEN READY LOGIC. _ > READY soy ry 51 PCLK ~ GENERATOR > PCLK s BD007270 *MULTIBUS is a registered trademark of Intel Corporation. Publication # Rev. Al nt 05917 c /0 3-260 Issue Date: May 1987CONNECTION DIAGRAMS Top View DIPs PLCC G > e > Q {!a oO 1a \ } ac |e c aroy [[]1 18 Voc E <2 3k SRDY [] 2 17 [7] ARDYEN Litt SROYEN 3 16 51 C LI _ SRDYEN { | 4 ig | | 51 READY [_] 4 15 {_] 0 READY ["] 5 17] 50 EFI] 5 14 [7] NC EFI Fe (16 13 [[] PCLK || 6 16 |_| Ne FIG POLK x, (7 12 {_] RESET L|7 151 x, C48 11 [7 RES X, fe 14|_] RESET 9 GND [| 9 10 [7] cLk TOT oo nn a Oo x mM CD010750 < a Zz 3 My CD010760 Note: Pin 1 is marked for orientation. LOGIC SYMBOL ARDY SRDY SRDYEN EFI FIC XXp RES 50, $1 ARDYEN READY -_ CLK --> RESET -> PCLK -}> LSo03040 3-261 oa N J oo &82284 ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type c. Device Number d. Speed Option e. Optional Processing } to | L. e. OPTIONAL PROCESSING Blank = Standard processing B = Burn-in d. SPEED OPTION Blank = 8 MHz -10=10 MHz c. DEVICE NUMBER/DESCRIPTION 82284 Clock Driver and Ready Interface for iAPX 286 Processors b. PACKAGE TYPE P = 18-Pin Plastic DIP (PD 018) D=18-Pin Ceramic DIP (CD 018) N = 20-Pin Plastic Leaded Chip Carrier a. TEMPERATURE RANGE Blank = Commercial (0 to + 70C) Valid Combinations Valid Combinations 62284 Valid Combinations list configurations planned to be 82284-10 supported in volume for this device. Consult the local AMD 822648 sales office to confirm availability of specific valid P,D combinations, to check on newly released valid combinations, 82284-10B Unpackaged Di AMB2284XC and to obtain additional data on AMD's standard military npackssoc = grade products. P,D,N 3-262PIN DESCRIPTION ARDY Asynchronous Ready (Input; Active LOW) ARDY is an active-LOW input used to terminate the current bus cycle. The ARDY input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous inputs. ARDYEN Asynchronous Ready Enable (Input; Active LOW) ARDYEN is an active-LOW input which qualifies the ARDY input. ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous inputs. CLK System Clock (Output) CLK output is used by the processor and any support devices which must be synchronized with the processor. The frequency of the CLK output is twice the processor's internal clock frequency. CLK can drive both TTL and MOS level inputs. EF! External Frequency In (input) The EFI input drives CLK when F/T is strapped HIGH. The EFI input frequency must be twice the processor's internal clock frequency. F/G Frequency/Crystal Select (Input) F/T is a strapping option used to select the source for the CLK output. When F/T is strapped LOW, the internal crystal drives CLK. When F/T is strapped HIGH, the EFI input drives the CLK output. GND System Ground: 0 V PCLK Peripheral Clock (Output) PGCLK is an output which provides a 50% duty cycle clock with one half the frequency of CLK. PCLK will be in phase with the processor's internal clock following the first bus cycle after the processor has been reset. READY Ready (Output; Active LOW) READY is an active-LOW output which signals the current bus cycle is to be completed. The SRDY, SRDYEN, ARDY, ARDYEN, S17, SO and RES inputs control READY as explained later in the READY generator section. READY is an open collector output requiring an external 910 ohm pull- up resistor. RES eset In (Input; Active LOW) RES is an active-LOW input which generates the system reset signal RESET. Signals to RES may be applied asynchronously to CLK. A Schmitt Trigger input is provided on RES, so that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed response to synchronous inputs. RESET Reset (Output; Active HIGH) RESET is an active-HIGH output which is derived from the RES input. RESET is used to force the system into an initial state. When RESET is active, READY will be active (LOW). S0, $7 Status (Input) These inputs prepare the 82284 for a subsequent bus cycle. 50 and 87 synchronize PCLK to the internal processor clock and control READY. These inputs have pullup resistors to keep them HIGH if nothing is driving them. Setup and hold times must be satisfied for proper operation. SRDY Synchronous Ready (Input; Active LOW) SADY is an active-LOW input used to terminate the current bus cycle. The SRDY input is qualified by the SADYEN input. Setup and held times must be satisfied for proper operation. SRDYEN Synchronous Ready Enable (Input; Active Low) SRDYEN is an active-LOW input which qualifies SRDY. SRDYEN selects SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold times must be satisfied for proper operation. Vcc +5-V Power Supply (Input) X14, X2 Crystal tn (Input) These are the pins to which a parallel resonant fundamental mode crystal is attached for the internal oscillator. When F/T is strapped LOW, the oscillator will drive the CLK output at the crystal frequency. The crystal frequency must be twice the processor's internal clock frequency. 3-263 eo NS N oe >82284 FUNCTIONAL DESCRIPTION Introduction The 82284 generates the clock, ready, and reset signals required for iAPX 286 processors and support components. The 82284 is packaged in an 18-pin DIP and contains a crystal-controlled oscillator, MOS clock generator, peripheral clock generator, MULTIBUS-ready synchronization logic and system reset generation logic. Clock Generator The CLK output provides the basic timing control for an iAPX 286 system. CLK has output characteristics sufficient to drive MOS devices. CLK is generated by either an internal crystal oscillator or an external source as selected by the F/C strapping option. When F/T is LOW, the crystal oscillator drives the CLK output. When F/T is HIGH, the EFI input drives the CLK output. The 82284 provides a second clock output {PCLK) for peripheral devices. PCLK is CLK divided by two. PCLK has a duty cycle of 50% and TTL output drive characteristics. PCLK is normally synchronized to the internal processor clock. After reset, the PCLK signal may be out of phase with the internal processor clock. The $7 and SO signals of the first bus cycle are used to synchronize PCLK to the internal processor clock. The phase of the PCLK output changes by extending its HIGH time beyond one system clock (see waveforms). PCLK is forced HIGH when either SO or S71 was active (LOW) for the two previous CLK cycles. PCLK continues to oscillate when both SO and $1 are HIGH. Since the phase of the internal processor clock will not change except during reset, the phase of PCLK will not change except during the first bus cycle after reset. Oscillator The oscillator circuit of the 82284 is a linear Pierce oscillator which requires an external parallel resonant fundamental mode crystal. The output of the oscillator is internally buffered. The crystal frequency chosen should be twice the processor's internal clock frequency. The crystal should have a typical load capacitance of 32 pF. X41 and Xe are the oscillator crystal connections. For stable operation of the oscillator, two loading capacitors are recom- mended, as shown in Figure 1. The sum of the board capacitance and loading capacitance should equal the values shown. It is advisable to limit stray board capacitances (not including the effect of the loading capacitors or crystal capacitance) to less than 10 pF between the X1 and Xg pins. Voc and GND pins should be decoupled as close to the 82284 as possible. Figure 1. Recommended Crystal and READY Connections x | 82284 x, FIC CLK CLK Voc iAPX 288 CPU OR 910 SUPPORT a COMPONENT READY READY Yoo Vec DECOUPLING . F SEE TABLE 1 FOR CAPACITOR VALUES | CAPACITOR TC004240 TABLE 1. 82284 CRYSTAL LOADING CAPACITANCE VALUES C,; Capacitance Co Capacitance Crystal Frequency (pin 7) (pin 8) 1 to 8 MHz 60 pF 40 pF 8 to 16 MHz 25 pF 15 pF Note: Capacitance values must include stray board capacitance. 3-264Reset Operation The reset logic provides the RESET output to force the system into a known, initial state. When the RES input is active (LOW), the RESET output becomes active (HIGH). RES is synchro- nized internally at the falling edge of CLK before generating the RESET output (see waveforms). Synchronization of the RES input introduces a one or two CLK delay before affecting the RESET output. At power up, a system does not have a stable Vcc and CLK. To prevent spurious activity, RES should be asserted until Voc and CLK stabilize at their operating values. iAPX 286 proces- sors and support components also require their RESET inputs be HIGH a minimum of 16 CLK cycles. An RC network, as shown in Figure 2, will keep RES LOW long enough to satisfy both needs. A Schmitt Trigger input with hysteresis on RES assures a single transition of RESET with an RC circuit on RES. The hysteresis separates the input voltage level at which the circuit output switches from HIGH to LOW from the input voltage level at which the circuit output switches from LOW to HIGH. The RES HIGH to LOW input transition voltage is lower than the RES LOW to HIGH input transition voltage. As long as the slope of the RES input voltage remains in the same direction (increasing or decreasing) around the RES input transition voltage, the RESET output will make a single transition. Ready Operation The 82284 accepts two ready sources for the system ready signal which terminates the current bus cycle. Either a synchronous (SRDY) or asynchronous ready (ARDY) source may be used. Each ready input has an enable (SRDYEN and ARDYEN) for selecting the type of ready source required to terminate the current bus cycle. An address decoder would normally select one of the enable inputs. READY is enabled (LOW) if either SRDY + SRDYEN =0 or ARDY + ARDYEN = 0 when sampled by the 82284 READY generation fogic. READY will remain active for at least two CLK cycles, except when RESET overrides it. The READY output has an open-collector driver allowing other ready circuits to be wire ORed with it, as shown in Figure 1. The READY signal of an iAPX 286 system requires an external 910 ohm + 5% pull-up resistor. To force the READY signal inactive (HIGH) at the start of a bus cycle, the READY output floats when either ST or SO are sampled LOW at the falling edge of CLK. Two system clock periods are allowed for the pull-up resistor to pull the READY signal to Vjy. When RESET is active, READY is forced active one CLK later (see wave- forms). Figure 3 illustrates the operation of SRDY and SADYEN. These inputs are sampled on the falling edge of CLK when ST and 50 are inactive and PCLK is HIGH. READY is forced active when both SRDY and SROYEN are sampled as LOW. Figure 4 shows the operation of ARDY and ARDYEN. These inputs are sampled by an interna! synchronizer at each falling edge of CLK. The output of the synchronizer is then sampled when PCLK is HIGH. If the synchronizer resolved both the ARDY and ARDYEN inputs to have been LOW, READY, becomes LOW. When both ARDY and ARDYEN have been resolved as active, the SHDY and SADYEN inputs are ignored. Either ARDY or ARDYEN must be HIGH at the end of Tg (see Figure 4). READY remains active until either S1 or SO are sampled LOW, or the ready inputs are sampled as inactive. Voc 82284 > 1NQ14 S 10kQ ANY RES j 470 | 10 pF TCG04250 Figure 2. Typical RC RES Timing Circuit 3-265 vezzs82284 UWE Vin AROVEN ~~ MMM Wo Figure 3. Synchronous Ready Operation 1, yy 1 1 ARDYEN Ca | ; ; ye 4 ' ' ov IMM \<\ ET * AS mm <CSMA WF024521 Figure 4. Asynchronous Ready Operation 3-266ABSOLUTE MAXIMUM RATINGS Storage Temperature ..............cceee -65 to + 150C Temperature Under Bias .............0.:cecereeer eee 0 to +70C All Output and Supply Voltages . .-0.5 Vto +7 V All Input Voltages ................ cece -10 V to +55 V Power Dissipation ...........::ccccecceeseeeeee eer nereeeeeneeenee 1W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TA)... eccceenecrecerereseeteee +0 to +70C Supply Voltage (VCC) 0.0... cece reeeeen eens +45 to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range unless otherwise specified Symbol Description Test Conditions Min. Max. Units VoH RESET, PCLK Output HIGH Voltage lon =-1 MA 2.4 v VoL RESET, PCLK Output LOW Voltage lol =5 mA 45 v VIH input HIGH Voltage 2.0 Vv VIL input LOW Voltage 0.8 v Vo Input Forward Clamp Voltage Io = -5 mA -1.0 Vv Me Input LOW Current -0.5 mA ly Input HIGH Current 50 LA VIHR RES Input HIGH Voltage 2.6 v Vuys RES input Hyste: 0.25 v VoLR READY OulbutiGev"y olfes loL=7 mA 45 Vv Voie CLK Output" OW Voitage lol =5 mA 45 V VOHC CLK Output HIGH Voltage loH =-800 pA 4.0 v loc Power Supply Current 145 mA CAPACITANCE (Ta = + 25C, Vcc = GND =0 V, Vin=+5 V or GND) PSymbol Description Test Conditions Min. | Max. | Units Cl Input Capacitance (Note 1) fo = 1 MHz 10 pF Notes: 1. This specification is provided for reference only. See Sectian 6 for Thermal Characteristics Information. 3-267 o N N o e82284 SWITCHING CHARACTERISTICS over operating range unless otherwise specified 8 MHz 10 MHz Parameter No. Description Test Conditions Min. | Max. | Min. | Max. | Units 1 EFl-to-CLK Delay At 1.5 V (Note 1) 30 30 ns 2 EFI LOW Time At 1.5 V (Notes 1 & 7) 25 25 ns 3 EFI HIGH Time At 1.5 V (Notes 1 & 7) 30 25 ns 4 CLK Period 62 500 50 500 ns 5 CLK LOW Time At 1.0 V (Notes 1, 2, & 8) 12 ns 6 CLK HIGH Time At 3.6 V (Notes 1, 2, & gy 16 ns 7 CLK Rise Time 1.0 to 3.6 V (Nete [he 10 8 ns 8 CLK Fall Time e \ ie 10 8 ns 9 Status Setup Time 22 20 ns 10 Status Hold Time 1 1 ns 1 17 16 ns 12 (Note 1) 0 0 ns 13 (Notes 1 & 3) 0 0 ns 14 (Note 1 & 3) 30 30 ns 15 RES Setup Time (Notes 1 & 3) 20 20 ns 16 RES Hold Time (Notes 1 & 3) 10 10 ns 17 READY inactive Delay At 0.8 V (Note 4) 5 5 ns 18 READY Active Delay At 0.8 V (Note 4) 0 24 0 24 ns 19 PCLK Delay (Note 5) 0 45 0 35 ns 20 RESET Delay (Note 5) 5 34 5 27 ns 21 PCLK LOW Time (Notes 5 & 6) t4-20 t4- 20 ns 22 PCLK HIGH Time (Notes 5 & 6) tg-20 t4- 20 ns Notes: 1. CLK loading: C_ = 150 pF. 2. With the internal oscillator crystal using recommmended crystal and capacitive loading, or with the EFI input meeting specifications tz and tg, use a paraliel-resonant, fundamental mode crystal. The recommended crystal loading for CLK frequencies of 8-16 MHz are 25 pF from pin X1 to ground, and 15 pF from pin Xp 10 ground. These recommended values are +5 pF and include ail stray capacitance. Decouple Voc and GND as close to the 82284 as possible. 3. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at specific CLK edge. 4. loading: lo. = 7 mA, CL = #50 pF. in system application, use 910 ohm +5% pull-up resistor to meet 80286 timing requiraments. For systems which operate faster than 10 MHz, care should be taken to minimize capacitive loading on READY. The user must ensure the RC time constant allows the pin to be pulled HIGH in two clock cycles. 5. PCLK and RESET ioading: C_= 75 pF. PCLK also has 750 ohm pull-up resistor. 6. tq refers to any allowable CLK period. 7. When driving the 82284 with EFI, provide minimum EFI HIGH and LOW times as follows: CLK Output Frequency 16-MHz CLK 20-MHz CLK* Min. Required EFI HIGH Time 30 ns 25 ns Min. Required EFl LOW Time 25 ns 25 ns *At CLK frequencies above 16 MHz, CLK output HIGH and LOW times are guaranteed only when using a crystal with recommended capacitive joading per Table 1, not when driving component from EFI. All features of the 82284 remain functional whether EF] or a crystal is used to drive the 82264. , 8, When using a crystal (with recommended loading capacitance per Table 1) appropriate for the speed of the 80286, CLK output HIGH and LOW times are guaranteed to meet 80286 requirements. 3-268SWITCHING TEST CIRCUITS o N N oe > Voc Voc 7500 910Q DEVICE DEVICE UNDER er TEST T 75 pF T 150 pF ~ ro904260 7004270 A. PCLK Output B. READY Output DEVICE DEVICE UNDER UNDER TEST | TEST T 150 pF T 75 pF TC004280 TC004290 Cc. CLK Outputs D. RESET Output 3-26982284 SWITCHING TEST WAVEFORMS 24V 15V oasv 1 1.5V WF024530 A. EFI Drive and Measurement Points 3.0V 26V 0.45 V 0.8V WF024540 B. RES Drive and Measurement Points 36V 3.6V 1.0V 1.0V WF024550 C. CLK Output Measurement Points 82284 cK / x 3.6V .6V OUTPUT 10V 1.0V 'seTuP tHoLD 24V DEVICE = 20V 4 INPUT ooy (EXCEPT 0.8 EFI& RES) 0.45V j DELAY > = 2.0V 0.8 V WF024560 D. AC Setup, Hold and Delay Time Measurement - General 3-270SWITCHING WAVEFORMS WF024570 Note: The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown. CLK as a Function of EFI 12, uw f f \ ff \ Sf \ Sf \_/ Gre fo) @ 2 hee - | tia DEPENOS ONY PREVIOUS ft RESET STATE OF A RES a NOTE 2 FeV \ T WF024580 Notes: 1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown. 2. Tie 910 ohm +5% pull-up resistor to the READY output. This LOW-to-HIGH transition depends on the state of ARDY, ARDYEN, SADY, and SRDYEN. RESET and READY Timing as a Function of RES with S1 and SO HIGH on IF THIS 15 Pox Finst A BUS CYCLE omy areven ARO aPOER REXDY WF024590 Notes: 1. This is an asynchronous input. The setup and hold times shown are required to quarantee the response shown. 2. Tia 910 ohm +5% pull-up resistor to the READY output. READY and PCLK Timing with RES HIGH 3-271 ao 1S N o@ a