TJA1043T,112 - NXP Semiconductors

1. General description

The TJA1043 is a high-speed CAN transceiver that provides an interface between a

Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.

The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in the

automotive industry, providing differential transmit and receive capability to (a

microcontroller with) a CAN protocol controller.

The TJA1043 belongs to the third generation of high-speed CAN transceivers from NXP

Semiconductors, offering significant improvements over first- and second-generation

devices such as the TJA1041A. It offers improved ElectroMagnetic Comp atibility (EMC)

and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and

passive behavior when the supply voltage is turned off. Advanced features include:

•Low-power management controls the power supply throughout the node while

supporting local and remote wake-up with wake-up source recognition

•Several protection and diagnostic functions including bus line short-circuit detectio n

and battery connection detection

•Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V

These features make the TJA1043 the ideal choice for high speed CAN networks

containing nodes that need to be available all times, even when the internal VIO and VCC

supplies are switched off.

2. Features and benefits

2.1 General

Fully ISO 11898-2 and ISO 11898-5 compliant

Suitable for 12 V and 24 V systems

Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)

VIO input allows for direct interfacing with 3 V and 5 V micr oc on tr olle rs

SPLIT voltage output for stabilizing the recessive bus level

Listen-only mode for node diagnosis and failure containment

2.2 Low-power management

Very low current Standby and Sleep modes, with local and remote wake-up

Capability to power down the entire node while supporting local, remote and host

wake-up

Wake-up source recognition

Transceiver disengages from the bus (zero load) when VBAT absent

TJA1043

High-speed CAN transceiver

Rev. 2 — 20 June 2011 Product data sheet

Product data sheet Rev. 2 — 20 June 2011 2 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

Functional behavior predictable under all supply conditions

2.3 Protection and diagnosis (detection and signalling)

High ESD handling capability on the bus pins

Bus pins and VBAT protected against transients in automotive environments

Transmit Data (TXD) dominant time-out function with diagnosis

TXD-to-RXD short-circuit ha ndler with diagnosis

Thermal protection with diagnosis

Undervoltage detectio n an d reco ve ry on pin s VCC, VIO and VBAT

Bus line short-circ uit dia gno sis

Bus dominant clamping diagnosis

Cold start diagnosis (first battery connection)

3. Quick reference data

4. Ordering information

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 4.5 - 5.5 V

Vuvd(VCC) undervoltage detection voltage on pin

VCC

33.54.3V

ICC supply current Normal mode; bus dominant 30 48 6 5 mA

Normal or Listen-only mode; bus

recessive 369mA

Standby or Sleep mode 0 0.75 2 A

VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANH and CANL 8- +8kV

VCANH voltage on pin CANH no time limit; DC limiting value 58 - +58 V

VCANL voltage on pin CANL no time limit; DC limiting value 58 - +58 V

Tvj virtual junction temperature 40 - +150 C

Table 2. Ordering i nformation

Type number Package

Name Description Version

TJA1043T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 2 — 20 June 2011 3 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

5. Block diagram

Fig 1. Block diagram

TEMPERATURE

PROTECTION

TIME-OUT

MODE

CONTROL

WAKE-UP

CONTROL

ERROR

DETECTION

MUX

DRIVER

TXD 1

RXD 4

SLOPE

CONTROL

DRIVER

CANH

CANL

GND

TJA1043

SPLIT SPLIT

WAKE-UP

FILTER

015aaa061

BAT

STB_N

ERR_N 8

BAT

WAKE

BAT

INH

Product data sheet Rev. 2 — 20 June 2011 4 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

The TJA1043 is a stand-alone high-speed CA N transceiver with a number of operating

modes, fail-safe features and diagnostic features that offer enhanced system reliability

and advanced power management. The transceiver combines the functionality of the

TJA1041A with improved EMC and ESD capability and quiescent current performance.

Improved slope control and high DC handling capability on the bus pins provide additional

application flexibility.

Fig 2. Pin configuration

TJA1043

TXD STB_N

GND CANH

CANL

RXD SPLIT

BAT

EN WAKE

INH ERR_N

015aaa062

7 8

Table 3. Pin description

Symbol Pin Description

TXD 1 transmit data input

GND 2 ground supply

VCC 3 transceiver supply voltage

RXD 4 receive data output; reads ou t data from the bus lines

VIO 5 supply voltage for I/O level adaptor

EN 6 enable control input

INH 7 inhibit output for switching external voltage regulators

ERR_N 8 error and power-on indication output (active LOW)

WAKE 9 local wake-up input

VBAT 10 battery supply voltage

SPLIT 11 common-mode stabilization output

CANL 12 LOW-level CAN bus line

CANH 13 HIGH-level CAN bus line

STB_N 14 standby control input (active LOW)

Product data sheet Rev. 2 — 20 June 2011 5 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

7.1 Operating modes

The TJA1043 supports five operating modes. Control pins STB_N and EN are used to

select the operating mode. Switching between modes allows access to a number of

diagnostics flag s via pin ERR_N. Table 4 describes how to switch between modes.

Figure 3 illustrates the mode transitions when VCC, VIO and VBAT are valid.

[1] Setting the UVNOM flag will clear the WAKE flag.

[2] Setting the Wake flag will clear the UVNOM flag.

[3] A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag

[4] After the minimum hold time, in Go-to-Sleep mode, th(min), the transceiver will enter Sleep mode and pin

INH will be set floating.

Table 4. Operating mo de selection

Internal flags Control pins Operating mode Pin INH

UVNOM[1] UVBAT Wake[2] STB_N[3] EN

From Normal, Listen-only, Standby and Go-to-Sleep mode s

set X X X X S leep mode floating

cleared set X HIGH X S tandby mode HIGH

cleared X set LOW X S tandby mode HIGH

cleared X cleared LOW LOW Standby mode HIGH

cleared X cleared LOW HIGH Go-to-Sleep mode[4] HIGH[4]

cleared cleared X HIGH LOW Listen-only mode HIGH

cleared cleared X HIGH HIGH Normal mode HIGH

From Sleep mode

set X X X X S leep mode floating

cleared set X HIGH X S tandby mode HIGH

cleared X set LOW X S tandby mode HIGH

cleared X cleared LOW X Sleep mode floating

cleared cleared X HIGH LOW Listen-only mode HIGH

cleared cleared X HIGH HIGH Normal mode HIGH

Product data sheet Rev. 2 — 20 June 2011 6 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

7.1.1 Normal mode

In Normal mode, the transce iver can transmit and receive data via the bus lines CANH

and CANL (see Figure 1 for the block diagram). The differential receiver converts the

analog data on the bus lines into digital data which is output to pin RXD. The slope of the

output signals on the bus lines is controlled and optimized in a way that guarantees the

lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH is active, so

voltage regulators controlled by pin INH (see Figure 6) will be active too.

7.1.2 Listen-only mode

In Listen-only mode, the transceiver’s transmitter is disabled, effectively providing a

transceiver listen-only feature. The receiver will still convert the analog bus signal on

pins CANH and CANL into digital data, available for output on pin RXD. As in Normal

mode, the bus pins are biased at 0.5VCC and pin INH remains active.

Fig 3. Mode transitions when valid VCC, VIO and VBAT voltages are present

015aaa063

STANDBY

MODE

NORMAL

MODE

GO-TO-SLEEP

MODE

LEGEND:

= H, = L logical state of pin

SLEEP

MODE

LISTEN-

ONLY MODE

Wake flag cleared

and

t > t

h(min)

STB_N = H and EN = H

STB_N = H and EN = L

STB_N = L

and

Wake flag set

STB_N = L

and

(EN = L or Wake flag set)

STB_N = L and EN = H

and

Wake flag cleared

STB_N = H

and

EN = H

STB_N = H

and

EN = L

STB_N = L

and

(EN = L or Wake flag set) STB_N = L and EN = H

and

Wake flag cleared

STB_N = L

and

EN = H

STB_N = H

and

EN = H

STB_N = L

and

EN = L

STB_N = H

and

EN = L

STB_N = H

and

EN = H

STB_N = H

and

EN = L

Product data sheet Rev. 2 — 20 June 2011 7 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

7.1.3 Standby mode

Standby mode is the TJA1043’s first-level power saving mode, offering reduced current

consumption. In Standby mode, the transceiver is unable to transmit or receive dat a and

the low-power r eceiver is activated to monitor bus activity. The bus pins are biased at

ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will

also be active.

Pins RXD and ER R_N will reflect any active wake-up requests (provided that VIO and

VBAT are present).

7.1.4 Go-to-Sleep mode

Go-to-Sleep mode is the controlled route for enter ing Sleep mode. In Go-to-Sleep mode,

the transceiver behaves as in Standby mode, with the addition that a go-to-sleep

command is issued to the transceiver . The transceiver will remain in Go-to-Sleep mode for

the minimum hold time (th(min)) befo re en te ring Slee p mo de. The tra nsceiver wil l not e nter

Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set

before th(min) has elapsed.

7.1.5 Sleep mode

Sleep mode is the TJA1043’s second-level po wer saving mode. Sleep mode is entered

via Go-to-Sleep mode, and al so when the undervoltage detection time on either VCC or

VIO elapses before the relevant voltage level has recovered. In Sleep mode, the

transceiver behaves as described for S tandby mod e, with the exception that pin INH is set

floating. Voltage regulators controlled by this pin will be switched off, and the current into

pin VBAT will be reduced to a minimum. Pins STB_N, EN and the W ake flag can be used to

wake up a node from Sleep mode (see Table 4).

7.2 Internal flags

The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and

system diagnosis support. Five of these flags can be polled by the controller via pin

ERR_N. Which flag is available on pin ERR_N at any time depends on the active

operating mode and on a number of other conditions. Table 5 describes how to access

these flags.

Table 5. Accessing internal flags via pin ERR_N

Internal

flag Flag is available on pin ERR_N[1] Flag is cleared

UVNOM no by setting the Pwon or Wake flags, by a

LOW-to-HIGH transition on STB_N or

when both VIO and VBAT have

recovered.

UVBAT no when VBAT has recovered

Pwon in Listen-only mode (coming from S t andby

mode, Go-to-Sleep mode, or Sleep mode) on entering Normal mode

Wake in Standby mode, Go-to-Sleep mode, and

Sleep mode (provided that VIO and VBAT

are present)

on entering Normal mode or by setting

the UVNOM fla g

Product data sheet Rev. 2 — 20 June 2011 8 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

[1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a

cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes.

[2] Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.

7.2.1 UVNOM flag

UVNOM is the VCC and VIO undervoltage d etection flag. The flag is set when the volt age on

pin VCC drop s below the VCC undervoltage detection volt age, Vuvd(VCC), for longer than the

undervoltage detection time, tdet(uv), or when th e vo ltage on pin VIO drops below Vuvd(VIO)

for longer than tdet(uv). When the UVNOM flag is set, the transce iver enters Sleep mode to

save power and to ensure the bus is not disturbed. In Sleep mode the volt age regulators

connected to pin INH are disab led , av oid ing any extra power consumption that might be

generated as a result of a short-circuit condition.

Any wake-up request, setting the Pwon flag or a LOW-to-H IGH transition on STB_N will

clear UVNOM and the timers, allowing the voltage regulator s to be reactivated (at least until

UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover fo r longer

than the undervoltage recovery time, trec(uv). The transceiver will then switch to the

operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).

7.2.2 UVBAT flag

UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on

pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter

Standby mode to save power and will disengage from the bus (zero load). UVBAT is

cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the

operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).

7.2.3 Pwon flag

Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers

after previously dropping below Vuvd(VBAT) (usually because the battery was

disconnected). Settin g the Pwon flag clears the UVNOM flag and timers. The Wake and

Wake-up source flags are set to ensure consistent system power-up under all supply

conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 5).

The flag is cleared when the transceiver enters Normal mode.

7.2.4 Wake flag

The Wake flag is set when the transceiver detects a local or remote wake-up request. A

local wake-up request is detected when the logic level on pin WAKE changes, and the

new level remains stable for at least twake. A remote wake-up request is triggered by two

bus dominan t states of at leas t twake(busdom), with the first dominant state followed by a

Wake-up

source in Normal mode (before the fourth

dominant-to-recessive edge on pin TXD[2])on leaving Normal mode

Bus failure in Normal mode (after the fourth

dominant-to-recessive edge on pin TXD[2])on re-entering Normal mode or by

setting the Pwon flag

Local failure in Listen-only mode (coming from Normal

mode) on entering Normal mode or when RXD

is dominant while TXD is recessive

(provided that all local failures are

resolved) or by setting the Pwon flag

Table 5. Accessing internal flags via pin ERR_N …continued

Internal

flag Flag is available on pin ERR_N[1] Flag is cleared

Product data sheet Rev. 2 — 20 June 2011 9 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

recessive state of at least twake(busrec) (provided the comp lete

dominant-recessive-dominant pattern is completed within tto(wake)bus). The Wake flag can

be set in Standby mode, Go -to-Sleep mode or Sleep mode. Setting the Wake flag clears

the UVNOM flag and timers. Once set, the Wake flag status is immediately available on

pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at

power-on and clear ed when the UVNOM flag is set or the transceiver enters Normal mode.

7.2.5 Wake-up source flag

Wake-up source reco gn itio n is pro vid e d via the Wake-up source flag, whic h is set wh en

the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source

flag can be polled via the ERR_N pin in Nor mal mode (see Table 5). This flag is also set at

power-on and cleared when the transceiver leaves Normal mode.

7.2.6 Bus failure flag

The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to

VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while

trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N

pin in Normal mode (see Table 5). This flag is cleared at power-on or when the transceiver

re-enters Normal mode.

7.2.7 Local failure flag

In Normal and Listen-only modes, the transceiver can distinguish four different local

failure events, any of which will cause the Local failure flag to be set. The four local failure

events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping

and an overtemperature event. The nature and detection of these local failures is

described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in

Listen-only mode (see Table 5). This flag is cleared at power-on, when entering Normal

mode or when RXD is dominant while TXD is recessive, provided that all local failures

have been resolved.

7.3 Local failures

The TJA1043 can detect fo ur different loca l failure conditions. Any of these failures will set

the Local failure flag, and in most cases the transmitter of the transceiver will be disabled.

7.3.1 TXD dominant clamping detection

A permanent LOW level on pin TXD (due to a hardware or software application failure )

would drive the CAN bus into a permanent domin ant state, blocking all network

communications. The TXD dom inant time-out function prevent s such a network lock-up by

disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant

time-out time tto(dom)TXD. The tto(dom)TXD timer defin es the minimum possible bit rate of

40 kbit/s. The transmitter remains disabled until the Local failure flag has been cleared.

7.3.2 T XD-to-RXD short-circuit detection

A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant

state once it had been driven dominant, because the low-side driver of RXD is typically

stronger than th e hig h- sid e dr ive r of the con tr olle r co nn e cte d to TXD. T XD-t o- RXD

short-circuit detection pr events such a network lock-up by disabling the trans m itte r. The

transmitter remains disabled until the Local failure flag has been cleared.

Product data sheet Rev. 2 — 20 June 2011 10 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

7.3.3 Bus dominant clamping detection

A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network

nodes could result in a dif ferential voltage on the bus high enough to represent a bus

dominant state. Because a node will not start transmission if the bus is dominant, the

normal bus failure detection will not detect this failure, but the bus dominant clamping

detection will. The Local failure flag is set if the dominant state on the bus persists for

longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped b us

is blocking network communications. Th ere is no need to disable th e transmitter . No te that

the Local failure flag does not retain a bus dominant clamping failure, and is released as

soon as the bus returns to rece ssive state.

7.3.4 Overtemperature detection

If the junction temperature becomes excessive, the transmitter will shut down in time to

protect the output drive rs from overheating wi thout compromi sing the maximum operating

temperature. The transmitter will remain disabled until the Local failure flag has been

cleared.

7.4 SPLIT pin

Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see

Figure 4 and Figure 6) can help to stabilize the recessive voltage level on the bus. This

will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with

poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a

DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is

floating.

7.5 VIO supply pin

Pin VIO should be connected to the m icrocontroller sup ply voltage (see Figure 6). This will

cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the

I/O levels of the microcontroller, facilitating direct interfacing without the need for glue

logic.

Fig 4. Stabilization circuit and application

GND

VCC

VSPLIT = 0.5VCC

in normal mode

and pwon/listen-only

mode;

otherwise floating

TJA1043

SPLIT

60 Ω

015aaa064

VSPLIT

CANH

CANL

Product data sheet Rev. 2 — 20 June 2011 11 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

7.6 WAKE pin

A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the

WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To

minimize current consumption, the internal bias voltage will follow the logic state on the

pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to

VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In

applications that don’t make use of the local wake-up facility, it is recommended that the

WAKE pin be connected to VBAT or GND to ensure optimal EMI performance.

Product data sheet Rev. 2 — 20 June 2011 12 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

8. Limiting values

[1] V erified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 p art 3 automotive transient test

pulses 1, 2a, 3a and 3b.

[2] IEC 61000-4-2 (150 pF, 330 ); direct coupling.

[3] ESD performance of pins CANH and CANL according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house.

The result is equal to or better than 8 kV (unaided).

[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).

[5] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).

[6] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF); grade C3B.

[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =T

amb +PRth(vj-a), where Rth(vj-a) is a

fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient

temperature (Tamb).

9. Thermal characteristics

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VBAT battery supply voltage no time limit 0.3 +58 V

load dump - 58 V

Vxvoltage on pin x no time limit; DC value

on pins CANH, CANL and SPLIT 58 +58 V

on pins INH and WAKE 0.3 +58 V

on pins VCC, VIO, TXD, RXD, STB_N, EN,

ERR_N 0.3 +7 V

IWAKE current on pin WAKE DC value - 15 mA

Vtrt transient voltage on pins CANH, CANL, SPLIT and VBAT [1] 200 +200 V

VESD electrostatic discharge

voltage IEC 61000-4-2 [2]

at pins CANH and CANL [3] 8+8 kV

HBM [4]

at pins CANH and CANL 8+8 kV

at any other pin 4+4 kV

MM [5]

at any pin 300 +300 V

CDM [6]

at corner pins 750 +750 V

at any pin 500 +500 V

Tvj virtual junction temperature [7] 40 +150 C

Tstg storage temperature 55 +150 C

Table 7. Thermal characteristics

Value determined for free convection conditions on a JEDEC 2S2P board.

Symbol Parameter Conditions Typ Unit

Rth(vj-a) thermal resistance from virtual junction to ambient in free air 68 K/W

Product data sheet Rev. 2 — 20 June 2011 13 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

10. Static characteristics

Table 8. Static characteristics

VCC = 4.5 V to 5.5 V ; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R

L=60



; Tvj =





Cto+150



C; unless otherwise

specified; all voltages are defined with respect to ground; positive currents flow into the device [1].

Symbol Parameter Conditions Min Typ Max Unit

Supply pin VCC

VCC supply voltage 4.5 - 5.5 V

Vuvd(VCC) undervoltage detection

voltage on pin VCC VBAT > 4.5 V 3 3.5 4.3 V

ICC supply current Normal mode; VTXD = 0 V (dominant) 30 48 65 mA

Normal or Listen -o n ly mode;

VTXD =V

IO (recessive) 36 9mA

Standby or Sleep mode; VBAT > VCC 00.752A

I/O level adapter supply; pin VIO

VIO supply voltage on pin VIO 2.8 - 5.5 V

Vuvd(VIO) undervoltage detection

voltage on pin VIO

VBAT or VCC > 4.5 V 0.8 1.8 2.5 V

IIO supply current on pin VIO Normal mode; VTXD = 0 V (dominant) - 150 500 A

Normal or Listen -o n ly mode;

VTXD =V

IO (recessive) 01 4A

Standby or Sleep mode 0 1 4 A

Supply pin VBAT

VBAT battery supply voltage 4.5 - 40 V

Vuvd(VBAT) undervoltage detection

voltage on pin VBAT 33.54.3V

IBAT battery supply current Normal or Listen-only mode 15 40 70 A

St andby mode; VCC >4.5V

VINH =V

WAKE =V

BAT

51830A

Sleep mode; VINH =V

CC =V

IO =0V;

VWAKE =V

BAT

51830A

CAN transmit data input; pin TXD

VIH HIGH-level input voltage 0.7VIO -V

IO +0.3 V

VIL LOW-level input voltage 0.3 - +0.3VIO V

IIH HIGH-level input current VTXD =V

IO 50 +5A

IIL LOW-level input current Normal mode; VTXD = 0 V 300 200 30 A

Ciinput capacitance not tested - 5 10 pF

CAN receive data output; pin RXD

IOH HIGH-level output current VRXD =V

IO 0.4 V; VIO =V

CC 12 60mA

IOL LOW-level output current VRXD = 0.4 V; VTXD =V

IO;

bus dominant 06 14mA

Standby and enable co ntrol inputs; pins STB_N and EN

VIH HIGH-level input voltage 0.7VIO -V

IO +0.3 V

VIL LOW-level input voltage 0.3 - 0.3VIO V

IIH HIGH-level input current VSTB_N =V

EN =0.7V

IO 14 10A

Product data sheet Rev. 2 — 20 June 2011 14 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

IIL LOW-level input current VSTB_N =V

EN =0V 10 +1A

Error and power-on indi ca tion output; pin ERR_N

IOH HIGH-level output current VERR_N =V

IO 0.4 V; VIO =V

CC 50 20 4A

IOL LOW-level output current VERR_N = 0.4 V 0.1 0.5 2 mA

Local wake-up input; pin WAKE

IIH HIGH-level input current VWAKE =V

BAT 1.9 V 10 51A

IIL LOW-level input current VWAKE =V

BAT 3.1 V 1 5 10 A

Vth threshold voltage VSTB_N =0V V

BAT 3V

BAT 2.5 VBAT 2V

Inhibit output; pin INH

VHHIGH-level voltage drop IINH =0.18 mA 0 0.25 0.8 V

ILleakage current Sleep mode 20 +2A

Bus lines; pins CANH and CANL

VO(dom) dominant output voltage VTXD =0V; t<t

to(dom)TXD

pin CANH 2.75 3.5 4.5 V

pin CANL 0.5 1.5 2.25 V

Vdom(TX)sym transmitter dominant

voltage symmetry Vdom(TX)sym = VCC VCANH VCANL 400 - +400 mV

VO(dif)bus bus differential output

voltage VTXD =0V; V

CC = 4.75 V to 5.25 V;

45 <R

L<65; dominant 1.5 - 3.0 V

VTXD =V

IO; recessive; no load 50 - +50 mV

VO(rec) recessive output voltage Normal or Listen-on ly mode ;

VTXD =V

IO; no load 20.5V

CC 3V

Standby or Sleep mode; no load 0.1 0 +0.1 V

IO(sc) short-circuit output current VTXD = 0 V (dominant); VCC =5V

pin CANH; VCANH =0V 100 70 40 mA

pin CANL; VCANL = 40 V 40 70 100 mA

IO(rec) recessive output current 27 V < VCAN <32V 3- +3mA

Vth(RX)dif differential receiver

threshold voltage Vcm(CAN) =30 V to +30 V [2]

Normal or Listen -o n ly mode 0.5 0.7 0.9 V

Standby or Sleep mode 0.4 0.7 1.15 V

Vhys(RX)dif differential receiver

hysteresis voltage Normal or Listen-only mode

Vcm(CAN) =30 V to +30 V [2] 50 120 400 mV

ILI input leakage current VCC =0V; V

CANH =V

CANL = 5 V 100 170 250 A

VBAT =0V; V

CANH =V

CANL =5V 2- +2A

Riinput resistance 9 15 28 k

Riinput resistance deviation between VCANH and VCANL 30 +3%

Ri(dif) differential input resistance 19 30 52 k

Ci(cm) common-mode input

capacitance VTXD =V

CC [3] - - 20 pF

Ci(dif) differential input

capacitance VTXD =V

CC [3] - - 10 pF

Table 8. Static characteristics …continued

VCC = 4.5 V to 5.5 V ; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R

L=60



; Tvj =





Cto+150



C; unless otherwise

specified; all voltages are defined with respect to ground; positive currents flow into the device [1].

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 20 June 2011 15 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

[1] All parameters are guaranteed over the virtual junction te mperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage range.

[2] Vcm(CAN) is the common mode voltage of CANH and CANL.

[3] Not tested in production; guaranteed by design.

11. Dynamic characteristics

[1] All parameters are guaranteed over the virtual junction te mperature range by design. Factory testing uses correlated test conditions to

cover the specified temperature and power supply voltage range.

Common-mode stabilization output; pin SPLIT

VOoutput voltage Normal or Listen-only mode;

500 A<I

SPLIT < 500 A0.3VCC 0.5VCC 0.7VCC V

Normal or Listen-only mode

RL=1M

0.45VCC 0.5VCC 0.55VCC V

ILleakage current Standby or Sleep mode;

58 V < VSPLIT <+58V 30 +3A

Temperature de te ction

Tj(sd) shutdown junction

temperature [3] - 190 - C

Table 8. Static characteristics …continued

VCC = 4.5 V to 5.5 V ; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R

L=60



; Tvj =





Cto+150



C; unless otherwise

specified; all voltages are defined with respect to ground; positive currents flow into the device [1].

Symbol Parameter Conditions Min Typ Max Unit

Table 9. Dynamic character istics;

VCC = 4.5 V to 5.5 V ; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R

L=60



; Tvj =





Cto+150



C; unless otherwise

specified; all voltages are defined with respect to ground; positive currents flow into the device[1].

Symbol Parameter Conditions Min Typ Max Unit

Timing character istics; Figure 5

td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 70 - ns

td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 90 - ns

td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-only mode - 60 - ns

td(busrec-RXD) delay time from bus recessive to

RXD Normal or Listen-only mode - 70 - ns

tPD(TXD-RXD) propagation delay from TXD to RXD VSTB_N = 0 V 40 - 240 ns

tdet(uv) undervoltage detection time 100 - 350 ms

trec(uv) undervoltage recovery time 1 - 5 ms

tto(dom)TXD TXD dominant time-out time VTXD =0V 0.3 0.6 1.5 ms

tto(dom)bus bus dominant time-out time VO(dif)(bus) > 0.9 V 0.3 0.6 1.5 ms

thhold time from issuing go-to-sleep command to

entering Sleep mode 20 35 50 s

twake(busdom) bus dominant wake-up time Standby or Sleep mode; VBAT =12V 0.5 1.75 5 s

twake(busrec) bus recessive wake-up time Standby or Sleep mode; VBAT =12V 0.5 1.75 5 s

tto(wake)bus bus wake-up time-out time 0.5 - 2 ms

twake wake-up time in response to a falling or rising edge

on pin WAKE; Standby or Sleep

mode

52550s

Product data sheet Rev. 2 — 20 June 2011 16 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

Fig 5. CAN transceiver timing diagram

CANH

CANL

td(TXD-busdom)

TXD

VO(dif)(bus)

RXD

HIGH

LOW

dominant

recessive

0.9 V

0.5 V

0.3VIO

0.7VIO

td(busdom-RXD)

td(TXD-busrec)

td(busrec-RXD)

tPD(TXD-RXD)

tPD(TXD-RXD) 015aaa025

Product data sheet Rev. 2 — 20 June 2011 17 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

12. Application information

Fig 6. Typical app lication with 3 V microcontroller

SPLIT

CAN bus wires

TJA1043 MICRO-

CONTROLLER

WAKE

VIO

INH

VBAT VCC

5710 3 VCC

Port x, y, z

RXD

TXD

STB_N

GND

CANLCANH 11 1213

015aaa060

TXD

RXD

ERR_N

5 V

BAT

3 V

Product data sheet Rev. 2 — 20 June 2011 18 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

13. Test information

13.1 Quality information

This product has been qualified to the appropriate Automotive Electronics Council (AEC)

standard Q100 or Q101 and is suitable for use in automotive applications.

Fig 7. Hysteresis of the receiver

Fig 8. Test circuit fo r timing characteristics

mgs378

VRXD

HIGH

LOW

hysteresis

0.5 0.9 Vi(dif)(bus) (V)

10 μF

100 nF47 μF

100 p

TJA1043

WAKE

TXD

310

STB_N

VIO

GND

VCC VBAT

SPLIT

CANL

CANH

8ERR_N

7INH

015aaa163

15 pF

4RXD

5 V

+12 V

Product data sheet Rev. 2 — 20 June 2011 19 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

14. Package outline

Fig 9. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 2 — 20 June 2011 20 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate pre ca utions are taken as

described in JESD625-A or equivalent standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded pa ckages,

packages with solder balls, and leadless packages are all reflow soldera ble.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 2 — 20 June 2011 21 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 10) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 10.

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 11. Lead-free process (from J-STD-020 C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 20 June 2011 22 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 10. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 2 — 20 June 2011 23 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

17. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TJA1043 v.2 20110620 Product data sheet - TJA1043 v.1

Modifications: •Section 1: text revised

•Section 3 “Quick reference data”: added along with ‘Quick reference data’ disclaimer in

Section 18.3

•Table 6: parameter conditions changed: Vx

•Table 7: format changed

•Table 8: parameter conditions changed: VO(dif)bus; text of Table note 3 revised

•Section 15 “ Handling information”: added

TJA1043 v.1 20100330 Product data sheet - -

Product data sheet Rev. 2 — 20 June 2011 24 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

suitable for use in medica l, military, aircraft, space or life support equipment,

nor in applications where failure or malf unction of an NXP Semiconductor s

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by cust omer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 20 June 2011 25 of 26

NXP Semiconductors TJA1043

High-speed CAN transceiver

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Quick reference data — The Quick reference dat a is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors TJA1043

High-speed CAN transceiver

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 June 2011

Document identifier: TJA1043

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Low-power management . . . . . . . . . . . . . . . . . 1

2.3 Protection and diagnosis (detection and

signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.2 Listen-only mode . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1.4 Go-to-Sleep mode . . . . . . . . . . . . . . . . . . . . . . 7

7.1.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2 Internal flags. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.1 UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.2 UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.3 Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.4 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2.5 Wake-up source flag. . . . . . . . . . . . . . . . . . . . . 9

7.2.6 Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.2.7 Local failure flag . . . . . . . . . . . . . . . . . . . . . . . . 9

7.3 Local failures . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.3.1 TXD dominant clamping detection . . . . . . . . . . 9

7.3.2 TXD-to-RXD short-circuit detection . . . . . . . . . 9

7.3.3 Bus dominant clamping detection. . . . . . . . . . 10

7.3.4 Overtemperature detection. . . . . . . . . . . . . . . 10

7.4 SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.5 VIO supply pin. . . . . . . . . . . . . . . . . . . . . . . . . 10

7.6 WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

9 Thermal characteristics . . . . . . . . . . . . . . . . . 12

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 13

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 15

12 Application information. . . . . . . . . . . . . . . . . . 17

13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 18

13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 18

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

15 Handling information. . . . . . . . . . . . . . . . . . . . 20

16 Soldering of SMD packages . . . . . . . . . . . . . . 20

16.1 Introduction to soldering. . . . . . . . . . . . . . . . . 20

16.2 Wave and reflow soldering. . . . . . . . . . . . . . . 20

16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 21

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 23

18 Legal information . . . . . . . . . . . . . . . . . . . . . . 24

18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 24

18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 24

18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25

19 Contact information . . . . . . . . . . . . . . . . . . . . 25

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26