AUIRLR3410
VDSS 100V
RDS(on) max. 105m
ID 17A
Features
Advanced Planar Technology
Low On-Resistance
Logic Level Gate Drive
Dynamic dV/dT Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve low on-resistance per silicon
area. This benefit combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient and
reliable device for use in Automotive and a wide variety of other
applications.
1 2015-10-29
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 17
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 12
IDM Pulsed Drain Current 60
PD @TC = 25°C Maximum Power Dissipation 79 W
Linear Derating Factor 0.53 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited) 150
mJ
IAR Avalanche Current 9.0 A
EAR Repetitive Avalanche Energy 7.9 mJ
dv/dt Pead Diode Recovery dv/dt 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.9
°C/W
RJA Junction-to-Ambient ( PCB Mount) ––– 50
RJA Junction-to-Ambient ––– 110
D-Pak
AUIRLR3410
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
AUIRLR3410 D-Pak Tube 75 AUIRLR3410
Tape and Reel Left 3000 AUIRLR3410TRL
G D S
Gate Drain Source
S
G
D
HEXFET® Power MOSFET
AUIRLR3410
2 2015-10-29
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
V
DD = 25V, starting TJ = 25°C, L = 3.1mH, RG = 25, IAS = 9.0A, VGS =10V. (See fig. 12)
I
SD 9.0A, di/dt 540A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 300µs; duty cycle 2%.
Uses IRL530N data and test conditions.
This is applied for LS of D-PAK is measured between lead and center of die contact.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994 .
R is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.122 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance
––– ––– 0.105
VGS = 10V, ID = 10A
––– ––– 0.125 VGS = 5.0V, ID = 10A
––– ––– 0.155 VGS = 4.0V, ID = 9.0A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Trans conductance 7.7 ––– ––– S VDS = 25V, ID = 9.0A
IDSS Drain-to-Source Leakage Current ––– ––– 25 µA VDS = 100 V, VGS = 0V
––– ––– 250 VDS = 80V,VGS = 0V,TJ =150°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg Total Gate Charge ––– ––– 34
nC
ID = 9.0A
Qgs Gate-to-Source Charge ––– ––– 4.8 VDS = 80V
Qgd Gate-to-Drain Charge ––– ––– 20 VGS = 5.0V
td(on) Turn-On Delay Time ––– 7.2 –––
ns
VDD = 50V
tr Rise Time ––– 53 ––– ID = 9.0A
td(off) Turn-Off Delay Time ––– 30 ––– RG = 6.0
tf Fall Time ––– 26 ––– VGS = 5.0V
LD Internal Drain Inductance ––– 4.5 –––
nH
Between lead,
6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
and center of die contact
Ciss Input Capacitance ––– 800 –––
pF
VGS = 0V
Coss Output Capacitance ––– 160 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 90 ––– ƒ = 1.0MHz
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 17
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 60 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 9.0A,VGS = 0V
trr Reverse Recovery Time ––– 140 210 ns TJ = 25°C ,IF = 9.0A
Qrr Reverse Recovery Charge ––– 740 1100 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
AUIRLR3410
3 2015-10-29
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance
Vs. Temperature
Fig. 1 Typical Output Characteristics
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 25°C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
0.1
1
10
100
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
A
20µs PULSE WIDTH
T = 175°C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
J
0.1
1
10
100
2345678910
T = 25°C
J
GS
V , Gate-to-Source Voltage (V)
D
I , Drain-to-Source Current (A)
V = 50V
20µs PULSE WIDTH
T = 175°C
J
A
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
V = 10V
GS
A
I = 15A
D
AUIRLR3410
4 2015-10-29
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
0
200
400
600
800
1000
1200
1400
110100
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
3
6
9
12
15
01020304050
Q , Total Gate Charge (nC)
G
V , Gate-to-Source Voltage (V)
GS
V = 80V
V = 50V
V = 20V
DS
DS
DS
A
FOR TEST CIRCUIT
SEE FIGURE 13
I = 9.0A
D
1
10
100
0.4 0.6 0.8 1.0 1.2 1.4
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
A
T = 175°C
J
1
10
100
1000
1 10 100 1000
V , Drain-to-Source Voltage (V)
DS
I , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 25°C
T = 175°C
Single Pulse
C
J
AUIRLR3410
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
5
10
15
20
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
AUIRLR3410
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Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
tp
V
(BR)DSS
I
AS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
0
50
100
150
200
250
300
350
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
A
Starting T , Junction Temperature (°C)
V = 25V
I
TOP 3.7A
6.4A
BOTTOM 9.0A
DD
D
AUIRLR3410
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Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
AUIRLR3410
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
YWWA
XX XX
Date Code
Y= Year
WW= Work Week
AUIRLR3410
Lot Code
Part Number
IR Logo
D-Pak (TO-252AA) Part Marking Information
AUIRLR3410
9 2015-10-29
D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
AUIRLR3410
10 2015-10-29
Qualification Information
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
D-Pak MSL1
ESD
Machine Model Class M4†
AEC-Q101-002
Human Body Model Class H1C†
AEC-Q101-001
Charged Device Model Class C5†
AEC-Q101-005
RoHS Compliant Yes
Moisture Sensitivity Level
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
10/29/2015 Updated datasheet with corporate template
Corrected ordering table on page 1.
3/17/2014 Added "Logic Level Gate Drive" bullet in the features section on page 1.
Updated data sheet with new IR corporate template.
† Highest passing voltage.
