HM4864-2,iM4864-3 HM4864P-2, HM4864P-3 65536- word < 1-bit Dynamic Random Access Memory The HM4864 is a 65,536-words by 1-bit, MOS random access memory circuit fabricated with HITACHIs double-poly N-channel silicon gate process for high performance and high functional density. The HM4864 uses a single transistor dynamic storage cell and dynamic control circuitry to achieve high speed and low power dissipation. Multiplexed address inputs permit the HM4864 to be packaged in a standard 16 pin DIP on 0.3 inch centers. This package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of +5V with +10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL, maximum input noise immunity to minimize false triggering of the inputs, on-chip address and data registers which eliminate the need for interface registers, and two chip select methods to allow the user to determine the appropriate speed/power characteristics of this memory system. The HM4864 also incorporates several flexible timing/operating modes. In addition to the usual read,write, and read-modify-write cycles, the HM4864 is capable of delayed write cycles, page-mode operation and RAS-only refresh. Proper control of the clock inputs (RAS, CAS, and WE) allows common 1!/O capability, two dimensional chip selection, and extended page boundaries (when operating in page mode). MFEATURES @ Recognized industry standard 16-pin configuration 150ns access time, 270ns cycle time (HM4864-2, HM4864P-2) 200ns access time, 335ns cycle time (HM4864-3, HM4864P-3) Single power supply of +5V+10% with a built-in Vgg generator Low Power; 330 mW active. 20 mW standby (max) The inputs TTL compatible, low capacitance, and protected against static charge Output data controlied by CAS and unlatched at end of cycle to allow two dimensional chip selection and extended page bound- ary @ Common 1/0 capability using early write operation Read-Modify-Write, RAS-only refresh, and Page-mode capability @ 128 refresh cycle @ HITACHI HM 4864-2, HM 4864-3 (DG-16A?! HM4864P -2, HM4864P -3 (DP -16) @PIN ARRANGEMENT (Top View) Ao-A> Address Inputs CAS Column Address Strobe Din Data In Dout Data Out RAS Row Address Strobe WE Read/Write Input Vee Power (+5V) Vss Ground Ao-As Refresh Address Input 199HM4864- 2, HM4864-3, HM4864P-2, HM4864P-3 MFUNCTIONAL BLOCK DIAGRAM WE R/W Cl WE OF Gert tt Memory & Memory Din Array =] | Arry M ABSOLUTE MAXIMUM RATINGS Row Dec Ke GAL Row Den ope: Voltage on any pin relative E] Memory |_| S| | Memory {&| tOVgg 20. eee eee -1.0 to +7V g] Arey [Ee] Acer fe = Kec Operating Temperature, Ta 2 4 & . io : elle : evs (Ambient) .............. 0 to +70C uf Memory |S] AJC] Memory |r Ae e S| Array 3|S] Array [3 Storage Temperature 3 = e| 3 Vaz Generato . + : 3 Row Dec Kxb GY Row Dec] ~1 (Ambient)........ ~65 to +150C (Cerdip 3 i re -56 to +125C (Plastic = z Memory | | 3} | Memory , 3 Array =| | Array Short-circuit Output Current . 50mA = So wos . al) Power Dissipation ......... IW Ao ae | Mi RECOMMENDED DC OPERATING CONDITIONS (Te=~0 to +70C) Parameter Symbol min typ max Unit Notes Supply Vol Vec 4.5 5.0 6.5 v 1 upPly Toltage Vss 0 0 0 Vv Input High Voltage Vin 2.4 _ .5 Vv 1 Input Low Voltage Vie =1.0 = 0.8 v | 1 MDC ELECTRICAL CHARACTERISTICS (Ta=0 to +70C, Vec=5V+10%, Vss=0V) Parameter | Symbol min max Unit Notes OPERATING CURRENT I _ 60 mA 24 Average Power Supply Operating Current (RAS, CAS Cycling; ! ac =min. ) ee . STANDBY CURRENT lees _ 35 mA 2 Power Supply Standby Current (RAS = Vi, Dout =High Impedance ) eee . REFRESH CURRENT Average Power Supply Current, Refresh Mode Tees _ 45 mA 2.4 (RAS Cycling, CAS = Via; tac= min.) PAGE MODE CURRENT Average Power Supply Current, Page-mode Operation Tees _ 45 mA 2,4 (RAS = Vii, CAS Cycling; tec= min.) INPUT LEAKAGE Input Leakage Current, any Input (V..=0 to +6.5V, all other pins not fu 10 10 BA under test =0V ) OUTPUT LEAKAGE _ Output Leakage Current (Dout is disabled, V.u.0 to +5.5V) foo 10 10 uA 3 OUTPUT LEVELS , 5 . Output High (Logic 1) Voltage (fa. =5mA)} wn 4 O Output Low (Logic 0) Voltage (fou: =4.2mA ) o NOTES 1. All voltages referenced to Vgg. 2. Icc depends on output loading condition when the device is selected. cc max. is specified at the output open condition. 3. Jz consists of leakage current only. 4. Current depends on cycle rate: maximum current is measured at the fastest cycle rate. MAC ELECTRICAL CHARACTERISTICS Parameter Symbol typ max Unit Notes Input Capacitance (Ao~A7, Din) Cant > 7 pF 1 Input Capacitance (RAS, CAS, WE) Ciaz _ 10 pF 1 Output Capacitance (Dout ) Cone _ 7 pF 1,2 NOTES 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = Vy, to disable Doyt 200 @ HITACHIHM4864-2, HM4864-3, HM4864P-2, HM4864P-3 MELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Ta=0 to +70C, Vec=5V+10%, Vss=0V) HM 4864-2 /P-2 HM 4864-3 /P-3 Parameter Symbol ~ . Unit Notes min max min max Random Read or Write Cycle Time tac 270 - 335 _ ns Read-Write Cycle Time tawe 270 _ 335 _ ns Page Mode Cycle Time tec 170 _ 225 _ ns Access Time from RAS trac _ 150 _ 200 ns 4,6 Access Time from CAS toac ~ 100 _- 135 ns 5,6 Output Buffer Turn-off Delay torr 0 40 0 50 ns 7 Transition Time (Rise and Fall ) tr 3 35 3 50 ns 3 RAS Precharge Time trp 100 _ 120 ns RAS Pulse Width tras 150 10000 200 10000 ns RAS Hold Time tas# 100 - 135 _ ns CAS Pulse Width tcas 100 7 135 _ ns CAS Hold Time tosn 150 _ 200 _ ns RAS to CAS Delay Time treo 20 50 25 65 ns 8 CAS to RAS Precharge Time tere 20 _ 20 _ ns Row Address Set-up Time taser 0 _ 0 _ ns Row Address Hold Time tran 20 _ 25 _ ns Column Address Set-up Time tasc 10 _ 10 _ ns Column Address Hold Time toan 45 _ 55 _ ns Column Address Hold Time referenced to RAS tar 95 _ 120 _- ns Read Command Set-up Time tres 0 _ 0 7 ns Read Command Hold Time tan 0 _ 0 _ ns Write Command Hold Time twon 45 _ 55 _ ns Write Command Hold Time referenced to RAS iwor 95 _ 120 _ ns Write Command Pulse Width twe 45 _ 55 _ ns Write Command to RAS Lead Time trwe 45 _ 55 _ ns Write Command to CAS Lead Time tows 45 _ 55 _ as Data-in Set-up Time tos 0 _ 0 _ ns 9 Data-in Hold Time tow 45 _ 55 _ ns 9 Data-in Hold Time referenced to RAS tour 95 | _ 120 _ ns CAS Precharge Time (for Page-mode Cycle Only) tep 60 _ 80 _ ns Refresh Period trer 7 2 _ 2 ms Write Command Set-up Time twes 20 - -20 _ ns 10 CAS to WE Delay town 60 - 80 _ ns 10 RAS to WE Delay trwp 110 - 145 - ns 10 RAS Precharge to CAS Hold Time trec 0 > 0 _ ns NOTES 1. AC measurements assume fy = Sns. trac (max)can be met. trcp (max) is specified as a 2. 8 cycles are required after power-on or prolonged reference point only; if frpop is greater than the periods (greater than 2ms) of RAS inactivity before specified trop (max) limit, then access time is proper device operation is achieved. Any 8 cycles controlled exclusively be tcac. _ which perform refresh are adequate for this purpose. 9. These parameters are reference to CAS leading edge in 3. Vizy (min) and Vy; (max) are reference levels for early write cycles and to WE leading edge in delayed measuring timing of input signals. Also, transition write or read-modify-write cycles. times are measured between Vy; and V7, . 10. twcs, tcwp and trwp are not restrictive operating 4. Assumes that trcps trcp (max). If trap is greater parameters. They are included in the data sheet as than the maximum recommended value shown in this electrical characteristics only: if twos 2twcs (min), table tp 4c exceeds the value shown. the cycle is an early write cycle and the data out pin 5. Assumes that tpcp 2 trcp (max). will remain open circuit (high impedance) throughout 6. Measured with a load circuit equivalent to 2TTL loads the entire cycle; if tcwp 2 tcwp (min) and trwp2 and 100 pF. trRwp (min) the cycle is a read/write and the data 7. topp (max) defines the time at which the output output will contain data read from the selected cell; if achieves the open circuit condition and is not refer- neither of the above sets of conditions is satisfied the enced to output voltage levels. condition of the data out (at access time) is indeter- 8. Operation with the trcp (max) limit insures that minate. @ HITACHI 201HM4864-2, HM4864-3, HM4864P- 2, HM4864P-3 MTIMING WAVEFORMS @READ CYCLE Column Address. Valid Data @WRITE CYCLE Valid Data Vow Dour Vor per: @READ-WRITE/READ-MODIFY- WRITE CYCLE tase Row Address _. va We WE , torr ars ac Dout m Vatid o OL tos) be~ tate Viw Da, Valid Data DX ta 202 @ HITACHIHM4864-2, -HM4864-3, HM4864P-2, HM4864P-3 @RAS-ONLY REFRESH CYCLE fap $-amnnnmnnn 8 A S- ., RAS \ tas = Address ML Row Address BX tearm =| fe-tarc oS ~~ NYS Dout Open @PAGE MODE READ CYCLE RAS Vix Vin TAS Vin Vin Vin Address Vir Va WE : E Vin. Vow Dout Vou @PAGE MODE WRITE CYCLE CAS Address Din Valid Data Valid Data @ HITACHI 203HM4864-2, HM4864-3, HM4864P-2, HM4864P-3 MTYPICAL CHARACTERISTICS 204 ACCESS TIME vs, SUPPLY VOLTAGE Ta=20C \ NX < Access Time tnac( Normalized) S Supply Voltage Vee (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE 50 Ta=20' tac Le | 270ns Les 3 | 500 20 Supply Current Icci (Operation) (mA) a 30 a a a 1,000 Supply Voltage Vec (V) SUPPLY CURRENT vs. CYCLE RATE 50 Yee =5.5V Ta=20C tap=100ns LZ 30 7 Supply Current fcci(Operation} (mA) o 1 2 a q Cycle Rate(1/tae} (MHz) HITACHI Access Time trac( Normalized) Supply Current fcey (Operationi (mAs Supply Current fccz (Stand By) (mA) u. ACCESS TIME vs. AMBIENT TEMPERATURE Veo =5.5 9 ~20 w 40 me Lart Ambient Temperature Ta (C) SUPPLY CURRENT vs. AMBIENT TEMPERATURE 5u T Veco =5.5V | tac S270 ns et 40 | (eee 330 30 ee heen ee 500 20 P= 1.000 10 -20 10 4g 70 190 Ambient Temperature Ta (C! SUPPLY CURRENT vs. SUPPLY VOLTAGE Ta=20C RAS, TAS = Ven 40 5 aay 3.5 bu Supply Voltage Vcc (V)Supply Current fecz (Stand By) (mA) Supply Current Iccs (Refresh Cycle? (mA! mA Supply Current frca Page Mude Cycle SUPPLY CURRENT vs. AMBIENT TEMPERATURE 4 Veco =5.5V RAS. TAS = Vin 3 | 2 1 a -2 10 40 70 1a) Ambient Temperature Ta ("C) SUPPLY CURRENT vs. AMBIENT TEMPERATURE 50 Vee =5.5V 40 30 SS" =270ns=4 2 ieee eee LL, 330 ~ 20 [= S00 +. 1.000 10 -20 10 40 70 ro09 Ambient Temperature Ta (C) SUPPLY CURRENT vs. SUPPLY VOLTAGE Sub Ta=20'C 40 30 tee =170ns J Lr Le 295 " 20 500 ao | 5 eo] 0 45 5.0 5.5 6.0 Supply Voltage Vee 'V) HM4864-2, HM4864-3, HM4864P-2, HM4864P-3 Supply Current cca (Refresh Cycle) (mA) Supply Voltage Iccs (Refresh Cycle) (mA) Supply Current Icc (Page Mode Cycle) (mA) @ HITACHI SUPPLY CURRENT vs. SUPPLY VOLTAGE 50 Ta=20C 40 tac =270ns 30 330 T 590 20 = 1.00 lo 4.0 45 5.0 5.5 6.0 Supply Voltage Vec (V) SUPPLY CURRENT vs. CYCLE RATE Vee = 5.54 Ta= 20C tre=100ns a0 2H 7 1 2 34 4 Cyele Rate (1/txc)(MHz) SUPPLY CURRENT vs. AMBIENT TEMPERATURE 5a, Vee =5.5V 40 30 tt eee a =170ns fe. oT Qu 2257] a] a) fp S00 10 -20 10 40 za 100 Ambient Temperature = Tu <'C 205HM4864-2, HM4864-3, HM4864P-2, HM4864P-3 206 Supply Current [cca (Page Mode Cycle} (mA) Ai,Din Input Level (V} Vi Clock Input Level ( a3 SUPPLY CURRENT vs. CYCLE RATE sa Vee HSV Tas zee eps Blins |_| a 1 7 : i Cycle Rate (1/tec} (MHz) INPUT LEVEL vs. AMBIENT TEMPERATURE 5 Veo Sau Vin Vin 1 5 - to 40 A) yun Ambient Temperature Ta (Cj CLOCK INPUT LEVEL vs. AMBIENT TEMPERATURE Vee S50V ab Vin] Vie -20 10 4 70 100 Ambient Temperature Ta ("C) @ HITACHI Ai,Din Input Level (V) Clock Input Level (V} INPUT LEVEL vs. SUPPLY VOLTAGE faz 20 | | a | | CLOCK 45 hate AS Supply Voltage Vee (Vi INPUT LEVEL vs. SUPPLY VOLTAGE fam + _4 [nner ToT | ra 15 m0 5 Supply Voltage Vee (V)RAS/CAS Cycle Long RAS/CAS Cycle RAS CAS, fee oma Note | Yee = 5.0, Ta = 20C a] fens BAPPLICATION INFORMATION @POWER ON An initial pause of 500 ys is required after power-up and a minimum of eight (8) initialization cycle,(any combination of cycles containing a RAS clock such as RAS-only refresh) must follow an initial pause. The Vee current (/ec) requirement of the HM4864 during power on is, however, dependent upon the input levels (RAS, CAS) and the rise time of Vc, as shown in Fig. 1. @READ CYCLE A read cycle begins with addresses stable and a negative going transition of RAS. The time delay between the stable address and the start of RAS-on is controlled by parameter tase . Following the time when RAS reaches its low level, the row address must be held stable long enough to be captured. This controlling parameter is taay. Following this interval, the address can be changed from row address to column address. When the column address is stable, CAS can be turned on. The leading edge of CAS is controlled by parameter tacp . The basic limit on the CAS leading edge is that CAS can not start until the column address is stable, and this is controlled by parameter tasc.. The column address must be held stable long enough to be captured. The controlling parameter is tog. Note that tgcp (max) is not an operating limit of the HM4864 though its specification is listed on the data sheets. If CAS becomes on later than tgcp (max), the access time from RAS will be increased by the time which tgcp exceeds tacp (max). Following the time when CAS reaches its low level, the data-out pin remains in a high impedance state until a valid data appears. This parameter is tcac -access time from CAS. The access time from RAStgacis the time from RAS-on to valid Dout. The minimum value of trac is derived as the sum of taco (max) and tcac- The selected output data is held valid internally until CAS becomes high, and then Dout pin becomes high impedance. This parameter is tore - @ HITACHI RAS Only Cycle HM4864- 2, HM4864-3, HM4864P-2, HM4864P-3 Page Mode Cycle RAS.CAS= Vs fee om RAS,CAS= Ve a Ww 20 30 ay 5 Time (us ti Ver rise Ume = [Nes vee iv TRAS.CAS=ss Tec (mA) RAS,CAS= re 0 too 200 300 40u 500 Time les? tt Vee rise time} =100u5 Fig.1 Icc VS. Vec during power up. 207HM4864-2, HM4864-3, HM4864P-2, HM4864P-3 @ WRITE CYCLE A write cycle is performed by bringing WE low before or during CAS-on. Two different write cycies can be defined as; Write cycleWrite data are available at the beginning of the CAS-on so that the write operation starts at the beginning, in this mode, Dout and WE signal times are not in any critical path for determining cycle time. Following the time when WE reaches its tow level, WE must be held stable long enough to be captured. This WE-on pulse deration is called twp. The time required to capture write data in a latch is called tox. This cycle is called an early write. Read Write cycleThis cycle starts as a read cycle, but as soon as the device specification is met, a write cycle is initiated. WE and Din are delayed until after Dout. This cycle is called a delayed write. A Read-modify-write cycle is a variation of this operation. In this mode, Din and WE become critical path signals for determining cycle time. @ CLOCK-OFF TIMING RAS and CAS must stay on for Dout stabilized to valid data. In the case of CAS, this is controlled by parameter tcgs (min). In the case of RAS, this is controlled by parameter teas (min). Following the end of RAS, CAS must stay off long enough to precharge internal circuits. The only Parameter of concern is tap. Normally CAS is not required to be off for minimum time of tcrp. However, in a page mode memory operation, there is a tcp (min) specification to control the CAS-off time. @ DATA OUTPUT Dout is three-state TTL compatible with a fan-out of two standard TTL loads. When CAS is high, Dout is in a high impedance state, When CAS is low, valid data appears after tcac at a read cycle, and Dout is not valid as an early-write cycle, 208 @ REFRESH Refresh of the HM4864 is accomplished by per- forming a memory cycle at each of the 128 row addresses within each two millisecond time interval. AO to A6 are refresh address pin compatible with standard 16K RAIM (HM4716A, HM4816A). During refresh, either Vj, or Viy is permitted for A7. Any cycle in which RAS signal occurs refreshes the entire selected row. RAS-only refresh resuits in substantial reduction in operating power. This re- duction in power is reflected in the /cc3 specifica- tion. @ PAGE MODE Page mode operation allows faster successive memo- ry operations at multiple column locations of the same row address with increased speed. This is done by strobing the row address into the chip and maintaining RAS at a logic low throughout all successive CAS memory cycles in which the row address is latched. As the time normally required for strobing a new row address is eliminated, access and cycle times can be descreaded and the operating power is reduced, These are specifications. @ HITACHI