FN957 Rev.10.00 Page 1 of 24
Jul 11, 2005
FN957
Rev.10.00
Jul 11, 2005
CA3140, CA3140A
4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
DATASHEET
The CA3140A and CA3140 are integrated circuit operational
amplifiers that combine the advantages of high voltage
PMOS transistors with high voltage bipolar transistors on a
single monolithic chip.
The CA3140A and CA3140 BiMOS operational amplifiers
feature gate protected MOSFET (PMOS) transistors in the
input circuit to provide very high input impedance, very low
input current, and high speed performance. The CA3140A
and CA3140 operate at supply voltage from 4V to 36V
(either single or dual supply). These operational amplifiers
are internally phase compensated to achieve stable
operation in unity gain follower operation, and additionally,
have access terminal for a supplementary external capacitor
if additional frequency roll-off is desired. Terminals are also
provided for use in applications requiring input offset voltage
nulling. The use of PMOS field effect transistors in the input
stage results in common mode input voltage capability down
to 0.5V below the negative supply terminal, an important
attribute for single supply applications. The output stage
uses bipolar transistors and includes built-in protection
against damage from load terminal short circuiting to either
supply rail or to ground.
The CA3140A and CA3140 are intended for operation at
supply voltages up to 36V (18V).
Features
• MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5T (Typ)
- Very Low Input Current (Il) -10pA (Typ) at 15V
- Wide Common Mode Input Voltage Range (VlCR) - Can be
Swung 0.5V Below Negative Supply Voltage Rail
- Output Swing Complements Input Common Mode
Range
• Directly Replaces Industry Type 741 in Most Applications
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers in
Automobile and Portable Instrumentation
• Sample and Hold Amplifiers
• Long Duration Timers/Multivibrators
(seconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectors
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low
Supply Voltage Systems
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
• Power Supplies
• Portable Instruments
• Intrusion Alarm Systems
Pinout
CA3140 (PDIP, SOIC)
TOP VIEW
INV. INPUT
NON-INV.
V-
1
2
3
4
8
7
6
5
STROBE
V+
OUTPUT
OFFSET
NULL
OFFSET
NULL
INPUT
-
+
CA3140, CA3140A
FN957 Rev.10.00 Page 2 of 24
Jul 11, 2005
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
CA3140AE -55 to 125 8 Ld PDIP E8.3
CA3140AEZ*
(See Note)
-55 to 125 8 Ld PDIP
(Pb-free)
E8.3
CA3140AM
(3140A)
-55 to 125 8 Ld SOIC M8.15
CA3140AM96
(3140A)
-55 to 125 8 Ld SOIC Tape and Reel
CA3140AMZ
(3140A) (See Note)
-55 to 125 8 Ld SOIC
(Pb-free)
M8.15
CA3140AMZ96
(3140A) (See Note)
-55 to 125 8 Ld SOIC Tape and Reel
(Pb-free)
CA3140E -55 to 125 8 Ld PDIP E8.3
CA3140EZ*
(See Note)
-55 to 125 8 Ld PDIP
(Pb-free)
E8.3
CA3140M
(3140)
-55 to 125 8 Ld SOIC M8.15
CA3140M96
(3140)
-55 to 125 8 Ld SOIC Tape and Reel
CA3140MZ
(3140) (See Note)
-55 to 125 8 Ld SOIC
(Pb-free)
M8.15
CA3140MZ96
(3140) (See Note)
-55 to 125 8 Ld SOIC Tape and Reel
(Pb-free)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
CA3140, CA3140A
FN957 Rev.10.00 Page 3 of 24
Jul 11, 2005
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V++8V) To (V- -0.5V)
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W)
PDIP Package* . . . . . . . . . . . . . . . . . . 115 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications VSUPPLY = 15V, TA = 25oC
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA3140 CA3140A
Input Offset Voltage Adjustment Resistor Typical Value of Resistor
Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
4.7 18 k
Input Resistance RI1.5 1.5 T
Input Capacitance CI44pF
Output Resistance RO60 60
Equivalent Wideband Input Noise Voltage
(See Figure 27)
eNBW = 140kHz, RS = 1M48 48 V
Equivalent Input Noise Voltage (See Figure 35) eNRS = 100f = 1kHz 40 40 nV/Hz
f = 10kHz 12 12 nV/Hz
Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA
IOM-Sink1818mA
Gain-Bandwidth Product, (See Figures 6, 30) fT4.5 4.5 MHz
Slew Rate, (See Figure 31) SR 9 9 V/s
Sink Current From Terminal 8 To Terminal 4 to
Swing Output Low
220 220 A
Transient Response (See Figure 28) trRL = 2k
CL = 100pF
Rise Time 0.08 0.08 s
OS Overshoot 10 10 %
Settling Time at 10VP-P, (See Figure 5) tSRL = 2k
CL = 100pF
Voltage Follower
To 1mV 4.5 4.5 s
To 10mV 1.4 1.4 s
Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL
CA3140 CA3140A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage |VIO|- 5 15- 2 5mV
Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA
Input Current II- 10 50 - 10 40 pA
CA3140, CA3140A
FN957 Rev.10.00 Page 4 of 24
Jul 11, 2005
Large Signal Voltage Gain (Note 3)
(See Figures 6, 29)
AOL 20 100 - 20 100 - kV/V
86 100 - 86 100 - dB
Common Mode Rejection Ratio
(See Figure 34)
CMRR - 32 320 - 32 320 V/V
70 90 - 70 90 - dB
Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V
Power-Supply Rejection Ratio,
VIO/VS (See Figure 36)
PSRR - 100 150 - 100 150 V/V
76 80 - 76 80 - dB
Max Output Voltage (Note 4)
(See Figures 2, 8)
VOM+ +12 13 - +12 13 - V
VOM- -14 -14.4 - -14 -14.4 - V
Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA
Device Dissipation PD- 120 180 - 120 180 mW
Input Offset Voltage Temperature Drift VIO/T- 8 - - 6 -V/oC
NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2k.
4. At RL = 2k.
Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL
CA3140 CA3140A
UNITSMIN TYP MAX MIN TYP MAX
Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3140 CA3140A
Input Offset Voltage |VIO|5 2mV
Input Offset Current |IIO|0.1 0.1pA
Input Current II22pA
Input Resistance RI11T
Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V
100 100 dB
Common Mode Rejection Ratio CMRR 32 32 V/V
90 90 dB
Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR
VIO/VS
100 100 V/V
80 80 dB
Maximum Output Voltage (See Figures 2, 8) VOM+3 3 V
VOM- 0.13 0.13 V
Maximum Output Current: Source IOM+10 10mA
Sink IOM-1 1mA
Slew Rate (See Figure 31) SR 7 7 V/s
Gain-Bandwidth Product (See Figure 30) fT3.7 3.7 MHz
Supply Current (See Figure 32) I+ 1.6 1.6 mA
Device Dissipation PD88mW
CA3140, CA3140A
FN957 Rev.10.00 Page 5 of 24
Jul 11, 2005
Block Diagram
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 A
Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC (Continued)
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3140 CA3140A
A 10 A
10,000
C1
12pF
5
A 1
1 8
4
6
7
2
3
OFFSET
STROBE
NULL
OUTPUT
INPUT
+
-
200A200A1.6mA 2A2mA
2mA 4mA
V+
V-
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
CA3140, CA3140A
FN957 Rev.10.00 Page 6 of 24
Jul 11, 2005
Schematic Diagram
Application Information
Circuit Description
As shown in the block diagram, the input terminals may be
operated down to 0.5V below the negative supply rail. Two
class A amplifier stages provide the voltage gain, and a unique
class AB amplifier stage provides the current gain necessary to
drive low-impedance loads.
A biasing circuit provides control of cascoded constant current
flow circuits in the first and second stages. The CA3140 includes
an on chip phase compensating capacitor that is sufficient for
the unity gain voltage follower configuration.
Input Stage
The schematic diagram consists of a differential input stage using
PMOS field-effect transistors (Q9, Q10) working into a mirror pair
of bipolar transistors (Q11, Q12) functioning as load resistors
together with resistors R2 through R5. The mirror pair transistors
also function as a differential-to-single-ended converter to provide
base current drive to the second stage bipolar transistor (Q13).
Offset nulling, when desired, can be effected with a 10k
potentiometer connected across Terminals 1 and 5 and with its
slider arm connected to Terminal 4. Cascode-connected bipolar
transistors Q2, Q5 are the constant current source for the input
stage. The base biasing circuit for the constant current source is
described subsequently. The small diodes D3, D4, D5 provide
gate oxide protection against high voltage transients, e.g., static
electricity.
Second Stage
Most of the voltage gain in the CA3140 is provided by the
second amplifier stage, consisting of bipolar transistor Q13 and
its cascode connected load resistance provided by bipolar
transistors Q3, Q4. On-chip phase compensation, sufficient for
a majority of the applications is provided by C1. Additional
Miller-Effect compensation (roll off) can be accomplished,
when desired, by simply connecting a small capacitor between
Terminals 1 and 8. Terminal 8 is also used to strobe the output
R5
500
R4
500
Q11 Q12
R2
500
R3
500
Q10
Q9
D5
D4
D3
5 1 8
STROBEOFFSET NULL
3
2
NON-INVERTING
INPUT
INVERTING
INPUT
+
-
C1
12pF
Q13
Q15 Q16
Q21
Q20
D8
Q19
Q18
Q17
R11
20
R9
50
R8
1K
R12
12K
R14
20K
R13
5K
D7
R10
1K
OUTPUT
D6
4
V-
V+
6
7
DYNAMIC CURRENT SINKOUTPUT STAGESECOND STAGEINPUT STAGEBIAS CIRCUIT
D2
Q8
Q4
Q3
Q5
Q2
Q6
Q7
D1
Q1
R1
8K
Q14
R7
30
R6
50
NOTE: All resistance values are in ohms.
CA3140, CA3140A
FN957 Rev.10.00 Page 7 of 24
Jul 11, 2005
stage into quiescence. When terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output Terminal 6 swings low, i.e., approximately to Terminal 4
potential.
Output Stage
The CA3140 Series circuits employ a broad band output stage
that can sink loads to the negative supply to complement the
capability of the PMOS input stage when operating near the
negative rail. Quiescent current in the emitter-follower cascade
circuit (Q17, Q18) is established by transistors (Q14, Q15) whose
base currents are “mirrored” to current flowing through diode D2 in
the bias circuit section. When the CA3140 is operating such that
output Terminal 6 is sourcing current, transistor Q18 functions as
an emitter-follower to source current from the V+ bus (Terminal 7),
via D7, R9, and R11. Under these conditions, the collector
potential of Q13 is sufficiently high to permit the necessary flow of
base current to emitter follower Q17 which, in turn, drives Q18.
When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q16 is the current sinking
element. Transistor Q16 is mirror connected to D6, R7, with
current fed by way of Q21, R12, and Q20. Transistor Q20, in turn,
is biased by current flow through R13, zener D8, and R14. The
dynamic current sink is controlled by voltage level sensing. For
purposes of explanation, it is assumed that output Terminal 6 is
quiescently established at the potential midpoint between the V+
and V- supply rails. When output current sinking mode operation
is required, the collector potential of transistor Q13 is driven below
its quiescent level, thereby causing Q17, Q18 to decrease the
output voltage at Terminal 6. Thus, the gate terminal of PMOS
transistor Q21 is displaced toward the V- bus, thereby reducing
the channel resistance of Q21. As a consequence, there is an
incremental increase in current flow through Q20, R12, Q21, D6,
R7, and the base of Q16. As a result, Q16 sinks current from
Terminal 6 in direct response to the incremental change in output
voltage caused by Q18. This sink current flows regardless of load;
any excess current is internally supplied by the emitter-follower
Q18. Short circuit protection of the output circuit is provided by
Q19, which is driven into conduction by the high voltage drop
developed across R11 under output short circuit conditions. Under
these conditions, the collector of Q19 diverts current from Q4 so
as to reduce the base current drive from Q17, thereby limiting
current flow in Q18 to the short circuited load terminal.
Bias Circuit
Quiescent current in all stages (except the dynamic current sink)
of the CA3140 is dependent upon bias current flow in R1. The
function of the bias circuit is to establish and maintain constant
current flow through D1, Q6, Q8 and D2. D1 is a diode connected
transistor mirror connected in parallel with the base emitter
junctions of Q1, Q2, and Q3. D1 may be considered as a current
sampling diode that senses the emitter current of Q6 and
automatically adjusts the base current of Q6 (via Q1) to maintain a
constant current through Q6, Q8, D2. The base currents in Q2, Q3
are also determined by constant current flow D1. Furthermore,
current in diode connected transistor Q2 establishes the currents
in transistors Q14 and Q15.
Typical Applications
Wide dynamic range of input and output characteristics with the
most desirable high input impedance characteristics is achieved
in the CA3140 by the use of an unique design based upon the
PMOS Bipolar process. Input common mode voltage range and
output swing capabilities are complementary, allowing operation
with the single supply down to 4V.
The wide dynamic range of these parameters also means that
this device is suitable for many single supply applications, such
as, for example, where one input is driven below the potential
of Terminal 4 and the phase sense of the output signal must be
maintained – a most important consideration in comparator
applications.
CA3140, CA3140A
FN957 Rev.10.00 Page 8 of 24
Jul 11, 2005
Output Circuit Considerations
Excellent interfacing with TTL circuitry is easily achieved with a
single 6.2V zener diode connected to Terminal 8 as shown in
Figure 1. This connection assures that the maximum output
signal swing will not go more positive than the zener voltage
minus two base-to-emitter voltage drops within the CA3140.
These voltages are independent of the operating supply
voltage.
Figure 2 shows output current sinking capabilities of the
CA3140 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
level shifting circuitry usually associated with the 741 series of
operational amplifiers.
Figure 4 shows some typical configurations. Note that a series
resistor, RL, is used in both cases to limit the drive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.
Offset Voltage Nulling
The input offset voltage can be nulled by connecting a 10k
potentiometer between Terminals 1 and 5 and returning its
wiper arm to terminal 4, see Figure 3A. This technique,
however, gives more adjustment range than required and
therefore, a considerable portion of the potentiometer rotation
is not fully utilized. Typical values of series resistors (R) that
may be placed at either end of the potentiometer, see Figure
3B, to optimize its utilization range are given in the Electrical
Specifications table.
An alternate system is shown in Figure 3C. This circuit uses
only one additional resistor of approximately the value shown
in the table. For potentiometers, in which the resistance does
not drop to 0 at either end of rotation, a value of resistance
10% lower than the values shown in the table should be used.
Low Voltage Operation
Operation at total supply voltages as low as 4V is possible with
the CA3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these lower
voltages.
The low voltage limitation occurs when the upper extreme of the
input common mode voltage range extends down to the voltage
at Terminal 4. This limit is reached at a total supply voltage just
below 4V. The output voltage range also begins to extend down to
the negative supply rail, but is slightly higher than that of the input.
Figure 8 shows these characteristics and shows that with 2V dual
supplies, the lower extreme of the input common mode voltage
range is below ground potential.
3
2
4
CA3140
8
6
7
V+
5V TO 36V
6.2V
5V
LOGIC
SUPPLY
5V
TYPICAL
TTL GATE
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT
SWING TO TTL LEVELS
1
0.01 0.1
LOAD (SINKING) CURRENT (mA)
1.0 10
10
100
1000
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SATURATION VOLTAGE (mV)
SUPPLY VOLTAGE (V-) = 0V
TA = 25oC
SUPPLY VOLTAGE (V+) = +5V +15V
+30V
FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15
AND Q16) vs LOAD CURRENT
FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
3
2
4
CA3140
7
6
V+
5
1
V-
10k
3
2
4
CA3140
7
6
V+
5
1
V-
10k
RR
3
2
4
CA3140
7
6
V+
5
1
V-
10k
R
CA3140, CA3140A
FN957 Rev.10.00 Page 9 of 24
Jul 11, 2005
Bandwidth and Slew Rate
For those cases where bandwidth reduction is desired, for
example, broadband noise reduction, an external capacitor
connected between Terminals 1 and 8 can reduce the open
loop -3dB bandwidth. The slew rate will, however, also be
proportionally reduced by using this additional capacitor. Thus,
a 20% reduction in bandwidth by this technique will also
reduce the slew rate by about 20%.
Figure 5 shows the typical settling time required to reach 1mV
or 10mV of the final value for various levels of large signal
inputs for the voltage follower and inverting unity gain
amplifiers.
The exceptionally fast settling time characteristics are largely
due to the high combination of high gain and wide bandwidth of
the CA3140; as shown in Figure 6.
Input Circuit Considerations
As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiting resistance should be provided
between the inverting input and the output when the CA3140 is
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
3
2
4
CA3140
7
6
LOAD
RL
RS
MT2
MT1
30V
NO LOAD
120VAC
3
2
4
CA3140
7
6
V+ +HV
LOAD
RL
FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS
FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
SETTLING TIME (s)
0.1
INPUT VOLTAGE (V)
1.0 10
SUPPLY VOLTAGE: VS = 15V
TA = 25oC
1mV
10mV 10mV
1mV
1mV1mV
10mV
FOLLOWER
INVERTING
LOAD RESISTANCE (RL) = 2k
LOAD CAPACITANCE (CL) = 100pF
10
8
6
4
2
0
-2
-4
-6
-8
-10
10mV
3
2
CA3140 6
SIMULATED
LOAD
4
-15V
0.1F5.11k
0.1F
7
+15V
5k
2k
100pF
5k
INVERTING
SETTLING POINT
200
4.99k
D1
1N914
D2
1N914
2
CA3140 6
SIMULATED
LOAD
4
-15V
0.1F
0.1F
7
+15V
2k
100pF
0.05F
2k
3
10k
FOLLOWER
CA3140, CA3140A
FN957 Rev.10.00 Page 10 of 24
Jul 11, 2005
used as a unity gain voltage follower. This resistance prevents
the possibility of extremely large input signal transients from
forcing a signal through the input protection network and
directly driving the internal constant current source which could
result in positive feedback via the output terminal. A 3.9k
resistor is sufficient.
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 7 shows typical input terminal current versus
ambient temperature for the CA3140.
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in input
offset voltage) due to the application of large differential input
voltages that are sustained over long periods at elevated
temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts of
the opposite polarity reverse the offset. Figure 9 shows the
typical offset voltage change as a function of various stress
voltages at the maximum rating of 125oC (for metal can); at
lower temperatures (metal can and plastic), for example, at
85oC, this change in voltage is considerably less. In typical
linear applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the same
magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage.
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY
FIGURE 7. INPUT CURRENT vs TEMPERATURE
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
101103104105106107108
FREQUENCY (Hz)
OPEN LOOP VOLTAGE GAIN (dB)
100
80
60
40
20
0
SUPPLY VOLTAGE: VS = 15V
TA = 25oC
102
OPEN LOOP PHASE
-75
-90
-105
-120
-135
-150
(DEGREES)
RL = 2k,
CL = 0pF
RL = 2k,
CL = 100pF
OL
SUPPLY VOLTAGE: VS = 15V
TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA)
1K
100
1
10K
10
SUPPLY VOLTAGE (V+, V-)
0 5 10 15 20 25
-1.5
-2.0
-1.0
-2.5
RL =
+VOUT AT TA = 125oC
+VOUT AT TA = 25oC
+VOUT AT TA = -55oC
+VICR AT TA = 125oC
+VICR AT TA = 25oC
+VICR AT TA = -55oC
-3.0
0
-0.5
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 7 (V+)
SUPPLY VOLTAGE (V+, V-)
0 5 10 15 20 25
-VICR AT TA = 125oC
-VICR AT TA = 25oC
-VICR AT TA = -55oC
-VOUT FOR
TA = -55oC to 125oC
INPUT AND OUTPUT VOLTAGE EXCURSIONS
FROM TERMINAL 4 (V-)
0
-0.5
0.5
-1.0
-1.5
1.5
1.0
CA3140, CA3140A
FN957 Rev.10.00 Page 11 of 24
Jul 11, 2005
Super Sweep Function Generator
A function generator having a wide tuning range is shown in
Figure 10. The 1,000,000/1 adjustment range is accomplished
by a single variable potentiometer or by an auxiliary sweeping
signal. The CA3140 functions as a non-inverting readout
amplifier of the triangular signal developed across the
integrating capacitor network connected to the output of the
CA3080A current source.
Buffered triangular output signals are then applied to a second
CA3080 functioning as a high speed hysteresis switch. Output
from the switch is returned directly back to the input of the
CA3080A current source, thereby, completing the positive
feedback loop
The triangular output level is determined by the four 1N914
level limiting diodes of the second CA3080 and the resistor
divider network connected to Terminal No. 2 (input) of the
CA3080. These diodes establish the input trip level to this
switching stage and, therefore, indirectly determine the
amplitude of the output triangle.
Compensation for propagation delays around the entire loop is
provided by one adjustment on the input of the CA3080. This
adjustment, which provides for a constant generator amplitude
output, is most easily made while the generator is sweeping.
High frequency ramp linearity is adjusted by the single 7pF to
60pF capacitor in the output of the CA3080A.
It must be emphasized that only the CA3080A is characterized
for maximum output linearity in the current generator function.
Meter Driver and Buffer Amplifier
Figure 11 shows the CA3140 connected as a meter driver and
buffer amplifier. Low driving impedance is required of the
CA3080A current source to assure smooth operation of the
Frequency Adjustment Control. This low-driving impedance
requirement is easily met by using a CA3140 connected as a
voltage follower. Moreover, a meter may be placed across the
input to the CA3080A to give a logarithmic analog indication of
the function generator’s frequency.
Analog frequency readout is readily accomplished by the means
described above because the output current of the CA3080A
varies approximately one decade for each 60mV change in the
applied voltage, VABC (voltage between Terminals 5 and 4 of the
CA3080A of the function generator). Therefore, six decades
represent 360mV change in VABC.
Now, only the reference voltage must be established to set the
lower limit on the meter. The three remaining transistors from
the CA3086 Array used in the sweep generator are used for
this reference voltage. In addition, this reference generator
arrangement tends to track ambient temperature variations,
and thus compensates for the effects of the normal negative
temperature coefficient of the CA3080A VABC terminal voltage.
Another output voltage from the reference generator is used to
insure temperature tracking of the lower end of the Frequency
Adjustment Potentiometer. A large series resistance simulates
a current source, assuring similar temperature coefficients at
both ends of the Frequency Adjustment Control.
To calibrate this circuit, set the Frequency Adjustment
Potentiometer at its low end. Then adjust the Minimum
Frequency Calibration Control for the lowest frequency. To
establish the upper frequency limit, set the Frequency
Adjustment Potentiometer to its upper end and then adjust the
Maximum Frequency Calibration Control for the maximum
frequency. Because there is interaction among these controls,
repetition of the adjustment procedure may be necessary. Two
adjustments are used for the meter. The meter sensitivity
control sets the meter scale width of each decade, while the
meter position control adjusts the pointer on the scale with
negligible effect on the sensitivity adjustment. Thus, the meter
sensitivity adjustment control calibrates the meter so that it
deflects 1/6 of full scale for each decade change in frequency.
Sine Wave Shaper
The circuit shown in Figure 12 uses a CA3140 as a voltage
follower in combination with diodes from the CA3019 Array to
convert the triangular signal from the function generator to a
sine-wave output signal having typically less than 2% THD.
The basic zero crossing slope is established by the 10k
potentiometer connected between Terminals 2 and 6 of the
CA3140 and the 9.1k resistor and 10k potentiometer from
Terminal 2 to ground. Two break points are established by
diodes D1 through D4. Positive feedback via D5 and D6
establishes the zero slope at the maximum and minimum
levels of the sine wave. This technique is necessary because
the voltage follower configuration approaches unity gain rather
than the zero gain required to shape the sine wave at the two
extremes.
7
6
5
4
3
2
0
OFFSET VOLTAGE SHIFT (mV)
0 500 1000 1500 2000 2500 3000 3500 4000 4500
TIME (HOURS)
1
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
TA = 125oC
FOR METAL CAN PACKAGES
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE
SHIFT vs OPERATING LIFE
CA3140, CA3140A
FN957 Rev.10.00 Page 12 of 24
Jul 11, 2005
FIGURE 10A. CIRCUIT
Top Trace: Output at junction of 2.7 and 51 resistors;
5V/Div., 500ms/Div.
Center Trace: External output of triangular function generator;
2V/Div., 500ms/Div.
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div.
FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING
1V/Div., 1s/Div.
Three tone test signals, highest frequency 0.5MHz. Note the slight
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the CA3080A
and from the PC board and component leakages at the 100pA level.
FIGURE 10C. FUNCTION GENERATOR WITH FIXED
FREQUENCIES
FIGURE 10D. INTERCONNECTIONS
FIGURE 10. FUNCTION GENERATOR
0.1
F
1N914
6
7
4
2
3
0.1
F
5.1k
10k
2.7k
6
7
4
2
5
-15V
13k
+15V
CENTERING
10k
-15V
910k62k
11k
10k
EXTERNAL
OUTPUT
11k
HIGH
FREQUENCY
LEVEL
7-60pF
EXTERNAL
OUTPUT
TO OUTPUT
AMPLIFIER
OUTPUT
AMPLIFIER
TO
SINE WAVE
SHAPER
2k
FREQUENCY
ADJUSTMENT
HIGH
FREQ.
SHAPE
SYMMETRY
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
-15V +15V
10k120
39k
100k
3
6
3
24
7
7.5k+15V+15V
15k
360
360
2M
7-60
pF
-15V
-15V +15V
51
pF
+
CA3080A
-CA3140
CA3080
+
-
+
-
5
-15V
FROM BUFFER METER
DRIVER (OPTIONAL)
FREQUENCY
ADJUSTMENT
METER DRIVER
AND BUFFER
AMPLIFIER
FUNCTION
GENERATOR
SINE WAVE
SHAPER
M
POWER
SUPPLY 15V
-15V
+15V
DC LEVEL
ADJUST
51
WIDEBAND
LINE DRIVER
SWEEP
GENERATOR
GATE
SWEEP
V-
SWEEP
LENGTH
EXTERNAL
INPUT
OFF
V-
COARSE
RATE
FINE
RATE
EXT.
INT.
CA3140, CA3140A
FN957 Rev.10.00 Page 13 of 24
Jul 11, 2005
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER
FIGURE 13. SWEEPING GENERATOR
FREQUENCY
CALIBRATION
MINIMUM
200A
METER
FREQUENCY
CALIBRATION
MAXIMUM
METER
SENSITIVITY
ADJUSTMENT
METER
POSITION
ADJUSTMENT
CA3080A
6
3
2
4
7
+
CA3140
-
FREQUENCY
ADJUSTMENT
10k
620
4.7k
0.1F
12k
2k
500k
620k
51k
3M
510
510
2k
3.6k
-15V
M
11
14
13
3/5 OF CA3086
5
4
TO CA3080A
OF FUNCTION
GENERATOR
(FIGURE 10)
7
8
6
9
1k
2.4k
2.5
k
+15V
SWEEP IN
10
12
6
3
24
7
+
CA3140
-
7
2856
1
43
9
5.1k
0.1F
-15V
D1D4
D2
D3D6
D5
CA3019
DIODE ARRAY
EXTERNAL
OUTPUT
+15V
+15V
-15V
100
k
SUBSTRATE
OF CA3019
TO
WIDEBAND
OUTPUT
AMPLIFIER
7.5k
5.6k
-15V
R3 10k
10k
0.1F
1M
9.1k
R1
10k
R2
1k
430
4
7
+
CA3140
-
0.1
+15V
-15V
2
3
6
F
0.1
F
COARSE
RATE
SAWTOOTH
SYMMETRY
0.47F
0.047F
4700pF
470pF
7
3
2
6
4
+
CA3140
-
5
1
3
24
15
51k6.8k91k10k
100
390
3.9
25k
+15V
-15V
10k
10k
100k
30k
43k
LOGVIO
50k
LOG
RATE
10kGATE
PULSE
OUTPUT
-15V
EXTERNAL OUTPUT
TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
TO OUTPUT
AMPLIFIER
36k
51k
75k
50k
SAWTOOTH
“LOG”
TRIANGLE
+15V
+15V
4
7
+
CA3140
-
3
2
6
+15V
TRANSISTORS
FROM CA3086
ARRAY
ADJUST
TRIANGLE
SAWTOOTH
“LOG”
8.2k
100k
100k
FINE
RATE
SAWTOOTH
22M
1M
18M
750k
“LOG”
1N914
1N914 SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
-15V
CA3140, CA3140A
FN957 Rev.10.00 Page 14 of 24
Jul 11, 2005
This circuit can be adjusted most easily with a distortion
analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave generator.
The initial slope is adjusted with the potentiometer R1, followed
by an adjustment of R2. The final slope is established by
adjusting R3, thereby adding additional segments that are
contributed by these diodes. Because there is some interaction
among these controls, repetition of the adjustment procedure
may be necessary.
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that determines
the starting and stopping points of the sweep. A third CA3140
is used as a logarithmic shaping network for the log function.
Rates and slopes, as well as sawtooth, triangle, and
logarithmic sweeps are generated by this circuit.
Wideband Output Amplifier
Figure 14 shows a high slew rate, wideband amplifier suitable
for use as a 50 transmission line driver. This circuit, when
used in conjunction with the function generator and sine wave
shaper circuits shown in Figures 10 and 12 provides 18VP-P
output open circuited, or 9VP-P output when terminated in 50.
The slew rate required of this amplifier is 28V/s (18VP-P x x
0.5MHz).
Power Supplies
High input impedance, common mode capability down to the
negative supply and high output drive current capability are key
factors in the design of wide range output voltage supplies that
use a single input voltage to provide a regulated output voltage
that can be adjusted from essentially 0V to 24V.
Unlike many regulator systems using comparators having a
bipolar transistor input stage, a high impedance reference
voltage divider from a single supply can be used in connection
with the CA3140 (see Figure 15).
Essentially, the regulators, shown in Figures 16 and 17, are
connected as non inverting power operational amplifiers with a
gain of 3.2. An 8V reference input yields a maximum output
voltage slightly greater than 25V. As a voltage follower, when the
reference input goes to 0V the output will be 0V. Because the
offset voltage is also multiplied by the 3.2 gain factor, a
potentiometer is needed to null the offset voltage.
Series pass transistors with high ICBO levels will also prevent
the output voltage from reaching zero because there is a finite
voltage drop (VCESAT) across the output of the CA3140 (see
Figure 2). This saturation voltage level may indeed set the
lowest voltage obtainable.
The high impedance presented by Terminal 8 is advantageous
in effecting current limiting. Thus, only a small signal transistor
is required for the current-limit sensing amplifier. Resistive
decoupling is provided for this transistor to minimize damage to
it or the CA3140 in the event of unusual input or output
transients on the supply rail.
Figures 16 and 17, show circuits in which a D2201 high speed
diode is used for the current sensor. This diode was chosen for
its slightly higher forward voltage drop characteristic, thus giving
greater sensitivity. It must be emphasized that heat sinking of
this diode is essential to minimize variation of the current trip
point due to internal heating of the diode. That is, 1A at 1V
forward drop represents one watt which can result in significant
regenerative changes in the current trip point as the diode
temperature rises. Placing the small signal reference amplifier in
the proximity of the current sensing diode also helps minimize
the variability in the trip level due to the negative temperature
coefficient of the diode. In spite of those limitations, the current
limiting point can easily be adjusted over the range from 10mA
to 1A with a single adjustment potentiometer. If the temperature
stability of the current limiting system is a serious consideration,
the more usual current sampling resistor type of circuitry should
be employed.
A power Darlington transistor (in a metal can with heatsink), is
used as the series pass element for the conventional current
limiting system, Figure 16, because high power Darlington
dissipation will be encountered at low output voltage and high
currents.
2
6
8
1
4
7
+
CA3140
-
50F
25V
2.2
k2N3053
1N914
2.2
k
1N914
2.7
2.7
2N4037
+
-
+
-50F
25V
3
SIGNAL
LEVEL
ADJUSTMENT
2.5k
200
2.4pF
2pF -15V
+15V
OUTPUT
DC LEVEL
ADJUSTMENT
-15V
+15V
3k
2001.8k
51
2W
OUT
NOMINAL BANDWIDTH = 10MHz
tr = 35ns
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER
6
3
24
7
+
CA3140
-
VOLTAGE
REFERENCE
VOLTAGE
ADJUSTMENT
REGULATED
OUTPUT
INPUT
FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
SHOWING VOLTAGE FOLLOWER CONFIGURATION
CA3140, CA3140A
FN957 Rev.10.00 Page 15 of 24
Jul 11, 2005
A small heat sink VERSAWATT transistor is used as the series
pass element in the fold back current system, Figure 17, since
dissipation levels will only approach 10W. In this system, the
D2201 diode is used for current sampling. Foldback is
provided by the 3k and 100k divider network connected to
the base of the current sensing transistor.
Both regulators provide better than 0.02% load regulation.
Because there is constant loop gain at all voltage settings, the
regulation also remains constant. Line regulation is 0.1% per
volt. Hum and noise voltage is less than 200V as read with a
meter having a 10MHz bandwidth.
Figure 18A shows the turn ON and turn OFF characteristics of
both regulators. The slow turn on rise is due to the slow rate of
rise of the reference voltage. Figure 18B shows the transient
response of the regulator with the switching of a 20 load at
20V output.
FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK”
CURRENT LIMITING
5V/Div., 1s/Div.
FIGURE 18A. SUPPLY TURN-ON AND TURNOFF
CHARACTERISTICS
Top Trace: Output Voltage;
200mV/Div., 5s/Div.
Bottom Trace: Collector of load switching transistor, load = 1A;
5V/Div., 5s/Div.
FIGURE 18B. TRANSIENT RESPONSE
FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17
1
3
75
3k
100
2
1k1k
D2201
CURRENT
LIMITING
ADJUST
2N6385
POWER DARLINGTON
2
1k
1
3
8
2N2102
1k
+30V
INPUT
4
CA3140
7
1
6
5
100k
2
3
180k56pF
1k82k
250F
+
-
0.01F
100k
14
10
6
9
8
50k
13
5F
+
-
12
CA3086
2.2k
3
1
5
4
62k
VOLTAGE
ADJUST
10F+
-
2.7k
1k
11
7
2
HUM AND NOISE OUTPUT <200VRMS
(MEASUREMENT BANDWIDTH ~10MHz)
LINE REGULATION 0.1%/V
LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%
OUTPUT
0.1 24V
AT 1A
1
2
1k200
D2201
“FOLDBACK” CURRENT
LIMITER
2N5294
3k
8
2N2102
1k
+30V
INPUT
4
CA3140
7
1
6
5
100k
2
3
180k56pF
1k82k
250F
+
-
0.01F
100k
14
10
6
9
8
50k
13
5F
+
-
12
CA3086
2.2k
3
1
5
4
62k
VOLTAGE
ADJUST
10F+
-
2.7k
1k
11
7
2
HUM AND NOISE OUTPUT <200VRMS
(MEASUREMENT BANDWIDTH ~10MHz)
LINE REGULATION 0.1%/V
LOAD REGULATION
(NO LOAD TO FULL LOAD)
<0.02%
OUTPUT 0V TO 25V
25V AT 1A
3
100k
“FOLDS BACK”
TO 40mA
100k
CA3140, CA3140A
FN957 Rev.10.00 Page 16 of 24
Jul 11, 2005
Tone Control Circuits
High slew rate, wide bandwidth, high output voltage capability
and high input impedance are all characteristics required of
tone control amplifiers. Two tone control circuits that exploit
these characteristics of the CA3140 are shown in Figures 19
and 20.
The first circuit, shown in Figure 20, is the Baxandall tone
control circuit which provides unity gain at midband and uses
standard linear potentiometers. The high input impedance of
the CA3140 makes possible the use of low-cost, low-value,
small size capacitors, as well as reduced load of the driving
stage.
Bass treble boost and cut are 15dB at 100Hz and 10kHz,
respectively. Full peak-to-peak output is available up to at least
20kHz due to the high slew rate of the CA3140. The amplifier
gain is 3dB down from its “flat” position at 70kHz.
Figure 19 shows another tone control circuit with similar boost
and cut specifications. The wideband gain of this circuit is
equal to the ultimate boost or cut plus one, which in this case is
a gain of eleven. For 20dB boost and cut, the input loading of
this circuit is essentially equal to the value of the resistance
from Terminal No. 3 to ground. A detailed analysis of this circuit
is given in “An IC Operational Transconductance Amplifier
(OTA) With Power Capability” by L. Kaplan and H. Wittlinger,
IEEE Transactions on Broadcast and Television Receivers,
Vol. BTR-18, No. 3, August, 1972.
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES
4
7
+
CA3140
-
+30V
3
2
0.1F
6
0.005F
0.1
F
2.2M
2.2M
5.1
M
0.012F0.001F
0.022F
2F
18k
0.0022F
200k
(LINEAR)
100
pF 100pF
BOOST TREBLE CUT
BOOST BASS CUT
10k1M
CCW (LOG)
100k
TONE CONTROL NETWORK
FOR SINGLE SUPPLY
-+
+15V
30.1F
0.005F
5.1M
0.1F
-15V
2
6
7
4
+
CA3140
-
TONE CONTROL NETWORK
FOR DUAL SUPPLIES
NOTES:
5. 20dB Flat Position Gain.
6. 15dB Bass and Treble Boost and Cut
at 100Hz and 10kHz, respectively.
7. 25VP-P output at 20kHz.
8. -3dB at 24kHz from 1kHz reference.
4
7
+
CA3140
-
+32V
3
0.1
2.2M
2.2
M
FOR SINGLE SUPPLY
F
6
2
0.1
F
20pF
750
pF
750
pF
2.2M
0.047F
BOOST TREBLE CUT
51k5M
(LINEAR)
51k
TONE CONTROL NETWORK
BOOST BASS CUT
240k5M
(LINEAR)
240k
+15V
3
0.1F
0.047F
0.1F
-15V
2
6
7
4
+
CA3140
-
FOR DUAL SUPPLIES

9. 15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively.
10. 25VP-P Output at 20kHz.
11. -3dB at 70kHz from 1kHz Reference.
12. 0dB Flat Position Gain.
TONE CONTROL
NETWORK
CA3140, CA3140A
FN957 Rev.10.00 Page 17 of 24
Jul 11, 2005
Wien Bridge Oscillator
Another application of the CA3140 that makes excellent use of
its high input impedance, high slew rate, and high voltage
qualities is the Wien Bridge sine wave oscillator. A basic Wien
Bridge oscillator is shown in Figure 21. When R1 = R2 = R and
C1 = C2 = C, the frequency equation reduces to the familiar
f=1/(2RC) and the gain required for oscillation, AOSC is
equal to 3. Note that if C2 is increased by a factor of four and
R2 is reduced by a factor of four, the gain required for
oscillation becomes 1.5, thus permitting a potentially higher
operating frequency closer to the gain bandwidth product of the
CA3140.
Oscillator stabilization takes on many forms. It must be
precisely set, otherwise the amplitude will either diminish or
reach some form of limiting with high levels of distortion. The
element, RS, is commonly replaced with some variable
resistance element. Thus, through some control means, the
value of RS is adjusted to maintain constant oscillator output. A
FET channel resistance, a thermistor, a lamp bulb, or other
device whose resistance increases as the output amplitude is
increased are a few of the elements often utilized.
Figure 22 shows another means of stabilizing the oscillator
with a zener diode shunting the feedback resistor (RF of Figure
21). As the output signal amplitude increases, the zener diode
impedance decreases resulting in more feedback with
consequent reduction in gain; thus stabilizing the amplitude of
the output signal. Furthermore, this combination of a monolithic
zener diode and bridge rectifier circuit tends to provide a zero
temperature coefficient for this regulating system. Because this
bridge rectifier system has no time constant, i.e., thermal time
constant for the lamp bulb, and RC time constant for filters
often used in detector networks, there is no lower frequency
limit. For example, with 1F polycarbonate capacitors and
22M for the frequency determining network, the operating
frequency is 0.007Hz.
As the frequency is increased, the output amplitude must be
reduced to prevent the output signal from becoming slew-rate
limited. An output frequency of 180kHz will reach a slew rate of
approximately 9V/s when its amplitude is 16VP-P.
Simple Sample-and-Hold System
Figure 23 shows a very simple sample-and-hold system using
the CA3140 as the readout amplifier for the storage capacitor.
The CA3080A serves as both input buffer amplifier and low
feed-through transmission switch (see Note 13). System offset
nulling is accomplished with the CA3140 via its offset nulling
terminals. A typical simulated load of 2k and 30pF is shown
in the schematic.
In this circuit, the storage compensation capacitance (C1) is
only 200pF. Larger value capacitors provide longer “hold”
periods but with slower slew rates. The slew rate is:
NOTE:
13. AN6668 “Applications of the CA3080 and CA 3080A High
Performance Operational Transconductance Amplifiers”.
NOTES:
f1
2R1C1R2C2
-------------------------------------------
=
AOSC 1
C1
C2
-------R2
R1
-------
++=
ACL 1
RF
RS
--------
+=
C1
R2
R1
C2
OUTPUT
RF
RS
+
-
FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT
USING AN OPERATIONAL AMPLIFIER
8
5 4
3
1
9
6
CA3109
DIODE
ARRAY
+15V
0.1F
0.1F
-15V
2
6
7
4
+
CA3140
-SUBSTRATE
OF CA3019
0.1F
7
7.5k
3.6k
500
OUTPUT
19VP-P TO 22VP-P
THD <0.3%
3
R2
C21000pF
1000
pF
C1
R1
R1 = R2 = R
50Hz, R = 3.3M
100Hz, R = 1.6M
1kHz, R = 160M
10kHz, R = 16M
30kHz, R = 5.1M
2
FIGURE 22. WIEN BRIDGE OSCILLATOR CIRCUIT USING
CA3140
+15V
3.5k
30pF
2
6
1
+
CA3140
-
SIMULATED LOAD
NOT REQUIRED
100k
INPUT
0.1
0.1F
F
7
0.1F
-15V 2k
3
400
200pF
6
4
5
7
4
+
CA3080A
-
0.1F
+15V
-15V
200pF
2k
2
3
5
2k
STROBE
SAMPLE
HOLD-15
0
30k
1N914
1N914
2k
C1
FIGURE 23. SAMPLE AND HOLD CIRCUIT
CA3140, CA3140A
FN957 Rev.10.00 Page 18 of 24
Jul 11, 2005
Pulse “droop” during the hold interval is 170pA/200pF which is
0.85V/s; (i.e., 170pA/200pF). In this case, 170pA represents
the typical leakage current of the CA3080A when strobed off. If C1
were increased to 2000pF, the “hold-droop” rate will decrease to
0.085V/s, but the slew rate would decrease to 0.25V/s. The
parallel diode network connected between Terminal 3 of the
CA3080A and Terminal 6 of the CA3140 prevents large input
signal feedthrough across the input terminals of the CA3080A to
the 200pF storage capacitor when the CA3080A is strobed off.
Figure 24 shows dynamic characteristic waveforms of this
sample-and-hold system.
Current Amplifier
The low input terminal current needed to drive the CA3140
makes it ideal for use in current amplifier applications such as
the one shown in Figure 25 (see Note 14). In this circuit, low
current is supplied at the input potential as the power supply to
load resistor RL. This load current is increased by the
multiplication factor R2/R1, when the load current is monitored
by the power supply meter M. Thus, if the load current is
100nA, with values shown, the load current presented to the
supply will be 100A; a much easier current to measure in
many systems.
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by the
scale factor.
The dotted components show a method of decoupling the
circuit from the effects of high output load capacitance and the
potential oscillation in this situation. Essentially, the necessary
high frequency feedback is provided by the capacitor with the
dotted series resistor providing load decoupling.
Full Wave Rectifier
Figure 26 shows a single supply, absolute value, ideal full-
wave rectifier with associated waveforms. During positive
excursions, the input signal is fed through the feedback
network directly to the output. Simultaneously, the positive
excursion of the input signal also drives the output terminal
(No. 6) of the inverting amplifier in a negative going excursion
such that the 1N914 diode effectively disconnects the amplifier
from the signal path. During a negative going excursion of the
input signal, the CA3140 functions as a normal inverting
amplifier with a gain equal to -R2/R1. When the equality of the
two equations shown in Figure 26 is satisfied, the full wave
output is symmetrical.
NOTE:
14. “Operational Amplifiers Design and Applications”, J. G. Graeme,
McGraw-Hill Book Company, page 308, “Negative Immittance
Converter Circuits”.
Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
Top Trace: Output Signal; 5V/Div, 2s/Div.
Center Trace: Difference of Input and Output Signals through
Tektronix Amplifier 7A13; 5mV/Div., 2s/Div.
Bottom Trace: Input Signal; 5V/Div., 2s/Div.
LARGE SIGNAL RESPONSE AND SETTLING TIME
SAMPLING RESPONSE
Top Trace: Output; 100mV/Div., 500ns/Div.
Bottom Trace: Input; 20V/Div., 500ns/Div.
FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC
CHARACTERISTICS WAVEFORMS
+15V
2
1
100k
0.1F
-15V
4
5
7
+
CA3140
-0.1F
4.3k
10k
6
3
R1
POWER
SUPPLY
10M
R2
ILR2
R1
M
RL
IL
x
FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT
MEASUREMENT SYSTEMS
CA3140, CA3140A
FN957 Rev.10.00 Page 19 of 24
Jul 11, 2005
+15V
3
0.1F
8
5k
7
15
6
2
R2
R1
10k
R3
1N914
10k
100k
OFFSET
ADJUST
4
PEAK
ADJUST
10k
+
CA3140
-
20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V
GAIN
R2
R1
-------X
R3
R1R2R3
+
-----------------------------
===
R3
XX
2
+
1X–
-----------------


R1
=
FOR X 0.5 5k
10k
---------------R2
R1
-------
==
R310k0.75
0.5
-----------


15k==
OUTPUT
0
INPUT
0
FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL
FULL WAVE RECTIFIER WITH ASSOCIATED
WAVEFORMS
+15V
-15V
2
7
4
+
CA3140
-
3
0.01F
0.01F
6
1MNOISE VOLTAGE
OUTPUT
30.1k
1k
RS
BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48V (TYP)
FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENT
Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
FIGURE 28B. SMALL SIGNAL RESPONSE
(Measurement made with Tektronix 7A13 differential amplifier.)
Top Trace: Output Signal; 5V/Div., 5s/Div.
Center Trace: Difference Signal; 5mV/Div., 5s/Div.
Bottom Trace: Input Signal; 5V/Div., 5s/Div.
FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST
CIRCUIT AND ASSOCIATED WAVEFORMS
+15V
-15V
2
7
4
+
CA3140
-
3
0.1F
0.1F
6
0.05F
2k
10k
100pF
SIMULATED
LOAD
2k
BW (-3dB) = 4.5MHz
SR = 9V/s
FIGURE 28A. TEST CIRCUIT
INPUT
CA3140, CA3140A
FN957 Rev.10.00 Page 20 of 24
Jul 11, 2005
Typical Performance Curves
FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY
VOLTAGE AND TEMPERATURE
FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE
FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND
TEMPERATURE
FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE AND TEMPERATURE
FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs
FREQUENCY
FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY
125
100
75
50
25
OPEN-LOOP VOLTAGE GAIN (dB)
0 5 10 15 20
SUPPLY VOLTAGE (V)
125oC
25oC
TA = -55oC
RL = 2k
25
0
GAIN BANDWIDTH PRODUCT (MHz)
125oC
25oC
TA = -55oC
RL = 2k
20
10
0 5 10 15 20
SUPPLY VOLTAGE (V)
25
CL = 100pF
1
125oC
25oC
TA = -55oC
RL = 2k
5101520
SUPPLY VOLTAGE (V)
25
CL = 100pF
20
15
10
5
0
SLEW RATE (V/s)
0
7
6
5
4
3
0 5 10 15 20
SUPPLY VOLTAGE (V)
125oC
TA = -55oC
RL =
25
0
2
1
25oC
QUIESCENT SUPPLY CURRENT (mA)
25
20
15
10
5
0
OUTPUT SWING (VP-P)
10K 100K
FREQUENCY (Hz)
1M 4M
SUPPLY VOLTAGE: VS =15V
TA = 25oC
120
100
80
60
40
20
0
COMMON-MODE REJECTION RATIO (dB)
101102103104105106107
FREQUENCY (Hz)
SUPPLY VOLTAGE: VS =15V
TA = 25oC
CA3140, CA3140A
FN957 Rev.10.00 Page 21 of 24
Jul 11, 2005
FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY
FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY
Typical Performance Curves (Continued)
SUPPLY VOLTAGE: VS =15V
TA = 25oC
FREQUENCY (Hz)
110
1102103104105
EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)
100
10
1
1000
102103104105106107
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
100
80
60
40
20
0
+PSRR
-PSRR
SUPPLY VOLTAGE: VS =15V
TA = 25oC
POWER SUPPLY REJECTION RATIO
(PSRR) = VIO/VS
101
CA3140, CA3140A
FN957 Rev.10.00 Page 22 of 24
Jul 11, 2005
Metallization Mask Layout
Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is
part of the wafer. When the wafer is cut into chips, the cleavage
angles are 57o instead of 90 with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
62-70
(1.575-1.778)
4-10
(0.102-0.254)
60
50
40
30
20
10
0
58-66
(1.473-1.676)
5040302010
61
060 65
CA3140, CA3140A
FN957 Rev.10.00 Page 23 of 24
Jul 11, 2005
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
FN957 Rev.10.00 Page 24 of 24
Jul 11, 2005
CA3140, CA3140A
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2002-2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
0o8o0o8o-
Rev. 0 12/93