Sample & Buy Product Folder Support & Community Tools & Software Technical Documents THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 THS4541 Negative Rail Input, Rail-to-Rail Output, Precision, 850-MHz Fully Differential Amplifier 1 Features 3 Description * * * * * * * * * * * * * The THS4541 is a low-power, voltage-feedback, fully differential amplifier (FDA) with an input commonmode range below the negative rail, and rail-to-rail output. Designed for low-power data acquisition systems where high density is critical in a highperformance analog-to-digital converter (ADC) or digital-to-analog converter (DAC) interface design. * Fully Differential Amplifier (FDA) Architecture Bandwidth: 500 MHz (G = 2 V/V) Gain Bandwidth Product: 850 MHz Slew Rate: 1500 V/s HD2: -95 dBc at 10 MHz (2 VPP, RL = 500 ) HD3: -90 dBc at 10 MHz (2 VPP, RL = 500 ) Input Voltage Noise: 2.2 nV/Hz (f > 100 kHz) Low offset drift: 0.5 V/C (typ) Negative Rail Input (NRI) Rail-to-Rail Output (RRO) Robust Operation for Rload 50 Output Common-Mode Control Power Supply: - Single-Supply Voltage Range: 2.7 V to 5.4 V - Split-Supply Voltage Range: 1.35 V to 2.7 V - Quiescent Current: 10.1 mA (5-V Supply) Power-Down Capability: 2 A (typ) * * * * * Low-Power, High-Performance ADC Driver - SAR, , and Pipeline Low Power, High Performance (DC or AC Coupled) - Single-Ended to Differential Amplifier - Differential to Differential Amplifier Differential Active Filters Differential Transimpedance for DAC Outputs DC- or AC-Coupled Interface to the ADC3xxx Family of Low-Power, High-Performance ADCs Pin-Compatible to ADA4932-1 (VQFN-16) Simplified Schematic 50- Source Device Information(1) THS4541 FDA -60 Output Rload Measurement 500 Point + + PD Rg2 221 C2 100 nF 2.00 mm x 2.00 mm -50 Vcc Vocm WQFN (10) HD2 HD3 -70 Rt 60.2 BODY SIZE (NOM) 3.00 mm x 3.00 mm Single to Differential Gain of 2, 2-VPP Output Rf1 402 Rg1 191 PACKAGE VQFN (16) (1) For all available packages, see the package option addendum at the end of the data sheet. THS4541 Wideband, Fully-Differential Amplifier 50- Input Match, Gain of 2 V/V from Rt, Single-Ended Source to Differential Output C1 100 nF The THS4541 is characterized for operation over the wide temperature range of -40C to 125C available in 16-pin VQFN and 10-pin WQFN packages. PART NUMBER 2 Applications * The THS4541 features the negative-rail input required when interfacing a dc-coupled, groundcentered, source signal. This negative-rail input, with rail-to-rail output, allows for easy interface between single-ended, ground-referenced, bipolar signal sources and a wide variety of successive approximation register (SAR), delta-sigma (), or pipeline ADCs using only a single +2.7-V to +5.4-V power supply. Distortion (dBc) 1 -80 -90 -100 -110 -120 Vcc -130 Rf2 402 -140 0.1 1 Frequency (MHz) 10 50 D013 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Family Comparison................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 Handling Ratings....................................................... 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics: Vs+ - Vs- = 5 V ............. 5 Electrical Characteristics: Vs+ - Vs- = 3 V ............. 8 Typical Characteristics: 5-V Single Supply ............. 11 Typical Characteristics: 3-V Single Supply ............. 14 Typical Characteristics: 3-V to 5-V Supply Range.. 17 Parameter Measurement Information ................ 21 8.1 8.2 8.3 8.4 Example Characterization Circuits .......................... 21 Frequency-Response Shape Factors ..................... 23 I/O Headroom Considerations ................................ 26 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances ............................................ 28 8.5 Noise Analysis......................................................... 30 8.6 Factors Influencing Harmonic Distortion ................. 31 8.7 Driving Capacitive Loads ........................................ 32 8.8 Thermal Analysis..................................................... 32 9 Detailed Description ............................................ 33 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 33 34 35 36 10 Application And Implementation ....................... 44 10.1 Application Information.......................................... 44 10.2 Typical Applications .............................................. 44 11 Power-Supply Recommendations ..................... 49 12 Layout................................................................... 49 12.1 Layout Guidelines ................................................. 49 12.2 Layout Example .................................................... 50 13 Device and Documentation Support ................. 51 13.1 13.2 13.3 13.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 51 51 51 51 14 Mechanical, Packaging, and Orderable Information ........................................................... 51 4 Revision History Changes from Original (August 2014) to Revision A Page * Added clarifying text to note 1 in Pin Functions table. ........................................................................................................... 3 * Changed "Vcm" to "Vicm" in first paragraph ........................................................................................................................ 29 * Changed 0.9 V to 0.91 V in second paragraph of Overview section ................................................................................... 33 * Changed 0.9 V to 0.91 V in first paragraph of AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion section ................................................................................................................................. 36 * Changed "single" to "signal" in first paragraph of Application Information section ............................................................. 44 * Changed "usually" to "always" in fourth sentence of Detailed Design Procedure section ................................................... 44 * Added "(in Hz)" to second paragraph of this page ............................................................................................................... 45 * Added "" to second paragraph of Detailed Design Procedure section ........................................................................... 47 2 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 5 Device Family Comparison DEVICE BW (MHz) IQ (mA) THD (dBc) 2 VPP AT 100 kHz INPUT NOISE (nV/Hz) RAIL-TO-RAIL THS4531A 36 0.25 -104 10 Out THS4521 145 0.95 -102 4.6 Out THS4520 620 14.2 -107 2.0 Out 6 Pin Configuration and Functions Vs- Vs- Vs- Vs- RGT Package VQFN-16 (Top View) 16 15 14 13 RUN Package WQFN-10 (Top View) Vs+ 10 OUT- 1 9 OUT+ FB- 1 12 PD NC 2 8 NC IN+ 2 11 OUT- PD 3 7 Vocm IN- 3 10 OUT+ IN+ 4 6 IN- FB+ 4 9 5 Vocm 6 7 8 Vs+ Vs+ Vs+ Vs+ Vs- 5 Pin Functions PIN NAME NO. RGT (1) RUN I/O FB+ 4 -- O Noninverted (positive) output feedback FB- 1 -- O Inverted (negative) output feedback IN+ 2 4 I Noninverting (positive) amplifier input IN- 3 6 I Inverting (negative) amplifier input NC -- 2, 8 -- No internal connection OUT+ 10 9 O Noninverted (positive) amplifier output OUT- 11 1 O Inverted (negative) amplifier output PD 12 3 I Power down. PD = logic low = power off mode; PD = logic high = normal operation. Vocm 9 7 I Common-mode voltage input Vs+ 5, 6, 7, 8 10 I Positive power-supply input Vs- 13, 14, 15, 16 5 I Negative power-supply input (1) DESCRIPTION Solder the exposed thermal pad (RGT package) to a heat-spreading power or ground plane. This pad is electrically isolated from the die, but must be connected to a power or ground plane and not floated. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 3 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 5.5 V (Vs+) + 0.5 V Supply voltage, Vs+ - Vs- Voltage Input/output voltage range Current (Vs-) - 0.5 Differential input voltage 1 V Continuous input current 20 mA 80 mA Continuous output current Continuous power dissipation Maximum junction temperature Temperature (1) See Thermal Information table and Thermal Analysis section Operating free-air temperature range -40 150 C 125 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings MIN Tstg Storage temperature range Electrostatic discharge V(ESD) (1) (2) MAX UNIT C -65 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) -2000 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) -500 500 Machine model (2) -150 150 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Vs+ Single-supply voltage 2.7 5 5.4 UNIT V TA Ambient temperature -40 25 125 C 7.4 Thermal Information THS4541 THERMAL METRIC (1) RGT (VQFN) RUN (WQFN) 16 PINS 10 PINS RJA Junction-to-ambient thermal resistance 52 146 RJC(top) Junction-to-case (top) thermal resistance 69 75 RJB Junction-to-board thermal resistance 25 39 JT Junction-to-top characterization parameter 2.7 14 JB Junction-to-board characterization parameter 25 105 RJC(bot) Junction-to-case (bottom) thermal resistance 9.3 47 (1) 4 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com 7.5 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Electrical Characteristics: Vs+ - Vs- = 5 V At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Vout = 100 mVPP, G = 1 620 MHz C Vout = 100 mVPP, G = 2 (see Figure 61) 500 MHz C Vout = 100 mVPP, G = 5 210 MHz C Vout = 100 mVPP, G = 10 125 MHz C Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz C Large-signal bandwidth Vout = 2 VPP, G = 2 (see Figure 61) 340 MHz C Bandwidth for 0.1-dB flatness Vout = 2 VPP, G = 2 (see Figure 61) 100 MHz C Slew rate (2) Vout = 2-VPP, FPBW (see Figure 61) 1500 V/s C Rise/fall time Vout = 2-V step, G = 2 input 0.3 ns tr (see Figure 63) 1.4 ns C To 1%, Vout = 2-V step, tr = 2 ns, G = 2 (seeFigure 63) 4 ns C To 0.1%,Vout = 2-V step, tr = 2 ns, G = 2 (see Figure 63) 8 ns C Small-signal bandwidth Settling time Vout = 2-V step G = 2, input 0.3 ns tr (see Figure 63) 10% Vout = 2 VPP, G = 2, HD2 (see Figure 61) -140 dBc C Vout = 2 VPP, G = 2, HD3 (see Figure 61) -140 dBc C Vout = 2 VPP, G = 2, HD2 (see Figure 61) -95 dBc C Vout = 2 VPP, G = 2, HD3 (see Figure 61) -90 dBc C 2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) (see Figure 61) -90 dBc C 3rd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) (see Figure 61) -85 dBc C Input voltage noise f > 100 kHz 2.2 nV/Hz C Input current noise f > 1 MHz 1.9 pA/Hz C Overdrive recovery time 2X output overdrive, either polarity 20 ns C Closed-loop output impedance f = 10 MHz (differential) 0.1 C Overshoot and undershoot 100-kHz harmonic distortion 10-MHz harmonic distortion (1) (2) C Test levels (all values set by characterization and simulation): (A) 100% tested at TA 25C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / 2) * 2 * f-3dB. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 5 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Electrical Characteristics: Vs+ - Vs- = 5 V (continued) At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) DC PERFORMANCE AOL Open-loop voltage gain Input-referred offset voltage Input offset voltage drift (3) Input bias current (positive out of node) Input bias current drift (3) 100 119 dB A TA = 25C -450 100 450 V A TA = 0C to 70C -600 100 600 V B TA = -40C to 85C -700 100 700 V B TA = -40C to 125C -850 100 850 V B TA = -40C to 125C -2.4 0.5 2.4 V/C B TA = 25C 4.3 10 13 A A TA = 0C to 70C 4.3 11 13.5 A B TA = -40C to 85C 4.3 12 14 A B TA = -40C to 125C 4.3 12 14.5 A B 6 15 nA/C B TA = -40C to 125C TA = 25C -500 150 500 nA A TA = 0C to 70C -550 150 550 nA B TA = -40C to 85C -580 150 580 nA B TA = -40C to 125C -620 150 620 nA B Input offset current drift (3) TA = -40C to 125C -1.3 0.3 1.3 nA/C B < 3-dB degradation in TA = 25C CMRR from TA = -40C to 125C midsupply Vs- - 0.2 Vs- - 0.1 V A Common-mode input low Vs- - 0.1 Vs- V B < 3-dB degradation in TA = +25C CMRR from TA = -40C to 125C midsupply V A Common-mode input high V B Common-mode rejection ratio Input pins at (Vs+ - Vs-) / 2 Input impedance differential mode Input pins at (Vs+ - Vs-) / 2 Input offset current INPUT Vs+ - 1.3 Vs+ -1.2 Vs+ - 1.3 85 100 110 || 0.85 dB A k || pF C OUTPUT TA = 25C Vs- + 0.2 Vs- + 0.25 V A TA = -40C to 125C Vs- + 0.2 Vs- + 0.25 V B Output voltage low TA = 25C Vs+ - 0.25 Vs+ - 0.2 V A TA = -40C to 125C Vs+ - 0.25 Vs+ - 0.2 V B TA = 25C 75 100 mA A TA = -40C to 125C 75 mA B Output voltage high Output current drive (3) 6 Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Electrical Characteristics: Vs+ - Vs- = 5 V (continued) At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) POWER SUPPLY Specified operating voltage Quiescent operating current PSRR Power-supply rejection ratio 2.7 5.0 5.4 V B TA = +25C, Vs+ = 5.0 V 9.7 10.1 10.5 mA A TA = -40C to 125C 9.4 10.1 11 mA B Either supply pin to differential Vout 85 100 dB A POWER DOWN Enable voltage threshold Vs- + 1.7 Disable voltage threshold Disable pin bias current Power-down quiescent current V A Vs- + 0.7 V A PD = Vs- Vs+ 20 50 nA B PD = Vs- + 0.7 V 6 30 A A PD = Vs- 2 8 A A Turn-on time delay Time from PD = low to Vout = 90% of final value 100 ns C Turn-off time delay Time from PD = low to Vout = 10% of final value 60 ns C OUTPUT COMMON-MODE VOLTAGE CONTROL (4) Small-signal bandwidth Vocm = 100 mVPP 150 MHz C Slew rate (5) Vocm = 2-V step 400 V/s C A Gain CM Vos Input bias current Considered positive out of node Input impedance Vocm input driven to (Vs+ - Vs-) / 2 Default voltage offset from (Vs+ - Vs-) / 2 Vocm pin open Common-mode offset voltage Vocm input driven to (Vs+ - Vs-) / 2 Common-mode offset voltage drift (6) Common-mode loop supply headroom to negative supply (4) (5) (6) < 12-mV shift from midsupply CM Vos 0.995 V/V -0.7 0.1 0.7 A A k || pF C 40 mV A 47 || 1.2 8 TA = 25C -5 2 5 mV A TA = 0C to 70C -6 2 5.8 mV B TA = -40C to 85C -6.2 2 6.2 mV B TA = -40C to 125C -7.0 2 7.08 mV B -20 4 +20 V/C B TA = 25C 0.88 V A TA = 0C to 70C 0.91 V B TA = -40C to 85C 0.94 V B TA = -40C to 125C 0.94 V B 1.1 V A 1.15 V B TA = -40C to 85C 1.2 V B TA = -40C to 125C 1.2 V B TA = 25C Common-mode loop supply headroom to positive supply 0.982 -40 Vocm input driven to (Vs+ - Vs-) / 2 < 12-mV shift from midsupply CM Vos 0.975 TA = 0C to 70C Specifications are from the input Vocm pin to the differential output average voltage. This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / 2) * 2 * f-3dB. Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 7 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 7.6 www.ti.com Electrical Characteristics: Vs+ - Vs- = 3 V At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Vout = 100 mVPP, G = 1 600 MHz C Vout = 100 mVPP, G = 2 (see Figure 61) 500 MHz C Vout = 100 mVPP, G = 5 200 MHz C Vout = 100 mVPP, G = 10 120 MHz C Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz C Large-signal bandwidth Vout = 2 VPP, G = 2 (see Figure 61) 300 MHz C Bandwidth for 0.1-dB flatness Vout = 2 VPP, G = 2 (see Figure 61) 90 MHz C Slew rate (2) Vout = 2-V step, FPBW (see Figure 61) 1300 V/s C Rise/fall time Vout = 2-V step, G = 2, input 0.3 ns tr (see Figure 63) 1.8 ns C To 1%, Vout = 2-V step, tr = 2 ns, G = 2 (see Figure 63) 5 ns C To 0.1%, Vout = 2-V step, tr = 2 ns, G = 2 (see Figure 63) 8 ns C Small-signal bandwidth Settling time Vout = 2-V step G = 2, input 0.3 ns tr (see Figure 63) 10% Vout = 2 VPP, G = 2, HD2 (see Figure 61) -140 dBc C Vout = 2 VPP, G = 2, HD3 (see Figure 61) -140 dBc C Vout = 2 VPP, G = 2, HD2 (see Figure 61) -92 dBc C Vout = 2 VPP, G = 2, HD3 (see Figure 61) -89 dBc C 2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) (see Figure 61) -89 dBc C 3rd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) (see Figure 61) -87 dBc C Input voltage noise f > 100 kHz 2.2 nV/Hz C Input current noise f > 1 MHz 1.9 pA/Hz C Overdrive recovery time 2X output overdrive, either polarity 20 ns C Closed-loop output impedance f = 10 MHz (differential) 0.1 C Overshoot and undershoot 100-kHz harmonic distortion 10-MHz harmonic distortion (1) (2) 8 C Test levels (all values set by characterization and simulation): (A) 100% tested at TA 25C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / 2) * 2 * f-3dB. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Electrical Characteristics: Vs+ - Vs- = 3 V (continued) At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) DC PERFORMANCE AOL Open-loop voltage gain Input-referred offset voltage Input offset voltage drift (3) Input bias current (positive out of node) Input bias current drift (3) 100 119 dB A TA = 25C -450 100 400 V A TA = 0C to 70C -600 100 600 V B TA = -40C to 85C -700 100 700 V B TA = -40C to 125C -850 100 850 V B TA = -40C to 125C -2.4 0.5 2.4 V/C B TA = 25C 4.1 9 12 A A TA = 0C to 70C 4.1 9 12.5 A B TA = -40C to 85C 4.1 9 13 A B TA = -40C to 125C 4.1 9 13.5 A B -5 15 nA/C B TA = -40C to 125C TA = 25C -500 150 500 nA A TA = 0C to 70C -550 150 550 nA B TA = -40C to 85C -580 150 580 nA B TA = -40C to 125C -620 150 620 nA B Input offset current drift (3) TA = -40C to 125C -1.3 0.3 1.3 nA/C B < 3-dB degradation in TA = 25C CMRR from TA = -40C to 125C midsupply Vs- - 0.2 Vs- - 0.1 V A Common-mode input low Vs- - 0.1 Vs- V B < 3-dB degradation in TA = +25C CMRR from TA = -40C to 125C midsupply V A Common-mode input high V B Common-mode rejection ratio Input pins at (Vs+ - Vs-) / 2 Input impedance differential mode Input pins at (Vs+ - Vs-) / 2 Input offset current INPUT Vs+ - 1.3 Vs+ -1.2 Vs+ - 1.3 85 100 110 || 0.85 dB A k || pF C OUTPUT TA = 25C Vs- + 0.2 Vs- + 0.25 V A TA = -40C to 125C Vs- + 0.2 Vs- + 0.25 V B Output voltage low TA = 25C Vs+ - 0.25 Vs+ - 0.2 V A TA = -40C to 125C Vs+ - 0.25 Vs+ - 0.2 V B TA = 25C 55 60 mA A TA = -40C to 125C 55 mA B Output voltage high Output current drive (3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 9 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Electrical Characteristics: Vs+ - Vs- = 3 V (continued) At TA 25C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 , Rload = 499 , 50- input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a 2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) POWER SUPPLY Specified operating voltage Quiescent operating current PSRR Power-supply rejection ratio 2.7 3.0 5.4 V B TA = +25C, Vs+ = 3.0 V 9.3 9.7 10.1 mA A TA = -40C to 125C 9.0 9.7 10.6 mA B Either supply pin to differential Vout 85 100 dB A POWER DOWN Enable voltage threshold Vs- + 1.7 Disable voltage threshold V A Vs- + 0.7 V A PD = Vs- Vs+ 20 50 nA B PD = Vs- + 0.7 V 2 30 A A PD = Vs- 1.0 8.0 A A Turn-on time delay Time from PD = low to Vout = 90% of final value 100 ns C Turn-off time delay Time from PD = low to Vout = 10% of final value 60 ns C Disable pin bias current Power-down quiescent current OUTPUT COMMON-MODE VOLTAGE CONTROL (4) Small-signal bandwidth Vocm = 100 mVPP 140 MHz C Slew rate (5) Vocm = 1-V step 350 V/s C A Gain Input bias current Considered positive out of node Input impedance Vocm input driven to (Vs+ - Vs-) / 2 Default voltage offset from (Vs+ - Vs-) / 2 Vocm pin open Common-mode offset voltage Vocm input driven to (Vs+ - Vs-) / 2 TA = 25C CM Vos Common-mode offset voltage drift (6) Common-mode loop supply headroom to negative supply (4) (5) (6) 10 < 12-mV shift from midsupply CM Vos 0.990 V/V -0.7 0.1 0.7 A A k || pF C 40 mV A 47 || 1.2 -40 10 -5 2 5 mV A -5.8 2 5.8 mV B TA = -40C to 85C -6.2 2 6.2 mV B TA = -40C to 125C -7.0 2 7.0 mV B -20 4 20 V/C B TA = 25C 0.88 V A TA = 0C to 70C 0.91 V B TA = -40C to 85C 0.94 V B TA = -40C to 125C 0.94 V B 1.1 V A 1.15 V B TA = -40C to 85C 1.2 V B TA = -40C to 125C 1.2 V B TA = 25C Common-mode loop supply headroom to positive supply 0.987 TA = 0C to 70C Vocm input driven to (Vs+ - Vs-) / 2 < 12-mV shift from midsupply CM Vos 0.975 TA = 0C to 70C Specifications are from input Vocm pin to differential output average voltage. This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / 2) * 2 * f-3dB. Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 7.7 Typical Characteristics: 5-V Single Supply At Vs+ = 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 9 9 G=0.1 G=1 G=2 G=5 G=10 3 6 3 Gain (dB) Normalized Gain (dB) 6 0 -3 0 -3 Vo=100 mVpp Vo=500 mVpp Vo=1 Vpp Vo=2 Vpp Vo=5 Vpp -6 -6 -9 -9 1 10 100 Frequency (MHz) -12 10 1000 100 Frequency (MHz) D001 Rf = 402 , see Figure 61 and Table 6 for resistor values Figure 1. Small-Signal Frequency Response vs Gain Figure 2. Frequency Response vs Vopp 9 Vocm=1.0 V Vocm=1.5 V Vocm=2.0 V Vocm=2.5 V Vocm=3.0 V Vocm=3.5 V 8 7 6 6 5 5 4 4 3 10 RL=50 : RL=100 : RL=200 : RL=500 : RL=1000 : 8 Gain (dB) 7 Gain (dB) D002 See Figure 61 9 100 Frequency (MHz) 3 10 1000 D003 Vout = 100 mVPP , see Figure 61 with Vocm adjusted 100 Frequency (MHz) 1000 D004 Vout = 100 mVPP, see Figure 61 with RL adjusted Figure 3. Small-Signal Frequency Response vs Vocm Figure 4. Small-Signal Frequency Response vs Rload (RL) 9 40 Cload=10 pF, Ro = 24.9 : Cload=22 pF, Ro = 16 : Cload=51 pF, Ro = 9.1 : Cload=100 pF, Ro = 5.4 : 8 Av=2 Av=4 Av=10 35 30 7 25 Ro (:) Normalized Gain (dB) 1000 6 20 15 5 10 4 5 3 10 0 100 Frequency (MHz) 1000 1 D005 100 mVPP at load, Av = 2 (see Figure 71), two series Ro added at output before Cload 10 Cload (pF) 100 D006 Ro is two series output resistors to a differential Cload in parallel with 500 , see Figure 71 and Table 6 Figure 5. Small-Signal Frequency Response vs Cload Figure 6. Recommended Ro vs Cload Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 11 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics: 5-V Single Supply (continued) At Vs+ = 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 2.5 0.5 Differential Output (V) 1.5 Differential Output Voltage (V) 4 Vpp 2 Vpp 0.5 Vpp 2 1 0.5 0 -0.5 -1 -1.5 Ro=17 : Ro=0 : 0.4 0.3 0.2 0.1 -2 -2.5 0 6 8 10 12 14 16 18 20 Time (ns) 22 24 26 28 30 8 50-MHz input, 0.3-ns input edge rate, single-ended to differential output, dc coupled, see Figure 63 16 18 Time (ns) 20 22 24 D008 0.5 4 Vpp 2 Vpp 0.5 Vpp 1.5 Ro=0 : Ro=7.5 : 0.45 Differential Output Voltage (V) 2 Differential Output Voltage (V) 14 Figure 8. Step Response into Capacitive Load 2.5 1 0.5 0 -0.5 -1 -1.5 -2 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 -2.5 0 6 8 10 12 14 16 18 20 Time (ns) 22 24 26 28 30 8 10 12 14 D009 G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, see Figure 63 16 18 Time (ns) 20 22 24 D010 G = 5 V/V, 500-mVPP output into 22-pF Cload, see Figure 71 and Table 6 Figure 9. Small- and Large-Signal Step Response Figure 10. Step Response into Capacitive Load 0.2 Input and Differential Output Voltage (V) 15 0.5 V step 2 V step 0.15 Error to Final Value (%) 12 Av = 2 , 500-mVPP output into 22-pF Cload, see Figure 71 Figure 7. Small- and Large-Signal Step Response 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 Output Input 10 5 0 -5 -10 -15 0 5 10 15 Time ' from 50% of Input Edge (ns) 20 0 20 Figure 11. Small- and Large-Signal Step Settling Time 40 60 80 Time (ns) D011 Simulated with 2-ns input transition time, see Figure 63 12 10 D007 100 D012 Single-ended to differential gain of 2 (see Figure 63), 2X input overdrive Figure 12. Overdrive Recovery Performance Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Typical Characteristics: 5-V Single Supply (continued) At Vs+ = 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). -50 -70 HD2 HD3 -60 -80 -70 -80 Distortion (dBc) Distortion (dBc) HD2 HD3 -75 -90 -100 -110 -85 -90 -95 -100 -105 -120 -110 -130 -115 -140 0.1 1 Frequency (MHz) 10 -120 0.1 50 D013 2-VPP output, see Figure 61 Figure 13. Harmonic Distortion Over Frequency D014 Figure 14. Harmonic Distortion vs Output Swing -70 Avg IMD3 Avg IMD2 HD2 HD3 -75 -80 Distortion (dBc) Spurious Level (dBc) 10 10 MHz, see Figure 61 -60 -70 1 Differential Output Voltage (Vpp) -90 -100 -110 -80 -85 -90 -120 -95 -130 -140 0.1 1 10 Center of Two Input Test Frequencies (MHz) -100 10 50 D015 1 VPP each tone, see Figure 61 100 Differential Load Resistance (:) 1000 D016 f = 10 MHz, see Figure 61 with Rload adjusted Figure 15. IMD2 and IM3 Over Frequency Figure 16. Harmonic Distortion vs Rload -70 -80 HD2 HD3 HD2 HD3 -75 Distortion (dBc) Distortion (dBc) -85 -90 -80 -85 -90 -95 -95 -100 0.5 -100 1 1.5 2 2.5 3 Vocm Control Voltage (V) 3.5 4 1 f = 10 MHz, 2-VPP output, see Figure 63 with Vocm adjusted 10 Gain (V/V) D017 D018 10 MHz, 2-VPP output, see Figure 61 and Table 6 for gain setting Figure 17. Harmonic Distortion vs Vocm Figure 18. Harmonic Distortion vs Gain Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 13 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 7.8 Typical Characteristics: 3-V Single Supply At Vs+ = 3 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 9 9 G=0.1 G=1 G=2 G=5 G=10 3 6 3 Gain (dB) Normalized Gain (dB) 6 0 -3 0 -3 -6 -6 -9 -9 -12 1 10 100 Frequency (MHz) Vo=100 mVpp Vo=500 mVpp Vo=1 Vpp Vo=2 Vpp Vo=5 Vpp -12 10 1000 Rf = 402 , Vout = 100 mVPP, see Figure 61 and Table 6 for resistor values 9 Vocm=1.0 V Vocm=1.5 V Vocm=1.8 V 8 RL=50 : RL=100 : RL=200 : RL=500 : RL=1000 : 8 7 7 Gain (dB) Gain (dB) D020 Figure 20. Frequency Response vs Vopp 9 6 6 5 5 4 4 3 10 100 Frequency (MHz) 3 10 1000 D021 Vout = 100 mVPP, see Figure 61 with Vocm adjusted Figure 21. Small-Signal Frequency response vs Vocm 8 100 Frequency (MHz) 1000 D022 Vout = 100 mVPP, see Figure 61 with the Rload adjusted Figure 22. Small-Signal Frequency Response vs Rload (RL) 9 40 Cload=10 pF, Ro=27 : Cload=22 pF, Ro=18 : Cload=51 pF, Ro=10 : Cload=100 pF, Ro=5.4 : Av=2 Av=4 Av=10 35 30 7 25 Ro (:) Normalized Gain (dB) 1000 See Figure 61 with VCC = 3 V and Vocm = 1.5 V Figure 19. Small-Signal Frequency Response vs Gain 6 20 15 5 10 4 3 10 5 0 100 Frequency (MHz) 1000 1 D023 100 mVPP at load, Av = 2 (see Figure 71), two series Ro added at output before Cload 10 Differential Cload (pF) 100 D024 Two Ro at output to differential Cload in parallel with 500 , see Figure 71 and Table 6 Figure 23. Small-Signal Frequency Response vs Cload 14 100 Frequency (MHz) D019 Submit Documentation Feedback Figure 24. Recommended Ro vs Cload Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Typical Characteristics: 3-V Single Supply (continued) At Vs+ = 3 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 3 0.5 Differential Output Voltage (V) 2 Differential Output Voltage (V) 4 Vpp 2 Vpp 0.5 Vpp 2.5 1.5 1 0.5 0 -0.5 -1 -1.5 -2 Ro=13.7 : Ro=0 : 0.4 0.3 0.2 0.1 -2.5 -3 0 6 8 10 12 14 16 18 20 Time (ns) 22 24 26 28 30 8 50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, dc coupled, see Figure 63 Figure 25. Small- and Large-Signal Step Response 14 16 18 Time (ns) 20 22 24 D026 Figure 26. Step Response into Capacitive Load 0.5 4 Vpp 2 Vpp 0.5 Vpp 1.5 Ro=7.5 : Ro=0 : 0.45 Differential Output Voltage (V) 2 Differential Output Voltage (V) 12 500-mVPP output into 22-pF Cload, see Figure 71 with Vs+ = 3 V and Vocm = 1.5 V 2.5 1 0.5 0 -0.5 -1 -1.5 -2 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 -2.5 0 6 8 10 12 14 16 18 20 Time (ns) 22 24 26 28 30 8 10 12 14 D027 G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, see Figure 61 16 18 Time (ns) 20 22 24 D028 G = 5 V/V, 500-mVpp output into 22-pF Cload, see Figure 71 and Table 6 Figure 27. Small- and Large-Signal Step Response Figure 28. Step Response into Capacitive Load 6 Input and Differential Output Voltage (V) 0.2 0.5 V step 2 V step 0.15 Error to Final Value (%) 10 D025 0.1 0.05 0 -0.05 -0.1 -0.15 Output Input 4 2 0 -2 -4 -6 -0.2 0 5 10 15 Time ' from 50% of Input Edge (ns) 20 0 20 Simulated with 2-ns input transition time, see Figure 63 Figure 29. Small- and Large-Signal Step Settling Time 40 60 80 100 Time (ns) D029 D030 Single-ended to differential gain of 2 (see Figure 63), > 2X input overdrive Figure 30. Overdrive Recovery Performance Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 15 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics: 3-V Single Supply (continued) At Vs+ = 3 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). -70 -50 HD2 HD3 -60 -80 -70 -80 Distortion (dBc) Distortion (dBc) HD2 HD3 -75 -90 -100 -110 -85 -90 -95 -100 -105 -120 -110 -130 -115 -140 0.1 1 Frequency (kHz) 10 -120 0.1 50 D031 2-VPP output, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V Figure 31. Harmonic Distortion Over Frequency Figure 32. Harmonic Distortion vs Output Swing Avg IMD3 Avg IMD2 HD2 HD3 -75 -80 Distortion (dBc) Spurious Level (dBc) D032 -70 -90 -100 -110 -80 -85 -90 -120 -95 -130 -140 0.1 1 10 Center of Two Input Test Frequencies (MHz) -100 10 50 D033 1 VPP each tone, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V 100 Differential Load Resistance (:) 1000 D034 f = 10 MHz, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V Figure 33. IMD2 and IM3 Over Frequency Figure 34. Harmonic Distortion vs Rload -80 -70 HD2 HD3 HD2 HD3 -75 -85 -80 Distortion (dBc) Distortion (dBc) 10 f = 10 MHz, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V -60 -70 1 Differential Output Voltage (Vpp) -90 -85 -90 -95 -95 -100 -100 0.5 -105 1 1.5 2 Vocm Control Voltage (V) 2.5 1 f = 10 MHz, 2-VPP output, see Figure 63 with Vocm adjusted D036 f = 10 MHz, 2-VPP output, see Figure 61 and Table 6 for gain setting Figure 35. Harmonic Distortion vs Vocm 16 10 Gain (V/V) D035 Submit Documentation Feedback Figure 36. Harmonic Distortion vs Gain Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 7.9 Typical Characteristics: 3-V to 5-V Supply Range At Vs+ = 3 V and 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 10 0 100 -50 70 -100 40 -150 10 -200 -20 100 1k 10k 100k 1M Frequency (Hz) 10M Open Loop Phase (deg) Open Loop Gain (dB) Aol Gain Aol Phase -250 1G 100M Differential Output Impedance (:) 130 Gain=2, +3 V Gain=2, +5 V Gain=5, +3 V Gain=5, +5 V 1 0.1 0.01 0.001 0.0001 1k 10k D037 100k 1M Frequency (Hz) 10M 100M D038 Single-ended input to differential output, simulated differential output impedance, (closed-loop) gain of 2 and 5, see Figure 61 Figure 38. Closed-Loop Output Impedance Figure 37. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency -50 +5 V En +5 V In +3 V En +3 V In -55 Output Balance Error (dB) Input Spot Voltage (nV/Hz) and Current (pA/Hz) Noise 50 10 +3 V supply +5 V supply -60 -65 -70 -75 1 1k 10k 100k Frequency (Hz) 1M -80 1k 10M 10k D039 100k 1M Frequency (Hz) 10M 100M D040 Single-ended input to differential output, gain of 2 (see Figure 61), simulated with 1% resistor, worst-case mismatch Figure 40. Output Balance Error Over Frequency Figure 39. Input Spot Noise Over Frequency 110 90 +3 V +Vs +5 V +Vs +3 V -Vs +5 V -Vs 85 100 80 75 PSRR (dB) CMRR (dB) 90 80 70 70 65 60 55 50 60 45 50 1k 10k 100k 1M Frequency (Hz) 10M 40 10k 100M D041 Common-mode in to differential out, gain of 2 simulation 100k 1M 10M Frequency (Hz) 100M D042 Single-ended to differential, gain of 2 (see Figure 61) PSRR simulated to differential output Figure 41. CMRR Over Frequency Figure 42. PSRR Over Frequency Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 17 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics: 3-V to 5-V Supply Range (continued) At Vs+ = 3 V and 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 1 3 0 Output Common Mode Voltage (V) +5 V, 100 mVpp +5 V, 1 Vpp +3 V, 100 mVpp +3 V, 1 Vpp 0.5 Gain (dB) -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 1 10 100 Frequency (MHz) 5 V Large Signal 2.5 2.25 5 V Small Signal 2 1.75 3 V Large Signal 1.5 1.25 3 V Small Signal 1 25 1000 35 55 65 Time (ns) 75 85 95 D044 Figure 44. Common-Mode, Small- and Large-Step Response (Vocm pin driven) 1000 10 +5 V Vocm driven +5 V Vocm floating +3 V Vocm driven +3 V Vocm floating +5 V supply +3 V supply Output CM Voltage Offset (mV) 8 100 10 6 4 2 0 -2 -4 -6 -8 1 100 1k 10k 100k Frequency (Hz) 1M -10 0.8 10M 1.2 D045 Vocm input either driven to midsupply by low impedance source, or allowed to float and default to midsupply 1.6 2 2.4 2.8 3.2 Vocm Input Voltage (V) 3.6 4 D046 Average Vocm output offset of 37 units, Standard deviation < 2.5 mV, see Figure 63 Figure 45. Output Common-Mode Noise Figure 46. Vocm Offset vs Vocm Setting 100 100 +3 V supply +5 V supply 95 Positive Supply PSRR (dB) Negative Supply PSRR (dB) 45 D043 Figure 43. Common-Mode, Small- and Large-Signal Response (Vocm pin driven) Output Spot Common Mode Noise (nV/Hz) 2.75 90 85 80 95 90 85 80 75 75 +3 V supply +5 V supply 70 0.85 1.35 1.85 2.35 2.85 Vocm (V) 3.35 70 0.85 3.85 Single-ended to differential gain of 2 (see Figure 61), PSRR for negative supply to differential output (1-kHz simulation) Figure 47. -PSRR vs Vocm Approaching Vs- 18 1.35 D047 1.85 2.35 2.85 Vocm (V) 3.35 3.85 D048 Single-ended to differential gain of 2 (see Figure 61), PSRR for positive supply to differential output (1-kHz simulation) Figure 48. +PSRR vs Vocm Approaching Vs+ Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Typical Characteristics: 3-V to 5-V Supply Range (continued) At Vs+ = 3 V and 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 600 900 +5 V supply +3 V supply # of Units in 50 nA Bins # of Units in 50 PV Bins 500 +5 V supply +3 V supply 800 400 300 200 700 600 500 400 300 200 100 100 0 -500 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 400 450 500 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 400 450 0 D049 3 lots, total of 2962 units trimmed at 5-V supply 3 lots, total of 2962 units Figure 50. Input Offset Current 100 250 75 200 150 50 Ios ' from 25C (nA) Delta from 25C Vio (V) Figure 49. Input Offset Voltage 25 0 -25 -50 100 50 0 -50 -100 -150 -75 -200 -100 -50 -25 0 25 50 75 Ambient Temperature (C) 100 -250 -50 125 -25 D051 5-V and 3-V delta from 25C VIO, 25 units 0 25 50 75 Ambient Temperature (C) 100 125 D052 5-V and 3-V over temperature IOS, 25 units Figure 51. Input Offset Voltage Over Temperature Figure 52. Input Offset Current Over Temperature 14 12 +5 V supply +3 V supply 12 # of Units in Each 0.1 nA/C Bin # of Units in Each 0.2 V/qC Bin D050 Input Offset Current (nA) Input Offset Voltage (PV) 10 8 6 4 2 0 +5 V supply +3 V supply 10 8 6 4 2 -1.3 -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 -2.4 -2.2 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 D053 D054 Offset Drift (V/qC) Offset Current Drift (nA/C) -40C to 125C endpoint drift, 3 lots, total of 68 units -40C to 125C endpoint drift, 3 lots, total of 68 units Figure 53. Input Offset Voltage Drift Figure 54. Input Offset Current Drift Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 19 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Characteristics: 3-V to 5-V Supply Range (continued) At Vs+ = 3 V and 5 V, Vs- = GND, Vocm is open, 50- single-ended input to differential output, gain = 2 V/V, Rload = 500 , and TA 25C (unless otherwise noted). 10 11 5 V supply 3 V supply 9 5 V supply 3 V supply 10.5 Supply Current (mA) Differential Vopp (V) 8 7 6 5 4 3 10 9.5 9 8.5 8 2 7.5 1 0 10 7 100 Differential Load (:) 1000 0 D055 1 2 3 Disable Pin Voltage (PD) Volts 4 5 D056 Maximum differential output swing, Vocm at midsupply Figure 55. Maximum Vopp vs Rload Figure 56. Supply Current vs PD Voltage 1400 600 5 V data 3 V data # of Units in 0.5 mV Bins 800 600 400 400 300 200 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 40 35 30 25 20 15 5 10 0 -5 -10 -15 -20 0 -25 0 -30 100 -35 200 Vocm Offset Voltage (mV) 5 V data 3 V data 500 1000 -40 # of Units in 5 mV Bins 1200 D057 D058 Vocm Offset Voltage (mV) Vocm input floating, 3 lots, total of 2962 units Input driven midsupply, 3 lots, total of 2962 units Figure 58. Common-Mode Output Offset from Driven Vocm 5 4 Disable and Differential Output Voltage (V) Disable and Differential Output Voltage (V) Figure 57. Common-Mode Output Offset from Vs+ / 2 Default Value PD 3 V PD 5 V 3 3-V Supply 2 5-V Supply 1 0 -1 -2 0.04 0.06 0.08 0.1 0.12 Time (s) 0.14 0.16 0.18 5 3 2 1 0 -1 -2 0.28 D059 10 MHz, 1-Vpp input single to differential gain of 2, see Figure 63 0.3 0.32 Time (s) 0.34 0.36 D060 10 MHz, 1-VPP input single to differential gain of 2, see Figure 63 Figure 59. PD Turn On Waveform 20 PD 3 V Out 3 V Out 5 V PD 5 V 4 Submit Documentation Feedback Figure 60. PD Turn Off Waveform Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 8 Parameter Measurement Information 8.1 Example Characterization Circuits The THS4541 offers the advantages of a fully differential amplifier (FDA) design, with the trimmed input offset voltage of a precision op amp. The FDA is an extremely flexible device that provides a purely differential output signal centered on a settable output common-mode level. The primary options revolve around the choices of single-ended or differential inputs, ac-coupled or dc-coupled signal paths, gain targets, and resistor-value selections. The characterizations shown in Figure 1 to Figure 36 focus on single-ended-to-differential designs as the more challenging application requirement. Differential sources can certainly be supported and are often simpler to both implement and analyze. Because most lab equipment is single-ended, the characterization circuits typically operate with a single-ended, matched, 50- input termination to a differential output at the FDA output pins. That output is then translated back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range. DC-coupled, step-response testing uses two 50- scope inputs with trace math. The starting point for any singleended-to-differential, ac-coupled characterization plot is shown in Figure 61. THS4541 Wideband, Fully-Differential Amplifier 50- Input Match, Gain of 2 V/V from Rt, Single-Ended Source to Differential Output C1 100 nF 50- Source Rf1 402 Vcc Rg1 191 Rt 60.2 Vocm FDA + PD Rg2 221 C2 100 nF Output Rload Measurement 500 Point + Vcc Rf2 402 Figure 61. AC-Coupled, Single-Ended Source to a Differential Gain of a 2-V/V Test Circuit Most characterization plots fix the Rf (Rf1 = Rf2) value at 402 , as shown in Figure 61. This element value is completely flexible in application, but the 402 provides a good compromise for the parasitic issues linked to this value, specifically: * Added output loading. The FDA appears like an inverting op amp design with both feedback resistors as an added load across the outputs (approximate total differential load in Figure 61 is 500 || 804 = 308 ). * Noise contributions because of the resistor values. The resistors contribute both a 4kTR term and provide gain for the input current noise (see the Noise Analysis section). * Parasitic feedback pole at the input summing nodes. This pole created by the feedback R value and the 0.85-pF differential input capacitance (as well as any board layout parasitic) introduces a zero in the noise gain, decreasing the phase margin in most situations. This effect must be managed for best frequency response flatness or step response overshoot. The 402- value selected does degrade the phase margin slightly over a lower value, but does not decrease the loading significantly from the nominal 500- value across the output pins. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 21 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Example Characterization Circuits (continued) The frequency domain characterization curves start with the selections of Figure 61. Then, various elements are modified to show their impact over a range of design targets, specifically: * Gain setting is changed by adjusting Rt and the 2 - Rg elements (holding a 50- input match). * Output loading, including both resistive and capacitive load testing. * Power-supply settings. Most often, a single +5-V test uses a 2.5-V supply, and a +3-V test uses 1.5-V supplies. * The disable control pin is tied to Vs+ for any active channel test. Because most network and spectrum analyzers are a single-ended input, the output network on the THS4541 characterization tests typically show the desired load connected through a balun to a single-ended, 50- load, while presenting a 50- source from the balun output back into the balun. For instance, Figure 62 shows a wideband MA/Com balun used for Figure 61. This network shows a 500- differential load to the THS4541, but an ac-coupled, 50- source to the network analyzer. Distortion testing typically uses a lower-frequency, dcisolated balun (such as the TT1-6T) that is rotated 90 from the wider band interface of Figure 62. Ro1 237 C10 100 nF ETC1-1-13 50- Load THS4541 Output N1 500- Differential Ro2 Load 237 R9 56.2 N2 C9 100 nF Figure 62. Example 500- Load to a Single-Ended, Doubly-Terminated, AC-Coupled, 50- Interface This approach allows a higher differential load, but with a wideband 50- output match at the cost of considerable signal-path insertion loss. This loss is acceptable for characterization, and is normalized out to show the characterization curves. For time-domain or dc-coupled testing, the circuit of Figure 63 is used as a starting point, where the gain of a 5-V/V setting used in Figure 9 and Figure 27 are illustrated. THS4541 Wideband, Fully-Differential Amplifier 50- Input Match, Gain of 5 V/V from Rt, Single-Ended Source to Differential Step-Response Test 50Source Rf1 402 Vcc Rg1 68.1 Rt 80.6 Vocm FDA + R1 500 + Output Measurement Point PD Rg2 100 Vcc Rf2 402 Figure 63. DC-Coupled, Single-Ended-to-Differential, Basic Test Circuit Set for a Gain of 5 V/V 22 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Example Characterization Circuits (continued) In this case, the input is dc-coupled, showing a 50- input match to the source, gain of 5 V/V to a differential output, again driving a nominal 500- load. Using a single supply, the Vocm control input can either be floated (defaulting to midsupply) or be driven within the allowed range for the Vocm loop (see the headroom limits on Vocm in the Electrical Characteristics tables). To use this circuit for step-response measurements, load each of the two outputs with a 250- network, translating to a 50- source impedance driving into two 50- scope inputs. Then, difference the scope inputs to generate the step responses of Figure 9 and Figure 27. Figure 64 shows the output interface circuit. This grounded interface pulls a dc load current from the output Vocm voltage for single-supply operation. Running this test with balanced bipolar power supplies eliminates this dc load current and gives similar waveform results. Ro1 221 50Scope Rm1 64.9 THS4541 Output Ro2 221 Rm1 64.9 50Scope Figure 64. Example 500- Load to Differential, Doubly-Terminated, DC-Coupled 50- Scope Interface 8.2 Frequency-Response Shape Factors Figure 1 illustrates the small-signal response shape versus gain using a fixed 402- feedback resistor in the circuit of Figure 61. Being a voltage-feedback based FDA, the THS4541 shows a response shape that varies with gain setting, largely determined by the loop-gain crossover frequency and phase margin at the crossover. This loop-gain crossover frequency is where the open-loop response and the noise gain intersect (where the loop gain drops to 1). The noise gain is the inverse of the voltage divider from the outputs back to the differential inputs; use a balanced divider ratio on each feedback path. In general, the noise gain (NG) does not equal the signal gain for designs providing an input match from a source impedance. NG is given by 1 + Rf / (total impedance from the inverting summing junction to ground). Using the resistor values computed in the gain sweep of Table 6, and repeating that sweep showing the NG gives Table 1, where only the exact R solutions are shown. Table 1. Resistor Values and Noise Gain for Swept Gain with Rf = 402 (1) SIGNAL GAIN Rt, EXACT () Rg1, EXACT () Rg2, EXACT () NOISE GAIN 1 55.2 399 425 1.94 2 60.1 191 218 2.85 3 65.6 124 153 3.63 4 72.0 89.7 119 4.37 5 79.7 67.8 98.3 5.09 6 89.1 54.2 86.5 5.65 7 101 43.2 76.6 6.25 8 117 35.2 70.1 6.74 9 138 29.0 65.8 7.11 10 170 23.6 62.5 7.44 11 220 18.7 59.3 7.78 12 313 14.6 57.7 7.97 13 545 10.8 56.6 8.11 14 2209 7.26 56.1 8.16 (1) Rf = 402 , Rs = 50 , and AvMAX = 14.32 V/V. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 23 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com NG is critically important for bandwidth and all output error terms (such as dc offset and noise). For lower-speed devices, normally only the dc noise gain is considered. However, for the THS4541, with loop gain crossover at greater than 300 MHz, the feedback network produces a parasitic pole to the differential summing junctions that causes the noise gain to increase with frequency. This pole causes a lower crossover frequency than might be expected with added phase shift around the loop. Consider the feedback network (single-ended) of Figure 65, showing a parasitic 0.2 pF on the feedback 402- resistor. The 0.85-pF differential input capacitance of the THS4541 is converted to single-ended as a 1.7-pF parasitic for this single-sided analysis circuit (the Rg shown is Rg2 in Figure 61). Cf 200 fF Vin Rf 402 Vout + Rg 221 FDA Output Pin Cin 1.7 pF Figure 65. Feedback Network for the Gain of 2 Configuration Using 402 and Matching to a 50- Source The response shape from Vout to Vin in Figure 65 has a pole and then a zero. To describe NG, invert the Laplace transform of Vin and Vout from Figure 65 to provide the frequency-dependent NG response of Equation 1, where a zero comes in first and then a pole. Rf 1 Rg s Rf Cf Cin Cin * NG 1 1 Cf (c) s Rf Cf (1) The zero location is key. Using the gain of 2 values of Figure 65, the estimated zero in the NG is 588 MHz. Limiting the parasitic capacitance at the summing junctions, either differentially or signal-ended, to a ground or power plane is critical in board layouts. Using this feedback model, and the open-loop gain and phase data for the THS4541, allows the Aol and NG curves over frequency to be drawn, as shown in Figure 66, where the peaking in the noise gain pulls the intersection point back in frequency. 40 Aol Gain Gain = 0.1 Gain = 1 Gain = 2 35 Gain (dB) 30 25 20 15 10 5 0 10M 100M Frequency (Hz) 1G D062 Figure 66. Aol and Noise Gain Plots for the Lower Gains of Figure 61 24 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 To assess closed-loop bandwidth and peaking, the noise-gain phase must be subtracted from the THS4541 Aol phase to obtain the total phase around the loop, as shown in Figure 67. -90 -100 Phase (deg) -110 -120 -130 -140 -150 Aol Phase Gain = 0.1 Gain = 1 Gain = 2 -160 -170 -180 10M 100M Frequency (Hz) 1G D063 Figure 67. Loop-Gain Phase for the Three Lower Gains of Figure 1 From Figure 66 and Figure 67, using Table 2, tabulate the loop-gain crossover frequency and phase margin at these crossovers to explain the response shapes of Figure 1. Table 2. Estimated Crossover Frequency and Phase Margin for Gains of 0.1, 1, and 2 in Figure 1 GAIN DC NG (V/V) 0-dB LG (MHz) PHASE MARGIN () 0.1 1.1 457 18 1 1.94 380 41 2 2.85 302 59 From these crossover (or 0-dB loop gain) frequencies, a good approximation for the resulting f-3dB is to multiply the crossover frequencies by 1.6 when the phase margin is less than 65. Ideally, a 65 phase margin at loopgain crossover provides a flat Butterworth closed-loop response. The 59 phase margin for the gain of 2 setting explains the nearly flat response for this condition with 1.6 x 302 MHz = 483 MHz, estimated with f-3dB closely matching the measured 500-MHz SSBW. The very low phase margin in the attenuator setting at 0.1 V/V explains the highly peaked response in Figure 1. This peaking can be easily compensated, as shown in the Designing Attenuators section, using feedback capacitors and a differential capacitor across the inputs. Considering the noise gain zero as part of the loop-gain analysis shows the importance of using relatively-low, feedback-resistor values and minimizing layout parasitic capacitance on the input pins of the THS4541 to reduce the effects of this feedback pole. The TINA model does a good job of predicting these issues (the model includes the 0.85-pF differential internal capacitance); add any estimated external parasitic capacitance on the summing junctions in simulation to predict the response shape more accurately. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 25 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 8.3 I/O Headroom Considerations The starting point for most designs is usually to assign an output common-mode voltage. For ac-coupled signal paths, this voltage is often the default midsupply voltage, in order to retain the most available output swing around the centered Vocm. For dc-coupled designs, set this voltage with consideration for the required minimum headroom to the supplies shown in the specifications for the Vocm control. From the target output Vocm, the next step is to verify that the desired output differential VPP stays within the supplies. For any desired differential Vopp, check that the absolute maximum output pin swings with Equation 2 and Equation 3, and confirm they are within the supply rails for this rail-to-rail (RR) output device. Vopp Vomin Vocm 4 (2) Vopp Vomax Vocm (3) 4 For instance, driving the ADC3223 with its 0.95 Vcm control using a single 3.3-V supply, the maximum output swing is set by the negative-going signal from 0.95 Vcm to +0.2 V above ground. This 0.75-V, single-sided swing becomes an available 4 x 0.75 V = 3 VPP differential around the nominal 0.95 Vcm output common mode. On the high side, the maximum output is 0.95 + 0.75 = 1.7 V. This result is well within the allowed maximum of 3.3 V - 0.2 V = 3.1 V. This 3 VPP is also well beyond the maximum required 2-VPP full-scale differential input for this ADC. However, having this extra swing range is useful if an interstage filter to the ADC adds insertion loss. With the output headrooms confirmed, the input junctions must also stay within their operating range. The input range extends to the negative supply voltage (over the full temperature range); therefore, input range limitations usually appear only approaching the positive supply, where a maximum 1.3-V headroom is required over the full temperature range. The input pins operate at voltages set by the external circuit design, the required output Vocm, and the input signal characteristics. For differential-to-differential designs where the input Vicm voltage does not move with the input signal, there are two configurations to consider: * AC-coupled, differential-input designs have a Vicm equal to the output Vocm. The input Vicm requires approximately a 1.3-V headroom to the positive supply; therefore, the maximum Vocm to that value reduces from the Vocm positive headroom requirement of 1.2 V to the 1.3 V required on the input pins. The lower limit on the output Vocm is approximately 0.95 V to the negative supply over the full temperature range, and well within the 0-V minimum headroom on the input Vicm. * DC-coupled, differential-input designs, check the voltage divider from the source Vcm to the THS4541 Vocm setting to confirm the resulting voltage divider solves to an input Vicm within the allowed range. If the source Vcm can vary over some voltage range, this result must be validated over that range. For single-ended input to differential output designs, there is a dc Vicm voltage set by the external configuration with a small-signal related swing around that. The two conditions to consider are: * AC-coupled, single-ended input to differential designs place an average input Vicm equal to the output Vocm voltage with an ac-coupled swing around that Vocm following the input voltage. * DC-coupled, single-ended input to differential designs get a nominal input Vicm set by the source-signal common mode and the output Vocm setting with a small, signal-related swing around the dc Vicm level set by the voltage divider. 26 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 I/O Headroom Considerations (continued) One method of deriving the voltage range for Vicm for any single-ended input to differential output design is to determine the voltage swing on the nonsignal-input side of the FDA outputs and simply take its divider back to the input pin to ground or the dc reference used on that side. An example analysis is shown in Figure 68, where the circuit of Figure 61 is simplified to show just a Thevenized source impedance. Vocm + Rth 27.3 Vcc Vcm 2.5 V + Vs1 5V + C1 100 nF Rf1 402 Rg1 191 Vcc Vs THS4541 Vocm FDA + C2 100 nF + PD Rg2 221 Vcc Rf2 402 Figure 68. Input Swing Analysis Circuit from Figure 61 with Thevenized Source For this ac-coupled input analysis, the nominal dc input Vicm is simply the output Vocm (2.5 V in this example design). Then, considering the lower side of the feedback networks, any desired maximum output differential VPP generates a known ac VPP at the junction of Rg2 and Rf2. For instance, if the design intends a maximum 4-VPP differential output, each FDA output pin is 1 V around the Vocm (= 2.5 V), and then back to the Vicm, which produces a 1 V x 221 / (221 + 402) = 0.355 V around the dc setting of Vocm. This simple approach to assessing the input Vicm range for a single-ended to differential design can be applied to any design using an FDA by reducing the input side circuits to a divider to either the signal source and ground or voltage reference on the nonsignal input side. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 27 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances The THS4541 offers a trimmed input offset voltage and extremely low offset drift over the full -40C to 125C operating range. This offset voltage combines with several other error contribution terms to produce an initial 25C differential offset error band, and then a drift over temperature. For each error term, a gain must be assigned to that term. For this analysis, only dc-coupled signal paths are considered. One new source of output error (versus typical op amp analysis) arises from the effect that mismatched resistor values and ratios can have on the two sides of the FDA. Any common-mode voltage or drift creates a differential output error through the slight mismatches arising from the external feedback and gain-setting resistor tolerances, and the approximation (or snap) to standard value. The error terms (25C and drift), along with the gain to the output differential voltage, include: * Input offset voltage--this voltage has a gain equal to the noise gain or 1 + Rf / Rg, where Rg is the total dc impedance from the input pins back to the source, or a dc reference (typically ground). * Input offset current--this current has a gain to the differential output through the average feedback resistor value. The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias current creating a differential output offset because of Rf mismatch. For simplicity, the upper Rf and Rg values are called Rf1 and Rg1 with a ratio of Rf1 / Rg1 G1. The lower elements are defined as Rf2 and Rg2 with a ratio of Rf2 / Rg2 G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is used in the absolute and ratio mismatches. For instance, 1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal, with a worst-case Rf value mismatch of 2% as well. For matched impedance designs with Rt and Rg1 on a single-ended to differential stage, the standard value snap imposes a fixed mismatch in the initial feedback ratios with the resistor tolerance adding a mismatch to this initial ratio mismatch. Define the selected external resistor tolerance as T (so for 1% tolerance resistors, T = 0.01). * Total gain for bias current error is 2 x T x Rfnom Anything that generates an output common-mode level or shift over temperature also generates an output differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in the output common-mode is overridden by the common-mode control loop, where any feedback ratio mismatch creates a balanced, differential error around the Vocm output. The terms that create a differential error from a common-mode term and feedback ratio mismatch include the desired Vocm voltage, any source common-mode voltage, any drift on the reference bias to the Vocm control pin, and any internal offset and drift in the Vocm control path. Considering just the output common-mode control and the source common-mode voltage (Vicm), their conversion to output differential offsets is done by using Equation 4: Vocm G1 G2 Vicm G1 G2 Vod G1 G2 1 (4) 2 Neglecting any G1 and G2 mismatch because of standard values snap, the conversion gain for these two terms can be recast in terms of the nominal Rf / Rg G, and tolerance T, as shown in Equation 5. As G increases, this conversion gain approaches 4T, as a worst-case gain for these terms to output differential offset. Vod G 4T Vocm (1 G) (1 T 2 ) (5) 28 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances (continued) This conversion gain to differential output error is applied to two error terms: Vocm, assuming the input control pin is driven and not floating, and the source Vicm voltage. The source common-mode voltage is assumed to be 0 V in this example. If not, apply this gain to the source common-mode value or range in the intended application. As a full example of using these terms to estimate the worst-case output 25C error band, and then the worstcase drift (by adding all the error terms together independently), use the gain of 2 V/V configuration of Figure 63 with Rf = 402 , and assume 1% tolerance on the resistors with the standard values used in Figure 69. 50- Input-Matched, Gain of 2 V/V from Rt, Single-Ended to Differential, DC-Coupled, Single Supply Vcc Rs 50 Vocm THS4541 Wideband, Fully-Differential Amplifier Rf1 402 Vcc Rg1 191 + Vcc 5V + Vocm 2.5 V + Vs Rt 60.2 Vocm FDA + + R1 500 + VM1 PD Rg2 221 Vcc Rf2 402 Figure 69. DC-Coupled Gain of 2 with Rf = 402 and a Single-Ended to Differential Matched Input 50- Impedance The standard value snap on the signal-input side actually produces added G mismatch along with the resistor tolerances. For Figure 69, G2 = 402 / 221 = 1.819; and G1 = 402 / 218.3 = 1.837 nominally, with a 2% tolerance around this initial mismatch for G2 and G1, if 1% resistors are used. Using the maximum 25C error terms, and a nominal 2.5-V input to the Vocm control pin, gives Table 3 with the error terms, the gains to the output differential error (Vod), and then the summed output error band at 25C. Table 3. Worst-Case Output Vod Error Band 25C MAXIMUM VALUE GAIN TO Vod OUTPUT ERROR Input Vio ERROR TERM 0.45 mV 2.85 V/V 1.2825 mV Input Ios 0.5 A 402 0.201 mV Input Ibcm, Rf mismatch 13 A 8.04 0.105 mV Vocm input, G mismatch 2.5 V 0.0322 80.5 mV Total 82.09 mV The 0.03222 conversion gain for the G ratio mismatch is the worst case, starting from the initially higher G1 value because of standard value snap, and using a 1% tolerance on the Rf and Rg elements of that ratio. The actual Vocm conversion gain range is not symmetric, but is shown that way here. The initial 25C worst-case error band is dominated by the Vocm conversion to Vod through the feedback resistor ratio mismatch. Improve this G match and tolerances to reduce this term. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 29 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Normally, the expected drift in the output Vod is of more interest than an initial error band. Table 4 shows these terms and the summed results, adding all the terms independently to obtain a worst-case drift. Table 4. Worst-Case Output Vod Drift Band ERROR TERM DRIFT MAXIMUM VALUE GAIN TO Vod OUTPUT ERROR Input Vio 2.4 V/C 2.85 V/V 6.84 V/C Input Ios 1.3 nA/C 402 0.522 V/C Input Ibcm, Rf mismatch 15 nA/C 8.04 0.121 V/C Vocm input, G mismatch 12 V/C 0.0322 0.386 V/C Total 7.86 V/C In this calculation, the input offset voltage drift dominates the output differential offset drift. For the last term, the drift for the Vocm path is just for the internal offset drift of the common-mode path. Make sure to also consider the added external drift on the source of the Vocm input. The absolute accuracy and drift for the THS4541 are exceptionally good. Mismatched resistor feedback ratios combined with a high drift in the Vocm control input can actually dominate the output Vod drift. Where the output differential precision is more important than the input matching accuracy, consider matching the networks on the two input sides to achieve improved nominal G1 to G2 match. The gains for the input bias current error terms are relatively low in this example design using 402- feedback values. Higher Rf values give these terms more gain. A less conservative estimate of output drift considers the terms to be uncorrelated and RMS half of each terms worst-case span shown in Table 4. Performing this calculation for this example estimates a less conservative output offset drift of 3.42 V/C; essentially, half the worst-case span of the input offset drift term. Follow these steps to estimate the output differential offset and drift for any external configuration. 8.5 Noise Analysis The first step in the output noise analysis is to reduce the application circuit to its simplest form with equal feedback and gain setting elements to ground, as shown in Figure 70, with the FDA and resistor noise terms to be considered. enRg2 enRf2 Rg Rf r r In+2 + In2 eno2 eni2 enRg2 enRf2 Rg Rf r r Figure 70. FDA Noise-Analysis Circuit The noise powers are shown for each term. When the Rf and Rg terms are matched on each side, the total differential output noise is the RSS of these separate terms. Using NG 1 + Rf / Rg, the total output noise is given by Equation 6. Each resistor noise term is a 4kTR power. eno 30 eniNG 2 2 inRf 2 2 4kTRfNG Submit Documentation Feedback (6) Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Noise Analysis (continued) The first term is simply the differential input spot noise times the noise gain. The second term is the input current noise terms times the feedback resistor (and because there are two terms, the power is two times one of the terms). The last term is the output noise resulting from both the Rf and Rg resistors, again times two, for the output noise power of each side added together. Using the exact values for a 50-, matched, single-ended to differential gain, sweep with a fixed Rf = 402 (see Table 6) and the intrinsic noise eni = 2.2 nV and In = 1.9 pA for the THS4541, gives an output spot noise from Equation 6. Then, dividing by the signal gain (Av) gives the input-referred, spot-noise voltage (ei) shown in Table 5. Table 5. Swept Gain Output and Input-Referred, Spot-Noise Calculations (1) (1) Av Rt, EXACT () Rg1, EXACT () Rg2, EXACT () NOISE GAIN eno (nV/Hz) ei (nV/Hz) 1 55.2 399 425 1.94 6.64 6.64 2 60.1 191 218 2.85 8.71 4.36 3 65.6 124 153 3.63 10.7 3.56 4 72.0 89.7 119 4.37 12.1 3.03 5 79.7 67.8 98.3 5.09 13.7 2.74 6 89.1 54.2 86.5 5.65 15.4 2.56 7 101 43.2 76.6 6.25 16.7 2.39 8 117 35.2 70.1 6.74 17.3 2.16 9 138 29.0 65.8 7.11 18.6 2.06 10 170 23.6 62.5 7.44 18.9 1.89 11 220 18.7 59.3 7.78 19.6 1.78 12 313 14.6 57.7 7.97 20.0 1.66 13 545 10.8 56.6 8.11 20.3 1.56 14 2209 7.26 56.1 8.16 21.1 1.50 Rf = 402 . Notice that the input-referred ei is less than 2.2 nV/Hz for just the THS4541 above a gain of 7 V/V. This result is because NG is less than Av when the source impedance is included in the NG calculation. 8.6 Factors Influencing Harmonic Distortion As shown in the swept frequency harmonic distortion plots, the THS4541 provides extremely low distortion at lower frequencies. In general, FDA output harmonic distortion mainly relates to the open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. As the total load impedance decreases (including the effect of the feedback resistor elements in parallel for loading purposes), the output-stage, openloop linearity degrades, increasing the harmonic distortion, as illustrated in Figure 16 and Figure 34. As the output voltage swings increase, very fine-scale, open-loop, output-stage nonlinearities increase, also degrading the harmonic distortion, as illustrated in Figure 14 and Figure 32. Conversely, decreasing the target output voltage swings drops the distortion terms rapidly. For harmonic-distortion testing, 2 VPP is used as a nominal swing because this value represents a typical ADC, full-scale, differential input range. Increasing the gain acts to decrease the loop gain, resulting in the increasing harmonic distortion terms, as illustrated in Figure 18 and Figure 36. One advantage to the capacitive compensation for the attenuator design (described in the Designing Attenuators typical application example) is that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher frequencies. This compensation holds the loop gain high at frequencies lower than the noise-gain zero, improving distortion in these lower bands. Anything that moves the output pin voltage swings close to clipping into the supplies rapidly degrades harmonic distortion. Output clipping can occur from either absolute differential swing, or the swing can be moved closer to the supplies with the common-mode control. This effect is illustrated in Figure 17 and Figure 35. The THS4541 does an exceptional job of converting from single-ended inputs to differential outputs with very low harmonic distortions. External resistors of 1% tolerance are used in characterization with good results. Imbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert common-mode inputs to differential mode at the outputs with the gain described in the Output DC Error and Drift Calculations and the Effect of Resistor Imbalances section. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 31 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 8.7 Driving Capacitive Loads A very common requirement is driving the capacitive load of an ADC or some other next stage device. Directly driving a capacitive load with a closed-loop amplifier such as the THS4541 can lead to an unstable response, as shown in the step response plots into a capacitive load (see Figure 8 and Figure 26). One typical remedy for this instability is to add two small series resistors (Ro in Figure 71) at the outputs of the THS4541. Figure 6 and Figure 24 provide parametric plots of recommended Ro values versus differential capacitive load values and gain. THS4541 Wideband, Fully-Differential Amplifier 50- Input Match, Gain of 2 V/V from Rt, Single-Ended Source to Differential Output Rf1 402 Vcc Rg1 191 50- Source Ro1 17 Rt 60.2 Vocm FDA + Ro2 17 + Cload 22 pF Rload 500 Output Measurement Point PD Rg2 191 Vcc Rf2 402 Figure 71. Including Ro when Driving Capacitive Loads Operating at higher gains requires lower Ro values to achieve a 0.5-dB flat response for the same capacitive load. Some direct parasitic loading is acceptable with no series Ro that increases with gain setting, as illustrated in Figure 6 and Figure 24 where the Ro value is 0 . Even when these plots suggest no series Ro is required, good practice is to include a place for the Ro elements in the board layout (0- load initially) for later adjustment, in case the response appears unacceptable. The TINA simulation model does a good job of predicting this effect and showing the impact for different choices of capacitive load isolating resistors (Ro). 8.8 Thermal Analysis The relatively low internal quiescent power dissipation for the THS4541, combined with the excellent thermal impedance of the 16-pin VQFN package (RGT), limits the possibility of excessively-high, internal-junction temperatures. Because the 10-pin WQFN (RUN) package has a much higher junction-to-ambient thermal impedance (JA = 146C/W), a more detailed analysis may be warranted. To estimate the internal junction temperature (TJ), an estimate of the maximum internal power dissipation (PD) is first required. There are two pieces to the internal power dissipation: quiescent current power and the power used in the output stage to deliver load current. To simplify the latter, the worst-case, output-stage power is driving a dc differential voltage across a load using half the total supply voltage. As an example: 1. Assume a worst-case, 5% high 5-V supply. This 5.25-V supply with a maximum ICC of 11 mA gives a quiescent power term = 58 mW. 2. Assume a 100- differential load with a static 2.5-V differential voltage established across it. This 25 mA of dc load current generates a maximum output stage power of (5.25 V - 2.5 V) x 25 mA = 69 mW. 3. From this total worst-case internal PD = 127 mW, multiply times the 146C/W thermal impedance for the very-small, 10-pin WQFN package to get a 19C rise from ambient. Even for this extreme condition and the maximum rated ambient temperature of 125C, the junction temperature is a maximum 144C (less than than the rated absolute maximum of 150C). Follow this same calculation sequence for the exact application and package selected to predict the maximum TJ. 32 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 9 Detailed Description 9.1 Overview The THS4541 is a voltage-feedback (VFA) based, fully-differential amplifier (FDA) offering greater than 500-MHz, small-signal bandwidth at a gain of 2 V/V with trimmed supply current and input offset voltage. The core differential amplifier is a slightly decompensated voltage-feedback design with a high slew-rate, precision input stage. This design gives the 500-MHz gain of 2-V/V small-signal bandwidth shown in the characterization curves, with a 1500-V/s slew rate, yielding approximately a 340-MHz, 2-VPP, large-signal bandwidth in the same circuit configuration. The outputs offer near rail-to-rail output swing (0.2-V headroom to either supply), while the device inputs are negative rail inputs with approximately 1.2 V of headroom required to the positive supply. This negative rail input directly supports a bipolar input around ground in a dc-coupled, single-supply design (see Figure 63). Similar to all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode loop. The target for this output average is set by the Vocm input pin that can be either floated to default near midsupply or driven to a desired output common-mode voltage. The Vocm range extends from a very low 0.91 V above the negative supply to 1.1 V below the positive supply, supporting a wide range of modern analog-todigital converter (ADC) input common-mode requirements using a single 2.7-V to 5.4-V supply range for the THS4541. A power-down pin (PD) is included. Pull the PD pin voltage to the negative supply to turn the device off, putting the THS4541 into a very-low quiescent current state. For normal operation, the PD pin must be asserted high. When the device is disabled, remember that the signal path is still present through the passive external resistors. Input signals applied to a disabled THS4541 still appear at the outputs at some level through this passive resistor path as they would for any disabled FDA device. 9.1.1 Terminology and Application Assumptions Like all widely-used devices, numerous common terms have developed that are unique to this type of device. These terms include: * Fully differential amplifier (FDA)--In this document, this term is restricted to devices offering what appears similar to a differential inverting op amp design element that requires an input resistor (not high-impedance input) and includes a second internal control-loop setting the output average voltage (Vocm) to a default or set point. This second loop interacts with the differential loop in some configurations. * The desired output signal at the two output pins is a differential signal swinging symmetrically around a common-mode voltage where that is the average voltage for the two outputs. * Single-ended to differential--always use the outputs differentially in an FDA; however, the source signal can be either a single-ended source or differential, with a variety of implementation details for either. When the FDA operation is single-ended to differential, only one of the two input resistors receives the source signal with the other input resistor connected to a dc reference (often ground) or through a capacitor to ground. To simplify, several features in the application of the THS4541 are not explicitly stated, but are necessary for correct operation. These requirements include: * Good power-supply decoupling is required. Minimize the distance (< 0.1") from the power-supply pins to highfrequency, 0.1-F decoupling capacitors. Often a larger capacitor (2.2 F is typical) is used along with a highfrequency, 0.1-F supply decoupling capacitor at the device supply pins (share this capacitor for the four supply pins in the RGT package). For single-supply operation, only the positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to ground. If necessary, place the larger capacitors somewhat farther from the device and share these capacitors among several devices in the same area of the PCB. For each THS4541, attach a separate 0.1-F capacitor to a nearby ground plane. With cascaded or multiple parallel channels, including ferrite beads from the larger capacitor is often useful to the local high-frequency decoupling capacitor. * Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.1-F decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2F to 6.8F) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These can be placed somewhat farther from Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 33 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Overview (continued) * * * * the device and may be shared among several devices in the same area of the PCB. Although not always stated, make sure to tie the power disable pin to the positive supply when only an enabled channel is desired. Virtually all ac characterization equipment expects a 50- termination from the 50- source, and a 50- single-ended source impedance from the device outputs to the 50- sensing termination. This termination is achieved in all characterizations (often with some insertion loss), but is not necessary for most applications. Matching impedance is most often required when transmitting over longer distances. Tight layouts from a source, through the THS4541, and on to an ADC input do not require doubly-terminated lines or filter designs; the exception is if the source requires a defined termination impedance for correct operation (for example, a SAW filter source). The amplifier signal path is flexible for single or split-supply operation. Most applications are intended to be single supply, but any split-supply design can be used, as long as the total supply across the TH4541 is less than 5.5 V and the required input, output, and common-mode pin headrooms to each supply are observed. Left open, the Vocm pin defaults to near midsupply for any combination of split or single supplies used. The disable pin is negative-rail referenced. Using a negative supply requires the disable pin to be pulled down to within 0.7 V of the negative supply to disable the amplifier. External element values are normally assumed to be accurate and matched. In an FDA, match the feedback resistor values and also match the (dc and ac) impedance from the summing junctions to the source on one side and the reference or ground on the other side. Unbalancing these values introduces nonidealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides create a common-mode to differential conversion. Also, mismatched Rf values and feedback ratios create some added differential output error terms from any common-mode dc, ac signal, or noise terms. Snapping to standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio mismatch. Mismatched resistors or ratios do not in themselves degrade harmonic distortion. If there is meaningful CM noise or distortion coming in, those errors are converted to a differential error through element or ratio mismatch. 9.2 Functional Block Diagram Vs+ (RGT Package) FB+ OUT+ IN 2.5 k High-Aol + Differential I/O Amplifier IN+ 2.5 k + OUT (RGT Package) FB Vs+ 100 k Vcm Error Amplifier + PD Vocm CMOS Buffer 100 k Vs 34 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 9.3 Feature Description 9.3.1 Differential I/O The THS4541 combines a core differential I/O, high-gain block with an output common-mode sense that is compared to a reference voltage and then fed back into the main amplifier block to control the average output to that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on the Vocm pin. If floated, this reference is at half the total supply voltage across the device using two 100-k resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output average voltage to meet the target voltage on the Vocm pin. The bandwidth of this error amplifier is approximately the same bandwidth as the main differential I/O amplifier. The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load driving. No output current limit or thermal shutdown features are provided in this lower-power device. The differential inputs are PNP inputs to provide a negative-rail input range. To operate the THS4541 for the RGT package, connect external resistors from the FB- pin to the IN+ pins, and the FB+ pin to the IN- pins. For the RUN package, connect the OUT- pin to the IN+ pin through an Rf, and the OUT+ pin to the IN- pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+ and IN- pins. The differential I/O op amp operates similarly to an inverting op amp structure where the source must drive the input resistor and the gain is the ratio of the feedback to the input resistor. 9.3.2 Power-Down Control Pin (PD) The THS4541 includes a power-down control pin, PD. This pin must be asserted high for correct amplifier operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the THS4541 into a very low quiescent state (approximately 2 A). Switches in the default Vocm resistor string open to eliminate the fixed bias current (25 A) across the supply in this 200-k voltage divider to midsupply. 9.3.2.1 Operating the Power Shutdown Feature Assert this CMOS input pin to the desired voltage for operation. For applications that require the device to only be powered on when the supplies are present, tie the PD pin to the positive supply voltage. When the PD pin is somewhat below the positive supply pin, slightly more quiescent current is drawn; see Figure 56. For the minimum-on power, assert this pin to the positive supply. The disable operation is referenced from the negative supply; normally, ground. For split-supply operation, with the negative supply below ground, a disable control voltage below ground is required to turn the THS4541 off when the negative supply exceeds -0.7 V. For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to assure operation. This minimum logic-high level allows for direct operation from 1.8-V supply logic. 9.3.3 Input Overdrive Operation The THS4541 input stage architecture is intrinsically robust to input overdrives with the series input resistor required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input overdrive might produce through the source impedance and or the series Rg elements required by all designs. Figure 12 and Figure 30 illustrate the exceptional output limiting and short recovery time for an input overdrive that is attempting to drive the outputs to two times the available swing. The internal input diodes can safely absorb up to 15 mA in an overdrive condition. For designs that require more current to be absorbed, consider adding an external protection diode such as the BAV99 device used in the example ADC interface design of Figure 80. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 35 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 9.4 Device Functional Modes This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than Vs- + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation. The signal path is still present for the source signal through the external resistors. The Vocm control pin sets the output average voltage. Left open, Vocm defaults to an internal midsupply value. Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm error amplifier. 9.4.1 Operation from Single-Ended Sources to Differential Outputs One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode level. While the output side is relatively straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be greater than the Rg value. This input active impedance issue applies to both ac- and dc-coupled designs, and requires somewhat more complex solutions for the resistors to account for this active impedance, as shown in the following subsections. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion When the signal path can be ac coupled, the dc biasing for the THS4541 becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the input and output sides of an FDA design. The input can be ac coupled and the output dc coupled, or the output can be ac coupled and the input dc coupled, or they can both be ac coupled. One situation where the output might be dc coupled (for an ac-coupled input), is when driving directly into an ADC where the Vocm control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input common-mode. In any case, the design starts by setting the desired Vocm. When an ac-coupled path follows the output pins, the best linearity is achieved by operating Vocm at midsupply. The Vocm voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output path is also ac coupled, simply letting the Vocm control pin float is usually preferred in order to get a midsupply default Vocm bias with minimal elements. To limit noise, place a 0.1-F decoupling capacitor on the Vocm pin to ground. After Vocm is defined, check the target output voltage swing to ensure that the Vocm plus the positive or negative output swing on each side does not clip into the supplies. If the desired output differential swing is defined as Vopp, divide by 4 to obtain the Vp swing around Vocm at each of the two output pins (each pin operates 180 out of phase with the other). Check that Vocm Vp does not exceed the absolute supply rails for this rail-to-rail output (RRO) device. Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side are dc blocked (see Figure 61), no common-mode current flows from the output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage. This input headroom also sets a limit for higher Vocm voltages. Because the input Vicm is the output Vocm for ac-coupled sources, the 1.2-V minimum headroom for the input pins to the positive supply overrides the 1.1-V headroom limit for the output Vocm. Also, the input signal moves this input Vicm around the dc bias point, as described in the Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA section. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion The output considerations remain the same as for the ac-coupled design. Again, the input can be dc coupled while the output is ac coupled. A dc-coupled input with an ac-coupled output might have some advantages to move the input Vicm down if the source is ground referenced. When the source is dc coupled into the THS4541 (see Figure 63), both sides of the input circuit must be dc coupled to retain differential balance. Normally, the nonsignal input side has an Rg element biased to whatever the source midrange is expected to be. Providing this midscale reference gives a balanced differential swing around Vocm at the outputs. Often, Rg2 is simply 36 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Device Functional Modes (continued) grounded for dc-coupled, bipolar-input applications. This configuration gives a balanced differential output if the source is swinging around ground. If the source swings from ground to some positive voltage, grounding Rg2 gives a unipolar output differential swing from both outputs at Vocm (when the input is at ground) to one polarity of swing. Biasing Rg2 to an expected midpoint for the input signal creates a differential output swing around Vocm. One significant consideration for a dc-coupled input is that Vocm sets up a common-mode bias current from the output back through Rf and Rg to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this dc current. After the input signal range and biasing on the other Rg element is set, check that the voltage divider from Vocm to Vin through Rf and Rg (and possibly Rs) establishes an input Vicm at the device input pins that is in range. If the average source is at ground, the negative rail input stage for the THS4541 is in range for applications using a single positive supply and a positive output Vocm setting because this dc current lifts the average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V- input pin voltages on the FDA). 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA The design equations for setting the resistors around an FDA to convert from a single-ended input signal to differential output can be approached from several directions. Here, several critical assumptions are made to simplify the results: * The feedback resistors are selected first and set equal on the two sides. * The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA Both of these assumptions are typical and aimed to delivering the best dynamic range through the FDA signal path. After the feedback resistor values are chosen, the aim is to solve for the Rt (a termination resistor to ground on the signal input side), Rg1 (the input gain resistor for the signal path), and Rg2 (the matching gain resistor on the nonsignal input side); see Figure 61 and Figure 63. The same resistor solutions can be applied to either ac- or dc-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the Rt element (as shown in Figure 61) has the advantage of removing any dc currents in the feedback path from the output Vocm to ground. Earlier approaches to the solutions for Rt and Rg1 (when the input must be matched to a source impedance, Rs) follow an iterative approach. This complexity arises from the active input impedance at the Rg1 input. When the FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs must move with the input signal to generate the inverted output signal as a current in the Rg2 element. A more recent solution is shown as Equation 7, where a quadratic in Rt can be solved for an exact required value. This quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs required are: 1. The selected Rf value. 2. The target voltage gain (Av) from the input of Rt to the differential output voltage. 3. The desired input impedance at the junction of Rt and Rg1 to match Rs. Solving this quadratic for Rt starts the solution sequence, as shown in Equation 7. Rs 2 * 2Rs 2Rf Av 2RfRs2 Av 2 (c) Rt 2 Rt 0 2Rf 2 Av RsAv (4 Av ) 2Rf 2 Av RsAv (4 Av ) (7) Being a quadratic, there are limits to the range of solutions. Specifically, after Rf and Rs are chosen, there is physically a maximum gain beyond which Equation 7 starts to solve for negative Rt values (if input matching is a requirement). With Rf selected, use Equation 8 to verify that the maximum gain is greater than the desired gain. Av max Rf 4 Rf Rs 2 1 1 Rf Rs 2)2 ( Rs 1/4 (8) Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 37 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Device Functional Modes (continued) If the achievable Avmax is less than desired, increase the Rf value. After Rt is derived from Equation 7, the Rg1 element is given by Equation 9: Rf Rs 2 Av Rg1 Rs 1 Rt (9) Then, the simplest approach is to use a single Rg2 = Rt || Rs + Rg1 on the nonsignal input side. Often, this approach is shown as the separate Rg1 and Rs elements. Using these separate elements provides a better divider match on the two feedback paths, but a single Rg2 is often acceptable. A direct solution for Rg2 is given as Equation 10: Rf 2 Av Rg2 Rs 1 Rt (10) This design proceeds from a target input impedance matched to Rs, signal gain Av from the matched input to the differential output voltage, and a selected Rf value. The nominal Rf value chosen for the THS4541 characterization is 402 . As discussed previously, going lower improves noise and phase margin, but reduces the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise, and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the total loading on the outputs. Using Equation 8 to Equation 10 to sweep the target gain from 1 to Avmax < 14.3 V/V gives Table 6, which shows exact values for Rt, Rg1, and Rg2, where a 50- source must be matched while setting the two feedback resistors to 402 . One possible solution for 1% standard values is shown, and the resulting actual input impedance and gain with % errors to the targets are also shown in Table 6. Table 6. Required Resistors for a Single-Ended to Differential FDA Design Stepping Gain from 1 V/V to 14 V/V (1) (1) 38 Rt 1% Rg1, EXACT () Rg1 1% Rg2, EXACT () Rg2 1% ACTUAL ZIN %ERR TO Rs ACTUAL GAIN %ERR TO Av 55.2 54.9 60.1 60.4 395 392 421 422 49.731 -0.54% 1.006 0.62% 193 191 220 221 50.171 0.34% 2.014 3 65.6 0.72% 64.9 123 124 151 150 49.572 -0.86% 2.983 -0.57% 4 5 72.0 71.5 88.9 88.7 118 118 49.704 -0.59% 4.005 0.14% 79.7 80.6 68.4 68.1 99.2 100 50.451 0.90% 5.014 0.28% 6 89.1 88.7 53.7 53.6 85.7 86.6 49.909 -0.18% 6.008 0.14% 7 101 102 43.5 43.2 77.1 76.8 50.179 0.36% 7.029 0.42% 8 117 118 35.5 35.7 70.6 69.8 50.246 0.49% 7.974 -0.32% 9 138 137 28.8 28.7 65.4 64.9 49.605 -0.79% 9.016 0.18% 10 170 169 23.5 23.7 62.0 61.9 50.009 0.02% 9.961 -0.39% 11 220 221 18.8 18.7 59.6 59.0 49.815 -0.37% 11.024 0.22% 12 313 316 14.7 14.7 57.9 57.6 50.051 0.10% 11.995 -0.04% 13 545 549 10.9 11.0 56.7 56.2 49.926 -0.15% 12.967 -0.25% 14 2209 2210 7.26 7.32 56.2 56.2 50.079 0.16% 13.986 -0.10% Av Rt, EXACT () 1 2 Rf = 402 , Rs = 50 , and AvMAX = 14.32 V/V. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback resistors determines the frequency response flatness. Similar tables can be built using the equations provided here for other source impedances, Rf values, and gain ranges. Note the extremely low Rg1 values at the higher gains. For instance, at a gain of 14 V/V, that 7.32- standard value is transformed by the action of the common-mode loop moving the input common-mode voltage to appear like a 50- input match. This active input impedance provides an improved input-referred noise at higher gains; see the Noise Analysis section. The TINA model correctly shows this actively-set input impedance in the singleended to differential configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration The designs so far have included a source impedance, Rs, that must be matched by Rt and Rg1. The total impedance at the junction of Rt and Rg1 for the circuit of Figure 63 is the parallel combination of Rt to ground, and the ZA (active impedance) presented by Rg1. The expression for ZA, assuming Rg2 is set to obtain the differential divider balance, is given by Equation 11: Rg1 * Rf * 1 1 Rg2 (c) Rg1 (c) ZA Rg1 Rf 2 Rg2 (11) For designs that do not need impedance matching, but instead come from the low impedance output of another amplifier for instance, Rg1 = Rg2 is the single-to-differential design used without an Rt to ground. Setting Rg1 = Rg2 = Rg in Equation 11 gives the input impedance of a simple input FDA driving from a low-impedance, singleended source to a differential output as shown in Equation 12: Rf 1 Rg ZA 2Rg Rf 2 Rg (12) In this case, setting a target gain as Rf / Rg , and then setting the desired input impedance, allows the Rg element to be resolved first, and then the required Rf to get the gain. For example, targeting an input impedance of 200 with a gain of 4 V/V, Equation 13 gives the physical Rg element. Multiplying this required Rg value by a gain of 4 gives the Rf value and the design of Figure 72. 2D Rg ZA 2 1 D (13) THS4541 Wideband, Fully-Differential Amplifier Rf1 480 200- Input Impedance, Gain of 4 V/V Design Vcc Rg1 120 + Vocm Vs FDA + R1 500 + Output Measurement Point PD Rg2 120 Vcc Rf2 480 Figure 72. 200- Input Impedance, Single-Ended to Differential DC-Coupled Design with Gain of 4 V/V Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 39 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com After being designed, this circuit can also be ac coupled by adding blocking caps in series with the two 120- Rg resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using lower resistors values, leading to lower output noise for a given gain target. 9.4.2 Differential-Input to Differential-Output Operation In many ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again, assuming the two sides of the circuit are balanced with equal Rf and Rg elements, the differential input impedance is now just the sum of the two Rg elements to a differential inverting summing junction. In these designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be dc biased in the allowable range for the input pins with consideration given to the voltage headroom required from each supply. Slightly different considerations apply to ac- or dc-coupled, differential-in to differential-out designs, as described in the following sections. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues There are two typical ways to use the THS4541 with an ac-coupled differential source. In the first method, the source is differential and can be coupled in through two blocking capacitors. The second method uses either a single-ended or a differential source and couples in through a transformer (or balun). Figure 73 shows a typical blocking capacitor approach to a differential input. An optional input differential termination resistor (Rm) is included in this design. This Rm element allows the input Rg resistors to be scaled up while still delivering lower differential input impedance to the source. In this example, the Rg elements sum to show a 200- differential impedance, while the Rm element combines in parallel to give a net 100-, ac-coupled, differential impedance to the source. Again, the design proceeds ideally by selecting the Rf element values, then the Rg to set the differential gain, then an Rm element (if needed) to achieve a target input impedance. Alternatively, the Rm element can be eliminated, the Rg elements set to the desired input impedance, and Rf set to the get the differential gain (= Rf / Rg). THS4541 Wideband, Fully-Differential Amplifier Rf1 402 C1 100 nF Vcc Rg1 100 Downconverter Differential Output Vocm C2 100 nF Rm 200 FDA + R1 500 + Output Measurement Point PD Rg2 100 Vcc Rf2 402 Figure 73. Example Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the THS4541 The dc biasing here is very simple. The output Vocm is set by the input control voltage and, because there is no dc current path for the output common-mode voltage, that dc bias also sets the input pins common-mode operating points. 40 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Transformer input coupling allows either a single-ended or differential source to be coupled into the THS4541; possibly also improving the input-referred noise figure. These designs assume a source impedance that must be matched in the balun interface. The simplest approach is shown in Figure 74, where an example 1:2 turns ratio step-up transformer is used from a 50- source. THS4541 Wideband, Fully-Differential Amplifier Rf1 402 Pulse CX2047LNL 1:2 Turns Ratio Balun C1 100 nF Rs 50 Vcc Rg1 100 M1 90.4 H Vocm + VG1 N1 FDA + + N2 Output Measurement Point R1 500 PD Rg2 100 Vcc Rf2 402 Figure 74. Input Balun Interface Delivers a Differential Input to the THS4541 In this example, this 1:2 turns ratio step-up transformer provides a source and load match from the 50- source if the secondary is terminated in 200 (turns-ratio squared is the impedance ratio across a balun). The two Rg elements provide that termination as they sum to the differential virtual ground at the FDA summing junctions. The input blocking cap (C1) is optional and included only to eliminate dc shorts to ground from the source. This solution often improves the input-referred noise figure more so than just the FDA using this passive (zero power dissipation) input balun. Defining a few ratios allows a noise figure expression to be written as Equation 14: (1 E 2 ) 8 4 10 Log 1 2 2 E DE (DE )2 (c) NF eni (c) En 2 1 n in Rs 1 1 ** 2 E2 (c) 2 D kTRs 2 * where n turns ratio (the ohms ratio is then n2) differential gain in the FDA = Rf / Rg transformer insertion loss in V/V (from a dB insertion loss, convert to linear attenuation = ) kT = 4e-21J at 290 K (17C) * * * * (14) One way to use Equation 14 is to fix the input balun selection, and then sweep the FDA gain by stepping up the Rf value. The lowest-noise method uses just the two Rg elements for termination matching (no Rm element, such as in Figure 74) and sweep the Rf values up to assess the resulting input-referred noise figure. While this method can be used with all FDAs and a wide range of input baluns, relatively low-frequency input baluns are an appropriate choice here because the THS4541 holds exceptional SFDR for less than 40-MHz applications. Two representative selections, with their typical measured spans and resulting model elements, are shown in Table 7. For these two selections, the critical inputs for the noise figures are the turns ratio and the insertion loss (the 0.2 dB for the CX2014LNL becomes a = 0.977 in the NF expression). Table 7. Example Input Step-Up Baluns and Associated Parameters -1-dB FREQUENCY (MHz) PART NUMBER Rs () MIN ADT2-1T 50 0.1 CX2047LNL 50 0.083 NO. OF DECADES MAX INSERTION LOSS (dB) 463 0.3 270 0.2 -3-dB FREQUENCY (MHz) MFR -1-dB POINTS -3-dB POINTS MIN MiniCircuits 3.67 4.22 0.05 Pulse Eng 3.51 3.93 0.044 MODEL ELEMENTS MAX TURNS RATIO L1 (H) L2 (H) k M (H) 825 1.41 79.57747 158.50797 0.99988 112.19064 372 2 90.42894 361.71578 0.99976 180.81512 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 41 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Using the typical input referred noise terms for the THS4541 (eni = 2.2 nV and in = 1.9 pA) and sweeping the total gain from the input of the balun to the differential output over a 10-dB to 24-dB span, gives the input noise figure shown in Figure 75. 14 ADT2-1T CX2047LNL Noise Figure (dB) 13 12 11 10 9 8 7 10 12 14 16 18 Total Gain (dB) 20 22 24 D061 Figure 75. Noise Figure versus Total Gain with the Two Input Baluns of Table 7 The 50- referred noise figure estimates show a decreasing input-referred noise for either balun as the gain increases through 24 dB. The only elements changing in these sweeps are the feedback-resistor values, in order to achieve the total target gain after the step up from the input balun. The example of Figure 74 is a gain of 7.86 V/V, or a 17.9-dB gain where a 9.0-dB input noise figure is predicted from Figure 75. Another advantage for this method is that the effective noise gain (NG) is reduced by the source impedance appearing as part of the total Rg element in the design. The example of Figure 74 operates with a NG = 1 + 402 / (100 + 100) = 3 V/V, giving greater than 300-MHz SSBW in the THS4541 portion of the design. Combining that with the 372 MHz in the balun itself gives greater than 200 MHz in this 18-dB gain stage; or an equivalent greater than 1.6-GHz gain bandwidth product in a low-power, high dynamic range interface. Added features and considerations for the balun input of Figure 74 include: * Many of these baluns offer a secondary centertap. Leave the centertap unconnected for the best HD2 suppression and dc biasing (do not include a capacitor from this centertap to ground). * With a floating secondary centertap, the input pins common-mode voltage again equals the output Vocm setting because there is no dc path for the output common-mode voltage to create a common-mode current (ICM). 42 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues Operating the THS4541 with a dc-coupled differential input source is very simple and only requires that the input pins stay in range of the dc common-mode operating voltage. One example is a dc-to-50-MHz quadrature downconverter output. These outputs typically sit on a dc level with some internal source impedance to the external loads. The example of Figure 76 shows a design using the THS4541 with a simple, passive RLC filter to the inputs (the Rg elements act as the differential termination for the filter design). From the original source behind the internal 250- outputs, this circuit is a gain of 1 to the THS4541 output pins. The dc common-mode operating voltage level shifts from the 1.2-V internal, to the mixer, to an output at the ADC Vcm voltage of 0.95 V. In this case, a simple average of the two dc voltages in the gain of 1 stage gives a 1.08-V input pin common-mode result that is well within range. Quadrature Downconverter DC Bias and Output Impedance Third-Order 50-MHz, 0.2-dB Ripple, Chebychev, DC-Coupled Low-Pass Filter L1 920 nH Rf1 499 Vcc Rg1 250 Vocm C1 7.5 pF VG2 100-MHz, Single-RC Pole R3 250 L2 920 nH C2 7.5 pF FDA + R4 22 + PD Rg2 250 C3 30 pF Low-Power ADC3224 12-Bit, Dual, 125-MSPS ADC Vcc + + R1 22 + VG1 R2 250 THS4541 Wideband, Fully-Differential Amplifier VS2 1.2 V Rf2 499 ADC Vcm 0.95-V Output Figure 76. Example DC-Coupled, Differential I/O Design from a Quadrature Mixer to an ADC Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 43 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 10 Application And Implementation 10.1 Application Information The THS4541 offers an effective solution over a broad range of applications. Two examples are developed here. First, an attenuator stage that directly receives a higher input signal voltage and translates it to a lower differential swing on a fixed common-mode is shown. This design requires some attention to frequency-response flatness issues, and one approach to managing these issues is shown. The second example is a gain of 2 V/V, matched input of 50 to an output set to 0.95 V common-mode followed by a third-order Bessel filter with approximately 20 MHz of bandwidth feeding into the ADC34J22, a low-power, 12-bit, quad 50-MSPS JESD 204B ADC. 10.2 Typical Applications 10.2.1 Designing Attenuators THS4541 Wideband, Fully-Differential Amplifier Gain of 0.1 V/V from Rg1, Single-Ended to Differential, DC-Coupled, Single Supply Vcc Rf1 402 Vcc Rg1 4.02 k Vcm + Vcc 5V + Vcm 2.5 V + VG1 Vocm FDA + + R1 500 + VM1 PD Rg2 4.02 k Vcc Rf2 402 Figure 77. Divide-by-10 Attenuator Application for the THS4541 10.2.1.1 Design Requirements In this design, the aim is to: 1. Present a 4-k input impedance to a 40-V input signal (maximum 10 mA from the prior stage). 2. Attenuate that swing by a factor 1/10 (-20 dB) to a differential output swing. 3. Place that swing on a 2.5-V common-mode voltage at the THS4541 outputs. 4. Operate on a single +5-V supply and ground. 5. Tune the frequency response to a flat Butterworth response with external capacitors. 10.2.1.2 Detailed Design Procedure Operating the THS4541 at a low dc noise gain, or with higher feedback resistors, can cause a lower phase margin to exist, giving the response peaking shown in Figure 1 for the gain of 0.1 (a 1/10 attenuator) condition. Although it is often useful operating the THS4541 as an attenuator (taking a large input range to a purely differential signal around a controlled-output, common-mode voltage), the response peaking illustrated in Figure 1 is usually undesirable. Several methods can be used to reduce or eliminate this peaking; usually, at the cost of higher output noise. Using dc techniques always increases the output noise broadband, while using an ac noise-gain-shaping technique peaks the noise, but only at higher frequencies that can then be filtered off with the typical passive filters often used after this stage. Figure 77 shows a simplified schematic for the gain of 0.1 V/V test from Figure 61. 44 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Typical Applications (continued) This configuration shows a nominal 18 phase margin (from Table 2); therefore, a very highly-peaked response is illustrated in Figure 1. This peaking can be eliminated by placing two feedback capacitors across the Rf elements and a differential input capacitor. Adding these capacitors provides a transition from a resistively set noise gain (NG1 here; 1.1 in Table 2) to a capacitive divider at high-frequency flattening out to a higher noise gain (NG2 here). The key for this approach is to target a Zo, where the noise gain begins to peak up. Using only the following terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence for Zo and then the capacitor values. 1. Gain bandwidth product in Hz (850 MHz for the THS4541) 2. Low frequency noise gain, NG1 ( = 1.1 in the attenuator gain of 0.1 V/V design) 3. Target high-frequency noise gain selected to be higher than NG1 (NG2 = 3.1 V/V is selected for this design) 4. Feedback resistor value, Rf (assumed balanced for this differential design = 402 for this design example) From these elements, for any decompensated voltage-feedback op amp or FDA, solve for Zo (in Hz) using Equation 15: GBP NG1 NG1 * Zo 1 1 2 2 NG2 NG2 NG1 (c) (15) From this target zero frequency in the noise gain, solve for the feedback capacitors using Equation 16: 1 Cf 2S Rf Zo NG2 (16) The next step is to resolve the input capacitance on the summing junction. Equation 17 is for a single-ended op amp (for example, OPA847) where that capacitor goes to ground. To use Equation 17 for a voltage-feedback FDA, cut the target value in half, and place the result across the two inputs (reducing the external value by the specified internal differential capacitance). Cs NG2 1 Cf (17) Setting the external compensation elements using Equation 15 to Equation 17 allows an estimate of the resulting flat bandwidth f-3dB frequency, as shown in Equation 18: f3dB | GBP Zo (18) Running through these steps for the THS4541 in the attenuator circuit of Figure 77 gives the proposed compensation of Figure 78 where Equation 18 estimates a bandwidth of 252 MHz (Zo target is 74.7 MHz). C1 1.7 pF Gain of 0.1 V/V from Rg1, Single-Ended to Differential, DC-Coupled, Single Supply Vcc Vcc Rg1 4.02 k Vcm THS4541 Wideband, Fully-Differential Amplifier Rf1 402 + Vcc 5V + Vcm 2.5 V + VG1 Vocm C3 1 pF FDA + R1 500 + + VM1 PD Vcc Rg2 4.02 k Rf2 402 C2 1.7 pF Figure 78. Compensated Attenuator Circuit Using the THS4541 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 45 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Applications (continued) The 1 pF across the inputs is really a total 1.85 pF, including the internal differential capacitance, and a Cs = 3.7 pF for a single-ended design from Equation 17. These two designs (with and without the capacitors) were both bench tested and simulated using the THS4541 TINA model giving the results of Figure 79. This method does a good job of flattening the response for what starts out as a low phase-margin attenuator application. The simulation model does a very good job of predicting the peaking and showing the same improvement with the external capacitors; both giving a flat, approximately 250-MHz, closed-loop bandwidth for this gain of a 0.1-V/V design. In this example, the output noise begins to peak up (as a result of the noise-gain shaping of the capacitors) above 70 MHz. Use postfiltering to minimize any increase in the integrated noise using this technique. Using this solution to deliver an 8-VPP differential output to a successive approximation register (SAR) ADC (using the 2.5-V Vocm shown), the circuit accepts up to 40-V inputs, where the 4-k input Rg1 draws 10 mA from the source. 10.2.1.3 Application Curve -11 -14 Gain (dB) -17 Bench without caps Bench with caps Sim without caps Sim with caps -20 -23 -26 -29 -32 1M 10M 100M Frequency (Hz) 1G D064 Figure 79. Attenuator Response Shapes with and without External Compensation 46 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 Typical Applications (continued) 10.2.2 Interfacing to High-Performance ADCs Vcc R9 499 D1 BAV99 C1 Vcc 0.2 F 50Source R4 59 R12 35.7 L2 250 nH R13 35.7 C5 33 pF L3 250 nH R16 6.2 R7 205 ADC Input R6 205 Vocm FDA + + PD C6 180 pF R15 442 R17 6.2 Vcc R1 49.9 R5 59 R8 499 2 2-to-3 for ac-coupled Vin 3 1 JP1 C7 1 F ADC Input 2-to-1 for dc-coupled Vin Vcc 0.95 V ADC Vcm R11 Output 100 C3 10 nF Figure 80. DC-Coupled, Bipolar Input Gain of 2 V/V Single-Ended to Differential Interface to ADC 10.2.2.1 Design Requirements In this example design, an impedance matched input assuming a 50- source is implemented with a dc-coupled gain of 2 V/V to the ADC. This configuration effectively reduces the required full-scale input to 0.5 V for a 2-VPP full-scale input ADC. Add a low insertion-loss interstage filter to the ADC to control the broadband noise where the goal is to show minimal SNR reduction in the FFT, as well as minimal degradation in SFDR performance. 10.2.2.2 Detailed Design Procedure The THS4541 provides a very flexible element for interfacing from a variety of sources to a wide range of ADCs. Because all precision and high-speed ADCs require a differential input on a common-mode voltage, this design is the primary application for the THS4541. The THS4541 provides a simple interface to a wide variety of precision SAR, , or higher-speed pipeline ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than typically required in the signal path to the ADC inputs is provided by the THS4541. For instance, the gain of 2 single-ended to differential design example provides approximately a 500-MHz, small-signal bandwidth. Even if the source signal is Nyquist bandlimited, this broad bandwidth can possibly integrate enough THS4541 noise to degrade the SNR through the ADC if the broadband noise is not bandlimited between the amplifier and ADC. Figure 80 shows an example dc-coupled, gain of 2 interface with a controlled, interstage-bandwidth filter implemented on the demonstration board for the JESD digital-output interface, ADC34J22 (a 50-MSPS, quad, 12-bit ADC). This board is called the DEV-ADC34J22 ADC HSMC MODULE with complete documentation at http://dallaslogic.com/prod_dev-adc34j/. Designed for a dc-coupled 50 input match, this design starts with a 499- feedback resistor, and provides a gain of 2.35V/V to the THS4541 output pins. The third-order interstage, low-pass filter provides a 20-MHz Bessel response with a 0.85 V/V insertion loss to the ADC, providing a net gain of 2 V/V from board edge to the ADC inputs. Although the THS4541 can absorb overdrives, an external protection element is added using the BAV99 low-capacitance device, shown in Figure 80. For dc-coupled testing, pins 1 and 2 are jumpered together. When the source is an ac-coupled, 50- source, pins 2 and 3 are jumpered to maintain differential balance. FFT testing normally uses a bandpass filter into the board; an ac-coupled source. A typical 5-MHz, full-scale, single-tone FFT Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 47 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com Typical Applications (continued) is shown in Figure 81, where the jumper is placed from pins 2 to 3. The reported SNR of 70.09 dBFs is only a slight reduction from the tested ADC-only performance of 70.42 dBFs, showing the value of the interstage noise bandwidth limiting filter. The exceptionally low harmonic distortion for the THS4541 also shows up in the very low SFDR and THD shown in Figure 81. This 96-dB SFDR and 92.83-dB THD are comparable to the ADC-only test results. 10.2.2.3 Application Curve Spectral Content and Noise (dBFS) 0 SNR = 70.1 dBFS SFDR = 96 dBFS THD = 92.83 dBFS ENOB = 11.35 bits -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 Frequency (MHz) 20 25 D066 Figure 81. 5-MHz FFT, 50-MSPS Test for the Gain of 2 Interface in Figure 80 48 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 11 Power-Supply Recommendations The THS4541 is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V. Supplyvoltage tolerances are supported with the specified operating range of 2.7 V (10% low on a 3-V nominal supply) and 5.4 V (8% high on a 5-V nominal supply). Supply decoupling is required, as described in the Terminology and Application Assumptions section. Split (or bipolar) supplies can be used with the THS4541, as long as the total value across the device remains less than 5.5 V (absolute maximum). The thermal pad on the RGT package is electrically isolated; connect the thermal pad to any power or ground plane for heat spreading. Using a negative supply to deliver a true swing to ground output in driving SAR ADCs may be desired. While the THS4541 quotes a rail-to-rail output, linear operation requires approximately a 200-mV headroom to the supply rails. One easy option for extending the linear output swing to ground is to provide the small negative supply voltage required using the LM7705 fixed -230-mV, negative-supply generator. This low-cost, fixed negativesupply generator accepts the 3-V to 5-V positive supply input used by the THS4541 and provides a -230-mV supply for the negative rail. Using the LM7705 provides an effective solution, as shown in the TI Designs TIDU187, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts. 12 Layout 12.1 Layout Guidelines Similar to all high-speed devices, best system performance is achieved with a close attention to board layout. The THS4541 evaluation module (EVM) shows a good example of high frequency layout techniques as a reference. This EVM includes numerous extra elements and features for characterization purposes that may not apply to some applications. General high-speed, signal-path layout suggestions include: * Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs; however, open up both ground and power planes around the capacitive sensitive input and output device pins. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and less of a stability issue. * Use good, high-frequency decoupling capacitors (0.1 F) on the ground plane at the device power pins. Higher value capacitors (2.2 F) are required, but may be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors. * When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces. * Higher-speed FDAs, such as the THS4541, include a duplicate of the output pins on the input feedback side of the larger 16-pin VQFN (RGT) package. This duplication is intended to allow the external feedback resistors to be connected with virtually no trace length on the input side of the package. Use this layout approach with no extra trace length on this critical feedback path. The smaller 10-pin, WQFN (RUN) package lines up the outputs and the required inputs on the same side of the package where the feedback (Rf) resistors are placed immediately adjacent to the package with minimal trace length. * The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg elements can have more trace length if needed to the source or to ground. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 49 THS4541 SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 www.ti.com 12.2 Layout Example Figure 82. Layout Example 50 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 THS4541 www.ti.com SLOS375A - AUGUST 2014 - REVISED SEPTEMBER 2014 13 Device and Documentation Support 13.1 Device Support 13.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 13.1.2 Development Support 13.1.2.1 TINA Simulation Model Features The device model is available as part of the TINA model library. The model includes numerous features intended to speed designer progress over a wide range of application requirements. The following list shows the performance parameters included in the model: * For the small-signal response shape with any external circuit: - Differential open loop gain and phase - Parasitic input capacitance - Open-loop differential output impedance * For noise simulations: - Input differential spot voltage noise and a 100-kHz 1/f corner - Input current noise on each input with a 1-MHz 1/f corner * For time-domain, step-response simulations: - Differential slew rate - I/O headroom models to predict clipping - Fine-scale, dc precision terms: - PSRR - CMRR The typical characterization curves show more detail than the macromodels can provide; some of those unmodeled features include: * Harmonic distortion * Temperature drift in dc error terms (VIO and IOS) 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: THS4541 51 PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) THS4541IRGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HS4541 THS4541IRGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HS4541 THS4541IRUNR ACTIVE QFN RUN 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4541 THS4541IRUNT ACTIVE QFN RUN 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4541 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2017 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4541 : * Automotive: THS4541-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing THS4541IRGTR VQFN RGT 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 1.1 8.0 12.0 Q2 3000 330.0 12.4 3.3 3.3 W Pin1 (mm) Quadrant THS4541IRGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 THS4541IRUNR QFN RUN 10 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 THS4541IRUNT QFN RUN 10 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4541IRGTR VQFN RGT 16 3000 367.0 367.0 35.0 THS4541IRGTT VQFN RGT 16 250 210.0 185.0 35.0 THS4541IRUNR QFN RUN 10 3000 210.0 185.0 35.0 THS4541IRUNT QFN RUN 10 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RGT0016A VQFN - 1 mm max height SCALE 3.600 PLASTIC QUAD FLATPACK - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.00 0.08 1.45 0.1 (0.2) TYP 5 12X 0.5 8 EXPOSED THERMAL PAD 4 9 4X 1.5 SYMM 17 1 12 16X PIN 1 ID (OPTIONAL) 13 16 0.1 0.05 SYMM 16X 0.30 0.18 C A B 0.5 0.3 4219032/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Reference JEDEC registration MO-220 www.ti.com EXAMPLE BOARD LAYOUT RGT0016A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.45) SYMM 16 13 16X (0.6) 1 12 16X (0.24) SYMM 17 (0.475) TYP (2.8) 12X (0.5) 9 4 ( 0.2) TYP VIA 5 (R0.05) ALL PAD CORNERS 8 (0.475) TYP (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4219032/A 02/2017 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RGT0016A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.34) 13 16 16X (0.6) 1 12 16X (0.24) 17 SYMM (2.8) 12X (0.5) 9 4 METAL ALL AROUND 5 SYMM 8 (R0.05) TYP (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4219032/A 02/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: THS4541IRGTT THS4541IRGTR THS4541IRUNT THS4541IRUNR