General Description
The MAX817/MAX818/MAX819 microprocessor (µP)
supervisory circuits simplify power-supply monitoring,
battery control, and chip-enable gating in µP systems
by reducing the number of components required.
These devices are designed for use in +5V-powered
systems. Low supply current (11µA typical) and small
package size make these devices ideal for portable
applications. The MAX817/MAX818/MAX819 are specif-
ically designed to ignore fast transients on VCC. Other
supervisory functions include active-low reset, backup-
battery switchover, watchdog input, battery freshness
seal, and chip-enable gating. The Selector Guide below
lists the specific functions available from each device.
These devices offer two pretrimmed reset threshold volt-
ages for ±5% or ±10% power supplies: 4.65V for the L
versions and 4.40V for the M versions. The MAX817/
MAX818/MAX819 are available in space-saving µMAX
packages, as well as 8-pin DIP/SO.
________________________Applications
Battery-Powered Computers and Controllers
Embedded Controllers
Intelligent Instruments
Critical µP Monitoring
Portable Equipment
____________________________Features
♦Precision Supply-Voltage Monitor:
4.65V (MAX81_L)
4.40V (MAX81_M)
♦11µA Quiescent Supply Current
♦200ms Reset Time Delay
♦Watchdog Timer with 1.6sec Timeout
(MAX817/MAX818)
♦Battery-Backup Power Switching; Battery Voltage
Can Exceed VCC
♦Battery Freshness Seal
♦On-Board, 3ns Gating of Chip-Enable Signals
(MAX818)
♦Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning (MAX817/MAX819)
♦Manual Reset Input (MAX819)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
________________________________________________________________ Maxim Integrated Products 1
WDI
GND
PFO
PFI
1
2
8
7
BATT
RESET
VCC
OUT
MAX817
DIP/SO/µMAX
TOP VIEW
3
4
6
5
_________________Pin Configurations
19-0486; Rev 3; 12/05
PART†
MAX817_CPA
MAX817_CSA
MAX817_CUA 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
8 Plastic DIP
8 SO
8 µMAX
______________Ordering Information
_____________________Selector Guide
Ordering Information continued on last page.
†These parts offer a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
SUFFIX RESET THRESHOLD (V)
L4.65
M4.40
FEATURE MAX817
L/M
Active-Low Reset ✔
Backup-Battery Switchover ✔
MAX818
L/M
✔
✔
MAX819
L/M
✔
✔
Power-Fail Comparator ✔—
Watchdog Input ✔ ✔
✔
—
Battery Freshness Seal ✔ ✔
Manual Reset Input — —
✔
✔
Chip-Enable Gating —✔
Pin-Package 8-DIP/SO/
µMAX
8-DIP/SO/
µMAX
—
8-DIP/SO/
µMAX
Low-Power, Pin-
Compatible Upgrades for:
MAX690A/
MAX692A —MAX703/
MAX704
Typical Operating Circuit appears at end of data sheet.
Pin Configurations continued at end of data sheet.
*P
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: The input voltage limits on PFI and WDI may be exceeded (up to 12V VIN) if the current into these pins is limited to less
than 10mA.
Input Voltage
VCC, BATT ..........................................................-0.3V to +6.0V
All Other Pins (Note 1).............................-0.3V to (VCC + 0.3V)
Input Current
VCC Peak ..............................................................................1A
VCC Continuous .............................................................250mA
BATT Peak .....................................................................250mA
BATT Continuous .............................................................50mA
GND .................................................................................25mA
Output Current
OUT................................................................................250mA
All Other Outputs .............................................................25mA
OUT Short-Circuit Duration.................................................10sec
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C) .............727mW
SO (derate 5.88mW/°C above +70°C)..........................471mW
µMAX (derate 4.10mW/°C above +70°C) .....................330mW
Operating Temperature Ranges
MAX81_ _C_A ......................................................0°C to +70°C
MAX81_ _E_A ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
As applicable; CE IN = 0V,
WDI and MR unconnected
VCC < VRST
IOUT = 50mA
IOUT = 5mA
VCC = 0V, VOUT = 0V
IOUT = 250µA, VCC < (VBATT - 0.2V)
CONDITIONS
mV40Battery Switchover Hysteresis
mV
-20
Battery Switch Threshold
(VCC - VBATT)
20
V
VBATT - VBATT -
0.1 0.02
VOUT in Battery-Backup Mode
µA
11 60
ISUPPLY
Supply Current (excluding IOUT)11 45
V0 5.5
Operating Voltage Range, VCC,
VBATT (Note 2)
Ω100BATT to OUT On-Resistance
Ω510VCC to OUT On-Resistance
V
VCC - VCC -
0.5 0.25
VOUT Output
VCC - VCC -
0.05 0.025
µA
5.0
µA1
BATT Leakage Current,
Freshness Seal Enabled
UNITSMIN TYP MAXSYMBOLPARAMETER
VCC = 0V
Supply Current in Battery-
Backup Mode (excluding IOUT)
0.05 1.0
MAX81_ _C
MAX81_ _E
TA= +25°C
TA= TMIN to
TMAX
Power-up
Power-down
TA= +25°C
TA= TMIN to
TMAX
5.5V > VCC > (VBATT + 0.2V)BATT Standby Current (Note 3)
-0.10 0.02
µA
-1.00 0.02
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 3
VPFO = 0V
VPFI > 1.30V, ISOURCE = 40µA, VCC > 4.5V
MAX81_M
VPFI < 1.20V, ISINK = 3.2mA, VCC > 4.50V
MAX81_L
WDI = GND, time average
From VRST, VCC falling at 10V/ms
WDI = VCC, time average
VCC = 5V
MAX81_ _C, VCC = 1V, VCC falling,
VBATT = 0V, ISINK = 50µA
VCC > VRST(MAX), ISOURCE = 800µA
VCC < VRST(MIN), ISINK = 3.2mA
VIL = 0.4V, VIH = 0.8VCC
CONDITIONS
µA250 500
PFO Short-Circuit Current
VCC - 1.5VOH
PFO Output Voltage V
0.4VOL
nA-25 0.01 25IPFI
PFI Input Current
mV4PFI Input Hysteresis
V1.20 1.25 1.30VPFT
PFI Input Threshold
µA
-20 -15
WDI Input Current (Note 5) 120 160
V
3.5VIH
WDI Input Threshold (Note 4) 0.8VIL
ns50tWDI
WDI Pulse Width
V
4.25 4.40 4.50
VRST
Reset Threshold 4.50 4.65 4.75
sec1.00 1.60 2.25tWD
Watchdog Timeout Period
µs100
VCC to RESET Delay
0.3
mV25Reset Threshold Hysteresis
ms140 200 280tRP
Reset Timeout Period
VCC - 1.5VOH
0.4
VOL
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX81_ _E, VCC = 1.2V, VCC falling,
VBATT = 0V, ISINK = 100µA
V
0.3
RESET Output Voltage
0.8 V
2.0
VIL
MR Input Threshold
µs1
MR Pulse Width
VIH
ns100
MR Pulse that Would Not Cause
a Reset
ns120
MR to Reset Delay
kΩ45 63 85
MR Pull-Up Resistance
RESET AND WATCHDOG TIMER
POWER-FAIL COMPARATOR (MAX817/MAX819 only)
MANUAL RESET INPUT (MAX819 only)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.5V for MAX81_L, VCC = +4.5V to +5.5V for MAX81_M, VBATT = 2.8V, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C.)
Power-down
VCC = 5V
IOUT = -1µA, VCC = 0V, VBATT = 2.8V
IOUT = -100µA, VCC = 0V
Enable mode
Disable mode
CONDITIONS
µs15
RESET to CE OUT Delay
3.5VIL
CE OUT Input Threshold V
0.8VIH
V
2.7
VOH
CE OUT Output VCC - 1V
Ω40 150
CE IN to CE OUT Resistance
(Note 6)
µA±0.005 ±1
CE IN Leakage Current
UNITSMIN TYP MAXSYMBOLPARAMETER
Note 2: Either VCC or VBATT can go to 0V if the other is greater than 2.0V.
Note 3: “-” = battery-charging current, “+” = battery-discharging current.
Note 4: WDI is internally serviced within the watchdog timeout period if WDI is left unconnected.
Note 5: WDI input is designed to be driven by a three-stated output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device
must also be able to source and sink at least 200µA when active.
Note 6: The chip-enable resistance is tested with VCC = +4.75V for the MAX818L and VCC = +4.5V for the MAX818M.
VCE IN = VCE OUT = VCC/2.
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
Disable mode, CE OUT = 0V mA0.1 0.75 2.0
CE OUT Short-Circuit Current
(Reset Active)
50Ωsource impedance driver, CLOAD = 50pF ns38
CE IN to CE OUT Propagation
Delay (Note 7)
CHIP-ENABLE GATING (MAX818 only)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 5
8
-40 40
SUPPLY CURRENT
vs. TEMPERATURE (NO LOAD)
12
MAX817/18/19-01
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
-20 0 20 80 10060
16
14
10
0
-40 40
BATTERY SUPPLY CURRENT
(BACKUP MODE) vs. TEMPERATURE
20
80
100
120
140
160
MAX817/18/19-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (nA)
-20 0 20 80 10060
60
40
VCC = 0V
VBATT = 5.0V
VBATT = 2.8V
VBATT = 2.0V
0
-40 40
CE IN TO CE OUT ON-RESISTANCE
vs. TEMPERATURE
20
80
MAX817/18/19-03
TEMPERATURE (°C)
CE IN TO CE OUT ON-RESISTANCE (Ω)
-20 0 20 80 10060
60
40
90
100
10
70
50
30
VCE IN = 4V
VCE IN = 3V
VCE IN = 2V
0
-40 40
BATT TO OUT ON-RESISTANCE
vs. TEMPERATURE
MAX817/18/19-04
TEMPERATURE (°C)
BATT TO OUT ON-RESISTANCE (Ω)
-20 0 20 80 10060
50
100
150
200
250
300
VBATT = 2.0V
VBATT = 2.8V
VBATT = 5.0V
VCC = 0V
0
-40 40
VCC TO RESET PROPAGATION DELAY
vs. TEMPERATURE
200
MAX817/18/19-07
TEMPERATURE (°C)
VCC TO RESET PROPAGATION DELAY (ms)
-20 0 20 80 10060
300
400
500
100
VCC FALLING AT:
0.25V/ms
1V/ms
10V/ms
3
-40 40
VCC TO OUT ON-RESISTANCE
vs. TEMPERATURE
MAX817/18/19-05
TEMPERATURE (°C)
VCC TO OUT ON-RESISTANCE (Ω)
-20 0 20 80 10060
4
5
6
7
180
-40 40
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX817/18/19-06
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
-20 0 20 80 10060
190
200
210
220
1.50
-40 40
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
1.60
MAX817/18/19-08
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (sec)
-20 0 20 80 10060
1.65
1.70
1.55
0
-40 40
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
10
MAX817/18/19-09
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
-20 0 20 80 10060
15
20
5
__________________________________________Typical Operating Characteristics
(VCC = +5V, VBATT = 3.0V, TA= +25°C, unless otherwise noted.)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
6_______________________________________________________________________________________
0
04
BATTERY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX817/18/19-12
VCC (V)
BATTERY SUPPLY CURRENT (µA)
123 56
1
2
3
4
5
6
7
8
0
-40 40
CE IN TO CE OUT PROPAGATION DELAY
vs. TEMPERATURE
MAX817/18/19-13
TEMPERATURE (°C)
CE IN TO CE OUT PROPAGATION DELAY (ns)
-20 0 20
tPD-
tPD+
80 10060
1
2
3
4
5
6
7
20
MAX817/MAX819 PFI THRESHOLD
vs. TEMPERATURE
MAX817/18/19-14
TEMPERATURE (°C)
THRESHOLD (V)
-40 -20 0 60 80 10040
1.244
1.242
1.240
1.246
1.248
1.250
1.252
1.254
4.3
-40 40
RESET THRESHOLD
vs. TEMPERATURE
4.5
MAX817/18/19-10
TEMPERATURE (°C)
RESET THRESHOLD (V)
-20 0 20 8060
4.6
4.7
4.4
MAX81_L
MAX81_M
1000
1200
1400
1600
0
110100 1000 10,000
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
200
MAX817/18/19-11
RESET COMPARATOR OVERDRIVE, VTH-VCC (mV)
MAXIMUM TRANSIENT DURATION (µs)
400
600
800 RESET OCCURS
ABOVE CURVE
20
MAX817/MAX819 PFI TO PFO PROPAGATION
DELAY vs. TEMPERATURE
MAX817/18/19-15
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
-40 -20 0 60 80 10040
28
29
30
31
32
33
____________________________Typical Operating Characteristics (continued)
(VCC = +5V, VBATT = 3.0V, TA= +25°C, unless otherwise noted.)
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Ground. 0V reference for all signals.33
Input Supply Voltage, +5V input.22
Supply Output for CMOS RAM. When VCC rises above the reset threshold
or above VBATT, OUT is connected to VCC through an internal P-channel
MOSFET switch. When VCC falls below VBATT, BATT connects to OUT.
11
GND3
VCC
2
OUT1
Power-Fail Comparator Output. When PFI is less than VPFT or when VCC is
below VBATT, PFO goes low; otherwise PFO remains high. PFO is also used to
enable the battery freshness seal (see Battery Freshness Seal and Power-Fail
Comparator sections).
—5
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to
ground if unused.
4—
Power-Fail Comparator Input. When VPFI is below VPFT or when VCC is below
VBATT, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator
section). Connect to ground if unused.
—4
PFO
5
CE IN
—
PFI4
Backup-Battery Input. When VCC falls below VBATT, OUT switches from VCC to
BATT. When VCC rises above VBATT, OUT reconnects to VCC.
88
Active-Low Reset Output. Pulses low for 200ms when triggered and remains
low whenever VCC is below the reset threshold or when MR is a logic low. It
remains low for 200ms after VCC rises above the reset threshold, the watchdog
triggers a reset, or MR goes low to high.
77
BATT8
RESET
7
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted
for as long as MR is held low and for 200ms after MR returns high. The active-
low input has an internal 63kΩpull-up resistor. It can be driven from a TTL- or
CMOS-logic line or shorted to ground with a switch. Leave open, or connect to
VCC if unused.
——
Watchdog Input. If WDI remains either high or low for longer than the watch-
dog timeout period, the internal watchdog timer runs out and a reset is trig-
gered. If WDI is left unconnected or is connected to a high-impedance
three-state buffer, the watchdog feature is disabled. The internal watchdog
timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a ris-
ing or falling edge. The WDI input is designed to be driven by a three-stated-
output device with a maximum high-impedance leakage current of 10µA and a
maximum output capacitance of 200pF. The output device must also be capa-
ble of sinking and sourcing 200µA when active.
66
Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not
asserted. If CE IN is low when reset is asserted, CE OUT will remain low for
15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to
OUT in battery-backup mode. CE OUT is also used to enable the battery
freshness seal (see Battery Freshness Seal section).
5—
MR
6
WDI—
CE OUT
—
FUNCTIONNAME
MAX817 MAX818 MAX819
PIN
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
8_______________________________________________________________________________________
MAX817
MAX818
MAX819
VCC
BATT
WDI
PFI
CE IN
1.25V
CE OUT
GND
OUT
RESET
THIS PIN
FOR MAX819
ONLY.
THIS SECTION
FOR MAX817/
MAX818 ONLY.
THIS SECTION
FOR MAX817/
MAX819 ONLY.
THIS SECTION
FOR MAX818
ONLY.
MR
PFO
CHIP-ENABLE
OUTPUT
CONTROL
1.25V
RESET
GENERATOR
BATTERY
FRESHNESS
SEAL CIRCUITRY
BATTERY SWITCHOVER
CIRCUITRY
WATCHDOG
TIMER
Figure 1. Functional Diagram
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________ 9
_______________Detailed Description
General Timing Characteristics
Designed for 5V systems, the MAX817/MAX818/
MAX819 provide a number of microprocessor (µP)
supervisory functions (see the Selector Guide on the
first page). Figure 2 shows the typical timing relation-
ships of the various outputs during power-up and
power-down with typical VCC rise and fall times.
RESET Output
A µP’s reset input starts the µP in a known state. The
MAX817/MAX818/MAX819 µP supervisory circuits
assert a reset to prevent code-execution errors during
power-up, power-down, and brownout conditions.
RESET is guaranteed to be a logic low for 0V < VCC <
VRST if VBATT is greater than 1V. Without a backup bat-
tery (VBATT = GND) RESET is guaranteed valid for
VCC ≥1V. Once VCC exceeds the reset threshold an
internal timer keeps RESET low for the reset timeout
period, tRP. After this interval RESET returns high
(Figure 2).
If a brownout condition occurs (VCC drops below the
reset threshold), RESET goes low. Each time RESET is
asserted it stays low for at least the reset timeout peri-
od. Any time VCC goes below the reset threshold the
internal timer clears. The reset timer starts when VCC
returns above the reset threshold. RESET both sources
and sinks current.
Manual Reset Input (MAX819)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. On the MAX819, a logic
low on MR asserts reset. Reset remains asserted while
MR is low, and for tRP (200ms) after it returns high.
During the reset timeout period (tRP), MR’s state is
ignored if the battery freshness seal is enabled. MR has
an internal 63kΩpull-up resistor, so it can be left open
if not used. This input can be driven with TTL/CMOS-
logic levels or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function; external
debounce circuitry is not required. If MR is driven from
long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
Note that MR must be high or open to enable the bat-
tery freshness seal. Once the battery freshness seal is
enabled its operation is unaffected by MR.
Battery Freshness Seal
The MAX817/MAX818/MAX819 battery freshness seal
disconnects the backup battery from internal circuitry
and OUT until it is needed. This allows an OEM to
ensure that the backup battery connected to BATT will
be fresh when the final product is put to use. To enable
the freshness seal on the MAX817 and MAX819:
1) Connect a battery to BATT.
2) Ground PFO.
3) Bring VCC above the reset threshold and hold it
there until reset is deasserted following the reset
timeout period.
4) Bring VCC down again (Figure 3).
Use the same procedure for the MAX818, but ground
CE OUT instead of PFO. Once the battery freshness
seal is enabled (disconnecting the backup battery from
internal circuitry and anything connected to OUT), it
remains enabled until VCC is brought above VRST.
Figure 2. Power-Up and Power-Down Timing
VCC
CE OUT FOLLOWS CE IN
*MAX817/MAX819 ONLY.
VOUT
tRP
VRST
VBATT
VBATT
VBATT
VBATT
VRST
VRESET
VCE OUT**
VPFO*
RESET TO
CE OUT
DELAY**
PFO FOLLOWS PFI
** MAX818 ONLY.
Figure 3. Battery Freshness Seal Timing
VCC
RESET tRP
VRST VRST
CE OUT (MAX818)
(EXTERNALLY HELD AT 0V)
CE OUT STATE LATCHED
AT 1/2 tRP AND 3/4 tRP,
FRESHNESS SEAL ENABLED
PFO (MAX817/MAX819)
(EXTERNALLY HELD AT 0V)
PFO STATE LATCHED
AT 1/2 tRP AND 3/4 tRP,
FRESHNESS SEAL ENABLED
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
10 ______________________________________________________________________________________
On the MAX819, MR must be high or open to enable
the battery freshness seal. Once the battery freshness
seal is enabled its operation is unaffected by MR.
Watchdog Input (MAX817/MAX818)
In the MAX817/MAX818, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within tWD (1.6sec), reset asserts. The inter-
nal 1.6sec timer is cleared by either a reset pulse or by
toggling WDI, which can detect pulses as short as
50ns. The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is
released, the timer starts counting (Figure 4).
To disable the watchdog function, leave WDI uncon-
nected or three-state the driver connected to WDI. The
watchdog input is internally driven low during the first
7/8 of the watchdog timeout period, then momentarily
pulses high, resetting the watchdog counter. When
WDI is left open-circuited, this internal driver clears the
1.6sec timer every 1.4sec. When WDI is three-stated or
left unconnected, the maximum allowable leakage cur-
rent is 10µA and the maximum allowable load capaci-
tance is 200pF.
Chip-Enable Gating (MAX818)
Internal gating of the chip-enable (CE) signal prevents
erroneous data from corrupting CMOS RAM in the
event of an undervoltage condition. The MAX818 uses
a series transmission gate from CE IN to CE OUT
(Figure 5). During normal operation (reset not assert-
ed), the CE transmission gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short CE propagation
delay from CE IN to CE OUT enables the MAX818 to be
used with most µPs. If CE IN is low when reset asserts,
CE OUT remains low for typically 15µs to permit the
current write cycle to complete.
Chip-Enable Input (MAX818)
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate will disable 15µs after reset
asserts (Figure 6). This permits the current write cycle
to complete during power-down.
Figure 4. Watchdog Timing
VCC
tRP tWD
RESET
WDI
Figure 6. Chip-Enable Timing
VBATT
VBATT
VCC
tRP tRP
15µs
VRST VRST VRST VRST
VRESET
VCE IN
VCE OUT
Figure 5. Chip-Enable Transmission Gate
CE IN CE OUT
P
N
OUT
CHIP-ENABLE
OUTPUT
CONTROL
RESET
GENERATOR
BATTERY
SWITCHOVER
CIRCUITRY
BATTERY
FRESHNESS
SEAL CIRCUITRY
MAX817
MAX818
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
______________________________________________________________________________________ 11
Any time a reset is generated, the CE transmission gate
remains disabled and CE IN remains high impedance
(regardless of CE IN activity) for the reset timeout peri-
od. When the CE transmission gate is enabled, the
impedance of CE IN appears as a 40Ωresistor in series
with the load at CE OUT. The propagation delay
through the CE transmission gate depends on VCC, the
source impedance of the drive connected to CE IN,
and the loading on CE OUT (see Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ωdriver and a 50pF load
capacitance (Figure 7). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low-output-impedance driver.
Chip-Enable Output (MAX818)
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a 40Ωresistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pull-up con-
nects CE OUT to OUT (Figure 5). This pull-up turns off
when the transmission gate is enabled.
Power-Fail Comparator
(MAX817/MAX819)
The MAX817/MAX819 PFI input is compared to an inter-
nal reference. If PFI is less than the power-fail threshold
(VPFT), PFO goes low. The power-fail comparator is
intended for use as an undervoltage detector to signal a
failing power supply (Figure 8). However, the comparator
does not need to be dedicated to this function because it
is completely separate from the rest of the circuitry.
The power-fail comparator turns off and PFO goes low
when VCC falls below VBATT. During the reset timeout
period (tRP), PFO is forced high, regardless of the state
of VPFI (see Battery Freshness Seal section). If the com-
parator is unused, connect PFI to ground and leave PFO
unconnected. PFO can be connected to MR on the
MAX819 so that a low voltage on PFI will generate a
reset (Figure 9). In this configuration, when the monitored
voltage causes PFI to fall below VPFT, PFO pulls MR low,
causing a reset to be asserted. Reset remains asserted
as long as PFO holds MR low, and for tRP (200ms) after
PFO pulls MR high when the monitored supply is above
the programmed threshold. When PFO is connected to
MR, it is not possible to enable the battery freshness
seal. Enabling the battery freshness seal requires MR to
be high or open. Once the battery freshness seal is
enabled, it is no longer affected by PFO’s connection to
MR.
Figure 7. CE Propagation Delay Test Circuit
CE IN
BATT
CE OUT
GND
MAX818
CL*
* CL INCLUDES LOAD CAPACITANCE, STRAY CAPACITANCE,
AND SCOPE-PROBE CAPACITANCE.
50pF
VCC
+5V
50Ω
50Ω
Figure 8. Using the Power-Fail Comparator to Generate a
Power-Fail Warning
MAX817
MAX819
VWARN = 1.25
POWER-FAIL-WARNING TRIP VOLTAGE
R1 + R2
R2
PFI
PFO
R1
R2
µP
VCC
VIN
NMI
RESET
1.25V
RESET
+5V
REGULATOR
( )
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
12 ______________________________________________________________________________________
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of RAM. With a backup battery
installed at BATT, the MAX817/MAX818/MAX819 auto-
matically switch RAM to backup power when VCC falls.
These devices require two conditions before switching
to battery-backup mode: 1) VCC must be below the
reset threshold, and 2) VCC must be below VBATT.
Table 1 lists the status of the inputs and outputs in bat-
tery-backup mode.
As long as VCC exceeds the reset threshold, OUT con-
nects to VCC through a 5ΩPMOS power switch. Once
VCC falls below the reset threshold, VCC or VBATT
(whichever is higher) switches to OUT. When VCC falls
below VRST and VBATT, BATT switches to OUT through
an 80Ωswitch.
When VCC exceeds the reset threshold, it is connected to
the substrate, regardless of the voltage applied to BATT
(Figure 10). During this time, the diode (D1) between
BATT and the substrate will conduct current from BATT
to VCC if VBATT is 0.6V greater than VCC. When BATT
connects to OUT, backup mode is activated and the
internal circuitry is powered from the battery (Table 1).
When VCC is just below VBATT, the current draw from
BATT is typically 6µA. When VCC drops to more than 1V
below VBATT, the internal switchover comparator shuts
off and the supply current falls to less than 1µA.
__________Applications Information
The MAX817/MAX818/MAX819 are protected for typical
short-circuit conditions of 10sec or less. Shorting OUT
to ground for longer than 10sec destroys the device.
Decouple VCC, OUT, and BATT to ground by placing
0.1µF capacitors as close to the device as possible.
Connected to VOUT. Current drawn from
the battery is less than 1µA, as long as
VCC < VBATT - 0.2V.
VBATT
Logic low
Disconnected from VOUT.VCC
VRESET
Logic high. The open-circuit voltage is equal
to VOUT.
VCEOUT
High impedanceVCEIN
Watchdog timer is disabled.VWDI
Connected to VBATT through an internal 80Ω
PMOS switch.
VOUT
STATUSSIGNAL
Table 1. Input and Output Status in
Battery-Backup Mode
Figure 9. Monitoring an Additional Supply by Connecting
PFO to MR.
MAX819
V2 (RESET) = 1.25
ADDITIONAL SUPPLY RESET VOLTAGE
R1 + R2
R2
R1
R2
µP
VCC
V1
V2
RESET
PFI
RESET
MR
PFO
( )
Figure 10. Backup-Battery-Switchover Block Diagram
SW1/SW2 SW3/SW4CONDITION
VCC > Reset Threshold Open Closed
Closed
Open
Open
Closed
VCC < Reset Threshold and
VCC > VBATT
VCC < Reset Threshold and
VCC < VBATT
RESET THRESHOLD = 4.65V IN MAX81_L
RESET THRESHOLD = 4.4V IN MAX81_M
OUT
D3
SUBSTRATE
D1 D2
SW2
SW1 SW4
SW3
BATT VCC
MAX817
MAX818
MAX819
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
______________________________________________________________________________________ 13
Watchdog Input Current
The MAX817/MAX818 WDI inputs are internally driven
through a buffer and series resistor from the watchdog
counter (Figure 1). When WDI is left unconnected, the
watchdog timer is serviced within the watchdog timeout
period by a low-high-low pulse from the counter chain.
For minimum watchdog input current (minimum overall
power consumption), leave WDI low for the majority of the
watchdog timeout period, pulsing it low-high-low once
within 7
/8of the watchdog timeout period to reset the
watchdog timer. If instead WDI is externally driven high for
the majority of the timeout period, up to 150µA can flow
into WDI.
Using a SuperCap™ as a
Backup Power Source
SuperCaps are capacitors with extremely high capaci-
tance values (on the order of 0.47F) for their size. Since
BATT has the same operating voltage range as VCC, and
the battery switchover threshold voltages are typically
±30mV centered at VBATT, a SuperCap and simple
charging circuit can be used as a backup power source.
Figure 11 shows a SuperCap used as a backup source.
If VCC is above the reset threshold and VBATT is 0.5V
above VCC, current flows to OUT and VCC from BATT
until the voltage at BATT is less than 0.5V above VCC.
For example, if a SuperCap is connected to BATT
through a diode to VCC, and VCC quickly changes from
5.4V to 4.9V, the capacitor discharges through OUT
and VCC until VBATT reaches 5.1V typical. Leakage cur-
rent through the SuperCap charging diode and the
internal power diode eventually discharges the
SuperCap to VCC. Also, if VCC and VBATT start from
0.1V above the reset threshold and power is lost at
VCC, the SuperCap on BATT discharges through VCC
until VBATT reaches the reset threshold. Battery-backup
mode is then initiated and the current through VCC
goes to zero.
Operation Without a
Backup Power Source
The MAX817/MAX818/MAX819 were designed for bat-
tery-backed applications. If a backup battery is not
used, connect VCC to OUT, and connect BATT to
ground.
Replacing the Backup Battery
The backup power source can be removed while VCC
remains valid, without danger of triggering a reset
pulse, if BATT is decoupled with a 0.1µF capacitor to
ground. As long as VCC stays above the reset thresh-
old, battery-backup mode cannot be entered.
Adding Hysteresis to the Power-Fail
Comparator (MAX817/MAX819)
The power-fail comparator has a typical input hystere-
sis of 4mV. This is sufficient for most applications where
a power-supply line is being monitored through an
external voltage divider (see Monitoring an Additional
Supply).
For additional noise margin, connect a resistor between
PFO and PFI, as shown in Figure 12. Select the ratio of
R1 and R2 such that PFI sees VPFT when VIN falls to the
Figure 11. Using a SuperCap™ as a Backup Power Source
with a +5V ±10% Supply
SuperCap is a trademark of Baknor Industries.
BATT
VCC OUT
RESET
GND
TO STATIC RAM
TO µP
0.1F
MAX817
MAX818
MAX819
+5V
100k
Figure 12. Adding Hysteresis to the Power-Fail Comparator
VCC
GND
TO µP
PFI
PFO
R1
R2 R3
*OPTIONAL
C1*
VIN +5V
R1 + R2
R2
VH = 1.25V
VTRIP = 1.25V
+
+
||
||
R2 R3
R1 R2 R3
MAX817
MAX819
PFO
0V
+5V
VH
VL
0V VTRIP
VIN
( )
R1
VL - 1.25
R3
5 - 1.25 =R2
1.25
( )
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
14 ______________________________________________________________________________________
desired trip point (VTRIP). Resistor R3 adds hysteresis.
It will typically be an order of magnitude greater than R1
or R2. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max) PFI input leakage
current does not shift the trip point. R3 should be larger
than 200kΩto prevent it from loading down the PFO pin.
Capacitor C1 adds additional noise rejection.
Monitoring an Additional Supply
(MAX817/MAX819)
The MAX817/MAX819 µP supervisors can monitor either
positive or negative supplies using a resistor voltage
divider to PFI. PFO can be used to generate an interrupt
to the µP or to trigger a reset (Figures 9 and 13).
Interfacing to µPs with
Bidirectional Reset Pins
µPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX817/MAX818/
MAX819 RESET output. If, for example, the RESET out-
put is driven high and the µP wants to pull it low, inde-
terminate logic levels may result. To correct this,
connect a 4.7kΩresistor between the RESET output
and the µP reset I/O, as in Figure 14. Buffer the RESET
output to other system components.
Negative-Going VCC Transients
These supervisors are relatively immune to short-dura-
tion, negative-going VCC transients (glitches) while
issuing a reset to the µP during power-up, power-down,
and brownout conditions. Therefore, resetting the µP
when VCC experiences only small glitches is usually not
desirable.
The Typical Operating Characteristics show a graph of
Maximum Transient Duration vs. Reset Threshold
Overdrive for which reset pulses are not generated. The
graph was produced using negative-going VCC pulses,
starting at 3.3V and ending below the reset threshold by
the magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
going VCC transient can typically have without triggering
a reset pulse. As the amplitude of the transient increases
(i.e., goes farther below the reset threshold), the maxi-
mum allowable pulse width decreases. Typically, a VCC
transient that goes 100mV below the reset threshold and
lasts for 135µs will not trigger a reset pulse.
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Figure 13. Monitoring a Negative Voltage
MAX817
MAX819
VCC
GND
PFI PFO
R1
R2
V-
NOTE: VTRIP IS NEGATIVE
0V
PFO
0V
VTRIP
V-
+5V
+5V
R1
5 - 1.25
R2
1.25 - VTRIP
=
Figure 14. Interfacing to µPs with Bidirectional Reset I/O
MAX817
MAX818
MAX819
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
4.7k
VCC
GND
VCC
GND
RESET
RESET
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
______________________________________________________________________________________ 15
____Pin Configurations (continued)
__________Typical Operating Circuit
WDI
GND
CE OUT
CE IN
1
2
8
7
BATT
RESET
VCC
OUT
MAX818
DIP/SO/µMAX
TOP VIEW
3
4
6
5
MR
GND
PFO
PFI
1
2
8
7
BATT
RESET
VCC
OUT
MAX819
DIP/SO/µMAX
3
4
6
5
CE IN*
*CE IN AND CE OUT APPLY TO MAX818 ONLY.
**WDI APPLIES TO MAX817/MAX818 ONLY.
BATT
RESET
I/O
OUT
CMOS
RAM
RESET
WDI**
CE OUT*
0.1µF
0.1µF0.1µF
GND
MAX817
MAX818
MAX819
VCC
ADDRESS
DECODE
REAL-
TIME
CLOCK
A0–A15
µP
+5V
Watchdog Software Considerations
(MAX817/MAX818)
To help the watchdog timer monitor software execution
more closely, set and reset the watchdog input at different
points in the program, rather than “pulsing” the watchdog
input high-low-high or low-high-low. This technique avoids
a “stuck” loop, in which the watchdog timer would contin-
ue to be reset within the loop, keeping the watchdog from
timing out. Figure 15 shows an example of a flow diagram
where the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine, the problem would quickly be
corrected, since the I/O is continually set low and the
watchdog timer is allowed to time out, triggering a reset or
an interrupt. As described in the Watchdog Input Current
section, this scheme results in higher average WDI input
current than does the method of leaving WDI low for the
majority of the timeout period and periodically pulsing it
low-high-low. Figure 15. Watchdog Flow Diagram
START
SET
WDI
LOW
SUBROUTINE
OR PROGRAM LOOP,
SET WDI
HIGH
RETURN
END
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
MAX817L/M, MAX818L/M, MAX819L/M*
+5V Microprocessor Supervisory Circuits
Ordering Information (continued) Chip Information
TRANSISTOR COUNT: 719
†These parts offer a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
PART†
MAX817_EPA
MAX817_ESA
MAX818_CPA 0°C to +70°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE PIN-PACKAGE
8 Plastic DIP
8 SO
8 Plastic DIP
MAX818_CSA
MAX818_CUA
MAX818_EPA -40°C to +85°C
0°C to +70°C
0°C to +70°C 8 SO
8 µMAX
8 Plastic DIP
MAX818_ESA -40°C to +85°C 8 SO
MAX819_CPA
MAX819_CSA
MAX819_CUA 0°C to +70°C
0°C to +70°C
0°C to +70°C 8 Plastic DIP
8 SO
8 µMAX
MAX819_EPA
MAX819_ESA -40°C to +85°C
-40°C to +85°C 8 Plastic DIP
8 SO
SUFFIX RESET THRESHOLD (V)
L4.65
M4.40
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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