CY62148ESL-55ZAXIT - Cypress Semiconductor

CY62148ESL MoBL®

4-Mbit (512 K × 8) St atic RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-50045 Rev. *C Revised August 23, 2010

4-Mbit (512 K × 8) Stat ic RAM

Features

■Higher speed up to 55 ns

■Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V

■Ultra low standby power

❐Typical standby current: 1 µA

❐Maximum standby current: 7 µA

■Ultra low active power

❐Typical acti ve current: 2 mA at f = 1 MHz

■Easy memory expansion with CE and OE features

■Automatic power-down when deselected

■Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■Available in Pb-free 32-Pin shrunk thin small outline package

(STSOP) package

Functional Description

The CY62148ESL is a high performance CMOS static RAM

organized as 512 K words by 8-bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL®) in portable

applications such as cellular telephones. The device also has an

automatic power-down feature that significantly reduces power

consumption. Placing the device in standby mode reduces

power consumption by more than 99 percen t when deselected

(CE HIGH). The eight input and output pins (I/O0 through I/O7)

are placed in a high impedance state when the device is

deselected (CE HIGH), the outputs are disabled (OE HIGH), or

during a write operation (CE LOW and WE LOW).

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)

is then written into the location specified on the address pins (A0

through A18).

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the I/O pins.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

A0IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

A17

ROW DECODER

COLUMN DECODER

512K x 8

ARRAY

INPUT BUFFER

A10

A11

A12

A18

Logic Block Diagram

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

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Document #: 001-50045 Rev. *C Page 2 of 13

Contents

4-Mbit (512 K × 8) Static RAM ..........................................1

Features .............................................................................1

Functional Description ................... ... .............. ... .. ............1

Pin Configuration .............................................................3

Product Portfolio ..............................................................3

Maximum Ratings .............................................................4

Operating Range ..................... .. ............................ ... .........4

Electrical Characteristics .................................................4

Capacitance ......................................................................5

Thermal Resistance ..........................................................5

Data Retention Characteristics .......................................6

Switching Characteristics ...................... ... .......................7

Switching Waveforms .............. ............................ ............8

Truth Table ........................................................................9

Ordering Information ......................................................10

Ordering Code Definitions .............................................10

Package Diagram ............................................................11

Acronyms ........................................................................11

Document Conventions .................. ... ............................11

Units of Measure ............. ............................ ... ... ........11

Document History Page ............. ............................ ... .....12

Sales, Solutions, and Legal Information ......................13

Worldwide Sales and Design Support .......................13

Products .................................................................... 13

PSoC Solutions .........................................................13

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Document #: 001-50045 Rev. *C Page 3 of 13

Pin Configuration

Figure 1. 32-Pin STSOP (Top View)

A11

A13

A17

A15

A18

A16

A14

A12

VCC

A10

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

STSOP

Top View

(not to scale)

Product Portfolio

Product Range VCC Range (V)[1] Speed

(ns)

Power Dissipation

Operating ICC, (mA) Standby, ISB2

(µA)

f = 1 MHz f = fmax

Typ[2] Max Typ[2] Max Typ[2] Max

CY62148ESL Industrial/

Automotive-A 2.2 V to 3.6 V and 4.5 V to 5.5 V 55 2 2.5 15 20 1 7

Notes

1. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.

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Document #: 001-50045 Rev. *C Page 4 of 13

Maximum Ratings

Exceeding m aximu m ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage temperature.................................–65 °C to +150 °C

Ambient temperature with pow er applied ....55 °C to +125 °C

Supply voltage to ground potential................. –0.5 V to 6.0 V

DC voltage applied to outputs

in high Z state [3, 4].........................................–0.5 V to 6.0 V

DC input voltage [3, 4].....................................–0.5 V to 6.0 V

Output current into outputs (low)..................................20 mA

Static discharge voltage.......................................... > 2001 V

(MIL-STD-883, Method 3015)

Latch-up current......................................................> 200 mA

Operating Range

Device Range Ambient

Temperature VCC[5]

CY62148ESL Industrial/

Automotive-A –40 °C to +85 °C 2.2 V to 3.6 V,

and 4.5 V to

5.5 V

Electrical Characteristics

Over the operating range

Parameter Description Test Co nditions 55 ns (Industrial/Automotive-A) Unit

Min Typ[6] Max

VOH Output HIGH voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – V

2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – –

4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – –

VOL Output LOW voltage 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 V

2.7 < VCC < 3.6 IOL = 2.1 mA – – 0.4

4.5 < VCC < 5.5 IOL = 2.1 mA – – 0.4

VIH Input HIGH voltage 2.2 < VCC < 2.7 1.8 – VCC + 0.3 V

2.7 < VCC < 3.6 2.2 – VCC + 0.3

4.5 < VCC < 5.5 2.2 – VCC + 0.5

VIL [7] Input LOW voltage 2.2 < VCC < 2.7 –0.3 – 0.4 V

2.7 < VCC < 3.6 –0.3 – 0.6

4.5 < VCC < 5.5 –0.5 – 0.6

IIX Input leakage current GND < VI < VCC –1 – +1 µA

IOZ Output leakage current GND < VO < VCC, output disabled –1 – + 1 µA

ICC VCC operating supply

current f = fmax = 1/tRC VCC = VCCmax

IOUT = 0 mA, CMOS levels –15 20mA

f = 1 MHz – 2 2.5

ISB1[8] Automatic CE

power-down current —

CMOS inputs

CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,

f = fmax (address and data only), f = 0 (OE and WE),

VCC = VCC(max)

–1 7µA

–

ISB2[8] Automatic CE

power-down current —

CMOS inputs

CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,

f = 0, VCC = VCC(max) –1 7µA

–

Notes

3. VIL(min) = –2.0 V for pulse durations less than 20 ns.

4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.

5. Full device AC operation assu mes a minimum of 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.

6. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.

7. Under DC conditions the device meets a VIL of 0.8 V (for VCC range of 2.7 V to 3. 6 V and 4.5 V to 5.5 V) and 0.6 V (for VCC range of 2.2 V to 2.7 V). However, in

dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6 V and 0.4 V for the above ranges. Refer to AN13470 for de tails.

8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.

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Document #: 001-50045 Rev. *C Page 5 of 13

Capacitance

Parameter [9] Description Test Conditions Max Unit

CIN Input capacitance TA = 25 °C, f = 1 MHz,

VCC = VCC(Typ) 10 pF

COUT Output capacitance 10 pF

Thermal Resist ance

Parameter [9] Description Test Conditions STSOP Unit

ΘJA Thermal resistance

(junction to ambient) Still air, soldered on a 3 × 4.5 inch, two-laye r pri nted

circuit board 49.02 °C/W

ΘJC Thermal resistance

(junction to case) 14.07 °C/W

Figure 2. AC Test Loads and Waveforms

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND 90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalentto: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

Parameter 2.5 V 3.0 V 5.0 V Unit

R1 16667 1103 1800 Ω

R2 15385 1554 990 Ω

RTH 8000 645 639 Ω

VTH 1.20 1.75 1.77 V

Notes

9. Tested initially and after any design or process changes that may aff ect these parameters.

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Data Retention Characteristics

Over the operating range

Parameter Description Conditions Min Typ[10] Max Unit

VDR VCC for data retention 1.5 – – V

ICCDR [11] Data retention current CE > VCC – 0.2 V, VIN > VCC – 0.2 V or

VIN < 0.2 V, VCC = 1.5 V Industrial/

Automotive-A –17µA

tCDR Chip deselect to data

retention time 0––ns

tR [12] Operation recovery time 55 – – ns

Figure 3. Data Retention Waveform

VCC(min)

tCDR

VDR >1.5 V

DATA RETENTION MODE

VCC

Notes

10.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.

11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.

12.Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

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Switching Characteristics

Over the operating range

Parameter [13] Description 55 ns (Industri a l/Automotive-A) Unit

Min Max

Read Cycle

tRC Read cycle time 55 – ns

tAA Address to data valid – 55 ns

tOHA Data hold from address change 10 – ns

tACE CE LOW to data valid – 55 ns

tDOE OE LOW to data valid – 25 ns

tLZOE OE LOW to low Z [14] 5–ns

tHZOE OE HIGH to high Z [14, 15] –20ns

tLZCE CE LOW to low Z [14] 10 – ns

tHZCE CE HIGH to high Z [14, 15] –20ns

tPU CE LOW to power-up 0 – ns

tPD CE HIGH to power-up – 55 ns

Write Cycle [16]

tWC Write cycle time 55 – ns

tSCE CE LOW to write end 40 – ns

tAW Address setup to write end 40 – ns

tHA Address hold from write end 0 – ns

tSA Address setup to write start 0 – ns

tPWE WE pulse width 40 – ns

tSD Data setup to write end 25 – ns

tHD Data hold from write end 0 – ns

tHZWE WE LOW to high Z [14, 15] –20ns

tLZWE WE HIGH to low Z [14] 10 – ns

Notes

13.Test conditions for all para meters other than tri-st ate pa rameters assume signal transition ti me of 3 ns or less (1 V/ns), timing refer ence levels of VCC(typ)/2, input p ulse

levels of 0 to VCC(typ), and out put loading of the specified IOL/IOH as shown in A C Test Loads and Waveforms on page 5.

14.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

15.tHZOE, tHZCE, and tHZWE transitions are measured when the outpu t enter a high impedance state.

16.The internal write time of the memory is defi ned by th e overlap of WE , CE = VIL. All sig nals must be ACTIVE to initiat e a write and an y of these signals ca n te rminate

a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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Document #: 001-50045 Rev. *C Page 8 of 13

Switching Waveforms

Figure 4. Read Cycle No. 1 (Address Transition Controlled) [17, 18]

Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19]

Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [20, 21]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

IMPEDANCE

ICC

ISB

HIGH

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

DATA VALID

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

ADDRESS

DATA I/O

NOTE

Notes

17.Device is continuously selected. OE, CE = VIL.

18.WE is HIGH for read cycles.

19.Address valid before or similar to CE transition LOW.

20.Data I/O is high impedance if OE = VIH.

21.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

22.During this period, the I/Os are in output state. Do not apply input signals.

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Document #: 001-50045 Rev. *C Page 9 of 13

Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24]

Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [24]

Truth Table

CE WE OE I/O Mode Power

H[26] X X High Z Deselect/power-down Standby (ISB)

L H L Data out Read Active (ICC)

L H H High Z Output disabled Active (ICC)

L L X Data in Write Active (ICC)

Switching Waveforms (continued)

tWC

DATA VAL ID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA I/O

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA I/O

NOTE

Notes

23.Data I/O is high impedance if OE = VIH.

24.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

25.During this period, the I/Os are in output state. Do not apply input signals.

26.Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

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Ordering Information

Table 1 lists the CY62148 ESL MoBL key package features and ordering codes. The table co ntains only the parts that are currently

available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress

website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.

Ordering Code Definitions

Tab le 1. Key features and Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

55 CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-free) Industrial

CY62148ESL-55ZAXA 51-85094 32-Pin STSOP (Pb-free) Automotive -A

Family: Low power SR A M

621 4 8

Dens ity = 4 Mbit

Company ID: CY = Cypress

Bus Width = x8

Process technology: 90-nm

SL = Low power

Speed grade (55 ns)

ZAX

32-Pin STSOP (Pb-free)

I/A Temperature grad es:

I = Industrial

A = Automotive-A

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Acronyms Document Conventions

Units of Measure

Package Diagram

Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 mm × 13.4 mm), 51-85094

51-85094-*E

Acronym Description

CMOS complementary metal oxide semiconductor

I/O input/output

MoBL more battery life

SRAM static random access memory

STSOP shrunk thin small outline package

Symbol Unit of Measure

ns nano seconds

Vvolts

µA micro ampe re s

mA milli amperes

pF pico Farad

°C degree Celsius

Wwatts

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Document History Page

Document Title: CY62148ESL MoBL® 4-Mbit (512 K × 8) Static RAM

Document Number: 001-50045

Revision ECN Orig. of

Change Submission

Date Description of Change

** 2612938 VKN/PYRS 01/21/09 New datasheet

*A 2800124 VKN 11/06/2009 Included Automotive-A information

*B 2947039 VKN 06/10/2010 Added footnote related to chip enable in Truth Table

Added footnote for the ISB2 parameter in Electrical Characteristics

Updated Package Diagram

Updated links in Sales, Solutions, and Legal Informatio n

*C 3006318 AJU 08/23/10 Template update.

Updated table of contents.

Added acronyms, units of measure and ordering code definitions.

Added reference to note 8 to parameter ISB1on page 4 under Electrical

characterisitics table.

Added reference to note 1 1 to parameter ICCDR on page 6 under data retention

characteristics table.

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Document #: 001-50045 Rev. *C Revised August 23, 2010 Page 13 of 13

MoBL is the re gistered tradema rk, and More Batte ry Life is the tr ademark of Cypress S emiconductor C orporation. All ot her product and co mpany names mentioned in th is document are the trademarks

of their respective holders.

CY62148ESL MoBL®

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss pro duc ts are n ot war ran ted no r int end ed to be us ed for

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl i cat ions, unless pursuant to an express writte n agreement with Cypress. Furthermore, Cyp ress doe s not author i ze its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conj unction with a Cypre ss

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to the materials de scribed herei n. Cypress doe s not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

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