This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publicati on# 22336 Rev: CAmendment/0
Issue Date: November 28, 2000
Am29F010B
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 5.0 V ± 1 0% for r ead, eras e, and pro gram oper ations
— Simplifies system-level power requirements
■Manufactured on 0.32 µm process technology
— Compatible with Am29F010 and Am29F010A
device
■High performan c e
— 45 ns maximum access time
■Low power consumptio n
— 12 mA typical active read current
— 30 mA typical program/erase current
— <1 µA typical standby current
■Flexible sector architecture
— Eight 16 Kbyte sectors
— Any combination of sectors can be erased
— Supports full chip erase
■Sector protection
— Hardware-bas ed feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PR OM
programming equipment
■Embe dded Algorithms
— Embedded Erase algorithm automatically
pre-progr ams and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
progr ams and verifies data at specified address
■Erase Suspend/Resume
— Supports reading data from a sector not
being erased
■Minimum 1 m illi on erase c yc les guara nteed per
sector
■20-year data retention at 125°C
— Reliable operation for the life of the system
■Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
■Compatible with JEDEC standar ds
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
■Data# Polling and Toggl e Bits
— Provides a software method of detecting
program or erase cycle completion
2 Am29F010B
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash
memory organized as 131,072 bytes. The Am29F010B
is offered in 32-pin PDIP, PLCC and TSOP packages.
The byte-wide data appears on DQ0-DQ7. The de-
v i c e i s d e s i g n e d t o b e p r o g r a m m e d in-system with the
standard s ystem 5.0 Volt V CC supply. A 12.0 vo lt V PP is not
required for program or erase o pera tion s. The device can
also be programmed or erased in standard EPROM
programmers.
This de vi ce is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and benefits
of the Am29F010 and Am29F010A.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to oper ate without wait states. To eliminate b us conten-
tion the device has separate chip enable (CE#), write
enable ( WE#) and output enable (OE#) controls .
The de vice requires only a single 5. 0 v o lt po wer sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This invok es the E mbedded Pro-
gram algorithm—an internal algorithm that
automatically times the program pulse widths and
veri fies proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically
preprogr ams the arra y (i f it is not already prog rammed)
bef ore ex ecuting the er ase operation. During er ase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a prog ram
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase arc hitecture al lows memory se ctors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low VCC d etector automatically inhibits write operat ions
during power tr ansitions . T he hard ware sector protec-
tion feature disables both program and erase operations
in any combination of the sectors of memory, and is im-
plemented using standard EPROM programmers.
The system can place the de vice into the standby mode.
P o wer consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability, and cost
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
Am29F010B 3
TABLE OF CONTENTS
Product Selecto r Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29F010B Device Bus Operations .................................9
Requirements for Reading Array Data .....................................9
Writing Commands/Command Sequence s ......... .......... .. .........9
Program and Erase Operation Status ....................................10
Standby Mode .... ......... ........ ......... ................................. .........10
Output Disable Mode ..............................................................10
Table 2. Am29F010B Sector Addresses Table ...............................10
Autoselect Mode ........ .......... ..................... ..................... .. .......10
Table 3. Am29F010B Autoselect Codes (High Voltage Met hod) ....11
Sector Protection/Unprotection ...............................................11
Hardware Data Protection ......................................................11
Low V
CC
Write Inhibit ......................................................................11
Write Pulse “Glitch” Protection ........................................................11
Logical Inhibit ....... ... ....... ....... ......... ...... ... ..... ......... ....... ........ ... ..... ...1 1
Power-Up Write Inhibit ....................................................................11
Command Definitions . . . . . . . . . . . . . . . . . . . . . .12
Reading Array Data ................................................................12
Reset Command ...................... ................................. ........ ......12
Autoselect Command Sequence .............. ......... ........ ......... ....12
Byte Program Command Sequence ........... ............................12
Fig ur e 1. Pro g ra m Ope ra tion ... ....... .............. ............. ....... ..............13
Chip Erase Command Sequence ...........................................13
Sector Erase Command Sequence ........................................13
Erase Suspend/Erase Resume Commands ........ .......... .........14
Figure 2. Erase Operation ...............................................................14
Command Definitions .............................................................15
Table 4. Am29F010B Command Definitions ...................................15
Write Operation Status . . . . . . . . . . . . . . . . . . . . .16
DQ 7 : Da t a# P o ll i n g .......... ....... .. ....... ........ ....... .. ....... ....... ....... .16
Figure 3. Data# Polling Algorithm ...................................................16
DQ6: Toggle Bit I ....................................................................16
Reading Toggle Bit DQ6 .........................................................17
Figure 4. Toggle Bit Algorithm .........................................................17
DQ5: Exceeded Timing Limits ................................................17
DQ3: Sector Erase Timer .......................................................18
Table 5. Write Operation Status ..................................................... 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Figure 5. Maximum Negative Overshoot Waveform .... ..... ....... .. .... 19
Figure 6. Maximum Positive Over sh o ot Waveform ...................... .. 19
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Test Setup ....................................................................... 22
Table 6. Test Specifications ........................................................... 2 2
Key to Switching Waveforms . . . . . . . . . . . . . . . 22
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Read Operatio n s Ti mings .................... ....... .............. ...... 23
Erase and Program Operations ......................................................... 24
Figure 9. Program Operation Timings ............................................ 25
Figure 10. Chip/Sector Erase Operation Timings .......................... 2 5
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 26
Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 26
Erase and Program Operations ......................................................... 27
Alternate CE# Controlled Writes .................................................... 27
Figure 13. Alternate CE# Controlled Write Operation Tim ing s ...... 28
Erase and Programming Performance . . . . . . . 28
Latchup C haracteristic . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLC C a nd P D I P P in Capacit a nc e . . . . . . . . . . . . 29
Da ta Re t e nt i on . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
PD 032—32-Pin Plast ic DIP .. ........................................ ........ .30
PL 032—32-Pin Plast ic Leaded Chip Carrier ....................... ..31
TS 032—32-Pin Standard Thin Small Outline Package ....... ..32
TSR 032—32-Pin Standard Thin Small Outline Package ..... ..33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision A (August 12, 1999) .................................................34
Revision A+1 (September 22, 1999) ..... ........................ ........ .34
Revision A+2 (September 27, 1999) ..... ........................ ........ .34
Revision B (November 12, 1999) ............................................34
Revision C (November 28, 2000) ...........................................34
4 Am29F010B
PRODUCT SELECTOR GUIDE
Note: See the AC Characteristics section for full specifications.
BLOCK DIAGRAM
Family Part Number Am29F010B
Speed Option VCC = 5.0 V ± 5% -45
VCC = 5.0 V ± 10% -55 -70 -90 -120
Max Access Time (ns) 45 55 70 90 120
CE# Access (ns) 45 55 70 90 120
OE# Access (ns) 25 30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A16
Am29F010B 5
CONNECTION DIAGRAMS
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE#
A10
CE#
DQ7
VCC
WE#
DQ6
NC
A14
A13
DQ5
DQ4
DQ3
NC
PDIP
DQ6
NC
DQ5
DQ4
DQ3
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
VCC
WE#
NC
DQ1
DQ2
VSS
PLCC
6 Am29F010B
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard TSOP
A11
A9
A8
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Reverse TSOP
Am29F010B 7
PIN CONFIGURATION
A0–A16 = 17 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
VCC = +5.0 Volt Single Power Supply
(See Pr oduct Selector Guide f or s peed
options and voltage supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Inter nally
LOGIC SYMBOL
17
8
DQ0–DQ7
A0–A16
CE#
OE#
WE#
8 Am29F010B
ORDERING INFORMATION
Standard Products
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
Am29F010B 70 E C
TEMPERATURE RANGE
C = Comme rcial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic PDIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pino ut (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-on ly Read, Program, and Erase
Valid Combinations VCC Voltage
Am29F010B-45
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
5.0 V ± 5%
Am29F010B-55
5.0 V ± 10%
Am29F010B-70
Am29F010B-90
Am29F010B-120
Am29F010B 9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The regis ter is composed of lat ches that store
the commands, along with the address and data infor-
mation needed to execute t he c ommand. The content s
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control le vels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F010B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
tection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the pow er transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device add ress input s produc e valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To wr ite a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and O E # to VIH.
An erase oper at ion can er ase one sect or, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” cons ists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table r epresents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tabl es and timing diagrams for write operations.
Operation CE# OE# WE# Addresses
(Note 1) DQ0–DQ7
Read L L H AIN DOUT
Write L H L AIN DIN
Standby VCC ± 0.5 V X X X High-Z
Output Disable L H H X High-Z
Hardware Reset X X X X High-Z
10 Am29F010B
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more infor mation, and to each AC Charac-
teristics section in th e appropriate data sheet for timing
diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is held at VCC ± 0.5 V. (Note that this is a more
restricted voltage range than VIH.) The device enters
the TTL standby mode when CE# is held at VIH. The
dev ice requires the st andard access time (t CE) be fore it
is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Table 2. Am29F010B Sector Addresses Table
Note: All sectors are 16 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins A6,
A1, and A0 must be as shown in Autoselect Codes
(High V oltage Method) table. In addition, when verifying
sector protection, the sector address must appear on
the appropriate highest order address bi ts. Ref er to the
corresponding Sector Address Tables. The Command
Definitions tab le sho ws the remaining address bits that
are don’t care. When all necessary bits have been set
as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
Sector A16 A15 A14 Address Range
SA0 0 0 0 00000h-03FFFh
SA1 0 0 1 04000h-07FFFh
SA2 0 1 0 08000h-0BFFFh
SA3 0 1 1 0C000h-0FFFFh
SA4 1 0 0 10000h-13FFFh
SA5 1 0 1 14000h-17FFFh
SA6 1 1 0 18000h-1BFFFh
SA7 1 1 1 1C000h-1FFFFh
Am29F010B 11
Table 3. Am29F010B Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y sect or. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
secto rs.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representativ e to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protec ted
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures pre vent accidental eras ure or pro-
gramming, which might otherwise be caused by
spurious system lev el signals during VCC power-up and
power-down transitions, or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a wr ite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Description CE# OE# WE#
A16
to
A14
A13
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29F010B L L H X X VID XLXLH 20h
Sector Protec tion Ver if icat ion L L H SA X VID XLXHL
01h
(protected)
00h
(unprotected)
12 Am29F010B
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” se ctio n , next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Operations” section for more infor mation.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data. Once programming begins, how-
ever, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the au toselect mode , the r eset command
must
be written to return to reading array data.
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices codes ,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements . This method is an alternativ e to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the m anu-
facturer code. A read cycle at address XX01h retur ns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tab l es for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading arra y data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide further
controls or timings. The device automatically provides
internally generated progr am pulses and v erify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
progr am command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the stat us of the prog ram operatio n by using
DQ7or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempti ng to do so ma y halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver , a succeeding read will show that the
data is still “0”. Only erase operations can conv ert a “0”
to a “1”.
Am29F010B 13
Note: See the appropriate Command Definitions table for
program comma nd seq ue nce.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-b us-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Er ase algo-
rithm automatically preprogr ams a nd v e rifies the entire
memor y for an all zero data patter n prior to electrical
erase. The system is not required to provide any con-
trols or timings during thes e operations. The Command
Definitions table shows the address and data require-
ments f or the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7 or DQ6. See “Write Operation
Status” for infor mation on these status bits. When the
Embedded Erase algorithm is complete, the device re-
turns to reading array data and addresses are no
longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters , and to the Chip/Sector
Erase Operation Timings for t i ming waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not
require the system to preprogram
the memory prior to er ase. The Embedded Erase algo-
rithm automatically progr ams and verifies the s ector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, ot herwise the last address and comman d might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time bet ween additional sec-
tor erase commands can be assumed to be less than
50 µs, the system need not monitor DQ3. Any com-
mand during the time-out period resets the device
to reading array data. The system must rewrite the
command sequence and any additional sector ad-
dresses and commands.
The system can monitor DQ3 t o determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, all other
commands are ignored.
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arr a y dat a and addr esses are
no longer latched. The system can determine the sta-
tus of the erase oper ation b y using DQ7 or DQ6. Refer
to “Write Operation Status” for information on these
status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
14 Am29F010B
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “A C Char acteristics ” section f or par amet ers , and to
the Sector Er ase Oper ations Timing dia gr am for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend c ommand allo ws the s ystem to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and s uspends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase oper ation, the de vice requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from any sector not se-
lected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Normal read and write
timings and command definitions apply . Reading at any
address within e rase-suspended sec tors produces sta-
tus data on DQ7–DQ0. The system can use DQ7 to
determine if a sector is activ ely erasing o r is erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, t he system can once again read arr ay data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. Se e “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the s ector erase oper ati on. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Am29F010B 15
Command Definitions
Table 4. Am29F010B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory locat ion to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or
erased. Address bits A16–A14 uniquely select any sector.
Notes:
1. See Table 1 for description of bu s operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
4. No unlock or command cycles required when reading array
data.
5. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
6. The device accepts the three-cycle reset command
sequence for backward compatibility.
7. The fourth cycle of the autoselect command sequence is a
read operation.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The syste m may read in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is v alid only during a sector erase
operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2-3)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 4) 1 RA RD
Reset (Note 5) 1 XXXX F0
Reset (Note 6) 3 555 AA 2AA 55 555 F0
Autoselect
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 55 5 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 20
Sector Protect Verify
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
16 Am29F010B
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ3, DQ5, DQ6, and DQ7.
Table 5 and the following subsections describe the
functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-
mand sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. When the Embedded Program
algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the pro-
gram address to read valid status infor mation on DQ7.
If a program address falls within a protected sector,
Data# Polling on DQ7 is active for approximately 2 µs,
then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, Data# Polling produces a “1” on
DQ7. This is analogous to the complement/true datum
output described f or the Embedded Program algorithm:
the erase func tion changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for appro x imately 100 µs , the n the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 3. Data# Polling Algorithm
Am29F010B 17
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete .
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# pulse in the com-
mand sequence (prior to the program or erase
operation), and during the sector er ase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an er ase command sequence is written, if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then retur ns to reading
array data.
The Write Operation Status tab le shows the out puts for
Toggle Bit I on DQ6. Ref er to Figure 4 f or the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Char acterist ics” section for the timing diagram.
Reading Toggle Bit DQ6
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at leas t twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store t he v alue of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is n ot toggling, the device has com-
pleted the prog ram or e rase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 t hrough successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system t ask s. In this case, the syst em m ust start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 4).
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 4. Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
18 Am29F010B
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys-
tem can guarantee that the time between additional
sector erase commands will alw a ys be less t han 50 µs.
See also the “Sector Erase Command Sequence”
section.
After the sector erase command sequence is written,
the system should rea d th e stat us on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the c ommand sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands are ignored until the
erase operation is complete. If DQ3 is “0”, the device
will accept additional sector erase commands. To en-
sure the command has been accepted, the system
software should check the status of DQ3 prior to and
following each subsequent sector erase command. If
DQ3 is high on the second status check, the last com-
mand might not have been accepted. Table 5 shows
the outputs for DQ3.
Table 5. Write Operation Status
Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation DQ7
(Note 1) DQ6 DQ5
(Note 2) DQ3
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A
Embedded Erase Algorithm 0 Toggle 0 1
Erase
Suspend
Mode
Reading within Erase Suspended Sector 1 No toggle 0 N/A
Reading within Non-Erase Suspended Sector Data Data Data Data
Am29F010B 19
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.0 V
All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pin is –0.5 V . During
voltage transitions, inputs may overshoot V SS to –2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is VCC + 0.5 V. During volt-
age transi ti ons , inp ut and I/O pi ns may overs hoot to VCC
+ 2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is –0.5V. During
voltage transitions, A9 pins may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC in-
put voltage on A9 is +12.5 V which may overshoot to 14.0
V for periods up to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions abov e those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to ab solu te m axi mum ratin g co ndi tion s for
extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Case Temperature (TA) . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Case Temperature (TA) . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Case Temperature (TA) . . . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ±10% devices . . . . . . . . . .+4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 5. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 6. Maxim um Positive
Overshoot Waveform
20 Am29F010B
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Lea ka ge Cur ren t VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH 12 30 mA
ICC2 VCC Active Write Current
(Notes 2, 3, 4) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current CE# and OE# = VIH 0.4 1.0 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VID V oltage for Autoselect and Sector
Protect VCC = 5.0 V 10.5 12.5 V
VOL Output Low Volta ge IOL = 12 mA, VCC = VCC Min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
Am29F010B 21
DC CHARACTERISTICS (Continued)
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperatures (> +85°C).
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Active Current (Notes 1, 2) CE# = VIL, OE# = VIH 12 30 mA
ICC2 VCC Active Current
(Notes 2, 3, 4) CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Note 5) CE# = VCC ± 0.5 V, OE# = VIH 15µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High V oltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and
Sector Protect VCC = 5.25 V 10.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0. 85 VCC V
VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
22 Am29F010B
TEST CONDITIONS
Table 6. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
Figure 7. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -45 All others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8 V
Output timing measurement
reference levels 1.5 2.0 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
Am29F010B 23
AC CHARACTERISTICS
Read-only Operations Characteristics
Notes:
1. Not 100% tested.
2. See Figure 7 and Table 6 for test specifications.
Parameter
Symbol
Parameter Description Test Setup
Speed Options
UnitJEDEC Std -45 -55 -70 -90 -120
tAVAV tRC Read Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 45 55 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 45 55 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z
(Note 1) Max 10 15 20 20 30 ns
tGHQZ tDF Output Enable to Output High Z
(Note 1) Max 10 15 20 20 30 ns
tOEH Output Enable Hold Time
(Note 1)
Read Min 0 ns
Toggle and Data
Polling Min 10 ns
tAXQX tOH
Output Hold Time From
Addresses CE# or OE#,
Whichever Occurs First Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE tDF
tOH
Figure 8. Read Operations Timings
24 Am29F010B
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more informaiton.
Parameter Symbol
Parameter Description
Speed Options
UnitJEDEC Std -45 -55 -70 -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 35 45 45 45 50 ns
tDVWH tDS Data Setup Time Min 20 20 30 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHWL tGHWL Read Recover Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 25 30 35 45 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
tVCS VCC Set Up Time (Note 1) Min 50 µs
Am29F010B 25
AC CHARACTERISTICS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 9. Program Operati on Ti m ings
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data ( see “Write Operation Status”).
Figure 10. Chip/Sector Erase Operation Timings
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
tCH
PA
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
26 Am29F010B
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 11. Data# P olling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
tOE
DQ6
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
tACC
tRC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
Am29F010B 27
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Symbol
Parameter Description
Speed Options
UnitJEDEC Standard -45 -55 -70 -90 -120
tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 35 45 45 45 50 ns
tDVEH tDS Data Setup Time Min 20 20 30 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time (Note 1) Min 0 ns
tGHEL tGHEL Read Recover Time Before Write Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Wid th Min 2 5 30 35 45 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs
tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec
28 Am29F010B
AC CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 5.0 V VCC, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -45), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-lev el overhead is the time required to ex ecute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.
tGHEL
tWS
OE#
CE#
WE#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tWHWH1 or 2
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 13. Alternate CE# Controlled Write Operation Timings
Parameter
Limits
CommentsTyp (Note 1) Max (Note 2) Unit
Chip/Sector Erase Time 1.0 15 sec Excludes 00h programming prior to
erasure (Note 4)
Byte Programming Time 7 300 µs Excludes system-level overhead
(Note 5)
Chip Programming Time (Note 3) 0.9 6.25 sec
Am29F010B 29
LATCHUP CHARACTERISTIC
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25
°
C, f = 1.0 MHz.
PLCC AND PDIP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25
°
C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Min Max
Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter
Symbol Parameter Description Test Conditions Typ Max Unit
CIN Input Capacitance VIN = 0 4 6 pF
COUT Output Capacitance VOUT = 0 8 12 pF
CIN2 Control Pin Capacitance VPP = 0 8 12 pF
Parameter Description Test Conditions Min Unit
Minimum Pa ttern Data Retent ion Time 150°C10 Years
125°C20 Years
30 Am29F010B
PH YS ICAL DIMENSIONS
PD 032—32-Pin Plastic DIP
Dwg rev AD; 10/99
Am29F010B 31
PH YSICAL DIMENSI ONS* (contin ued)
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
32 Am29F010B
PH YSICAL DIMENSI ONS* (contin ued)
TS 032—32-Pin Standard Thin Small Outline Package
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
Am29F010B 33
PH YSICAL DIMENSI ONS* (contin ued)
TSR 032—32-Pin Standard Thin Small Outline Package
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
34 Am29F010B
REVISION SUMMARY
Revision A (August 12, 1999)
Initial release. The Am29F010B replaces the
Am29F010A data sheet (22181B+1).
Revision A+1 (September 22, 1999)
Device Bus Operations
Sector Protection/Unprotection:
Corrected the pub lica-
tion number for the programming supplement.
Revision A+2 (September 27, 1999)
Erase and Programming P erformance table
In Notes 1 and 6, corrected the erase cy cle endurance
to 1 million cycles.
Revision B (November 12, 1999)
A C Characteristics—Figure 9. Pr ogram Operations
Timing and Figure 10. Chip/Sector Erase
Operations
Deleted tGHWL and changed OE# waveform to star t at
high.
Physi cal Dimensions
Replaced figures with more detailed illustrations.
Revision C (November 28, 2000)
Global
Added table of contents. Removed Preliminary status
from document.
Ordering Informati on
Deleted bur n-in option.
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
