SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1986, Texas Instruments Incorporated
5BASIC
1
•Single Down/Up Count Control Line
•Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
•Fully Synchronous in Count Modes
•Asynchronously Presettable With Load
Control
•Package Options Include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•Dependable Texas Instruments Quality and
Reliability
description
The ’ALS190 and ’ALS191 are synchronous,
reversible up/down counters. The ’ALSL90 is a
4-bit decade counter and the ’ALS191 is a 4-bit
binary counter. Synchronous counting operation
is provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the steering logic. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple clock)
counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock input if
the enable input CTEN is low. A high at CTEN
inhibits counting. The direction of the count is
determined by the level of the down/up D/U input.
When D/U is low , the counter counts up and when
D/U is high, it counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter will be dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low
on the load input and entering the desired data at the data inputs. The output will change to agree with the data
inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N
dividers by simply modifying the count length with the preset inputs.
The CLK, D/U, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the
loading on, or current required by, clock drivers, etc., for long parallel words.
T wo outputs have been made available to perform the cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete
cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The
ripple clock output produces a low-level output pulse under those same conditions but only while the clock input
is low. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the
succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
The SN54ALS190 and SN54ALS191 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS190 and SN74ALS191 are characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
QB
QA
CTEN
D/U
QC
QD
GND
VCC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54ALS190, SN54ALS191 ...J PACKAGE
SN74ALS190, SN74ALS191 ...D OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
QA
CTEN
NC
D/U
QC
SN54ALS190, SN54ALS191 . . . FK PACKAGE
(TOP VIEW)
B
NC
D
CA
Q
GND
NC
NC–No internal connection
DQ
B
VCC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS190, SN54ALS190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
’ALS190 logic symbol†
A
B
13 RCO
3(CT=9)Z6
C5
[8]
[4]
[2]
[1]1,5D
1,2–/1,3+
G4
M3 (UP)
M2 (DOWN)
G1
7QD
6QC
2QB
3QA
MAX/MIN
12
2(CT=0)Z6
CTRDIV10
9
D
10
C
1
15
11
LOAD
14
CLK
4
CTEN
D/U 5
6,1,4
’ALS190 logic diagram (positive logic)
CTEN
D/U
CLK
LOAD
A
B
C10
9
1
15
11
14
5
4
12 MAX/MIN
13 RCO
1D
S
R
QD
7
C1
1D
S
R
QC
6
C1
C1 2QB
R
S
1D
1D
S
R
QA
3
C1
D
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
SN54ALS191, SN54ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
’ALS191 logic symbol†
13 RCO
3(CT=9)Z6
C5
[8]
[4]
[2]
[1]5D
1,2–/1,3+
G4
M3 (UP)
M2 (DOWN)
G1
7QD
6QC
2QB
3QA
MAX/MIN
12
2(CT=0)Z6
CTRDIV10
9
D
10
C
1
B
15
A
11
LOAD
14
CLK
4
CTEN
D/U 5
6,1,4
’ALS191 logic diagram (positive logic)
CTEN
D/U
CLK
LOAD
A
B
C10
9
1
15
11
14
5
4
12 MAX/MIN
13 RCO
1D
S
R
QD
7
C1
1D
S
R
QC
6
C1
C1 2QB
R
S
1D
1D
S
R
QA
3
C1
D
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
SN54ALS190, SN54ALS190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
typical load, count, and inhibit sequences
789012221098
RCO
MAX/MIN
QD
QC
QB
QA
7
Count Down
Load
InhibitCount Up
Data
Inputs
CTEN
D/U
CLOCK
D
C
B
A
LOAD
’ALS190
Illustrated below is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
SN54ALS191, SN54ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
typical load, count, and inhibit sequences
789012221098
RCO
MAX/MIN
QD
QC
QB
QA
7
Count Down
Load
InhibitCount Up
Data
Inputs
CTEN
D/U
CLOCK
D
C
B
A
LOAD
’ALS191
Illustrated below is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
fclock Clock frequency MHz
CLK high or low
tsu Setup time ns
VOL V
IIL VCC = 5.5 V, VI = 0.4 V mA
SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54ALS190, SN54ALS191 –55°C to 125°C. . . . . . . . . . . . . . . . . . .
SN74ALS190, SN74ALS191 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54ALS190
SN54ALS191 SN74ALS190
SN74ALS191 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
’ALS190 0 20 0 25
’ALS191 0 20 0 30
’AS190 25 20
twPulse duration ‘AS191 20 16.5 ns
LOAD low 25 20
Data before LOAD↑25 20
CTEN before CLK↑45 20
D/U before CLK↑45 20
LOAD inactive before CLK↑20 20
Data after LOAD↑5 5
tsu Hold time CTEN after CLK↑0 0 ns
D/U after CLK↑0 0
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS SN54ALS190
SN54ALS191 SN74AAL190
SN74ALS191 UNIT
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V
VCC = 4.5 V, IOL = 4 mA 0.25 0.5 0.25 0.4
VCC = 4.5 V, IOL = 8 mA 0.35 0.5
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
CTEN OR CLK –0.2 –0.2
All others –0.1 –0.1
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
ICC VCC = 5.5 V, All inputs at 0 V 12 22 12 22 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
FROM
(INPUT) TO
(OUTPUT)
fmax MHz
LOAD Any Q ns
ns
ns
ns
ns
ns
ns
ns
A, B, C, D Any Q
CLK RCO
CLK Any Q
CLK
CTEN
D/U
D/U
MAX/MIN
MAX/MIN
RCO
RCO
SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
switching characteristics (see Note 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
PARAMETER TA = MIN to MAX UNIT
SN54ALS190 SN74ALS190
SN54ALS191 SN74ALS191
MIN MAX MIN MAX
’ALS190 20 25
’ALS191 20 30
tPLH 737 8 30
tPHL 8 34 8 30
tPLH 425 4 21
tPHL 4 25 5 21
tPLH 524 5 20
tPHL 5 25 5 20
tPLH 326 3 18
tPHL 3 22 3 18
tPLH 837 8 31
tPHL 8 34 8 31
tPLH 12 45 15 37
tPHL 10 36 10 28
tPLH 835 8 25
tPHL 8 30 8 25
tPLH 421 4 18
tPHL 4 23 4 18
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
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