PCA85276 Automotive 40 x 4 LCD driver Rev. 2 -- 9 April 2015 Product data sheet 1. General description The PCA85276 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily cascaded for larger LCD applications. The PCA85276 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). For a selection of NXP LCD segment drivers, see Table 24 on page 46. 2. Features and benefits 1. AEC-Q100 grade 2 compliant for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 12, or 13 Internal LCD bias generation with voltage-follower buffers 40 segment drives: Up to 20 7-segment numeric characters Up to 10 14-segment alphanumeric characters Any graphics of up to 160 segments/elements 40 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption Extended temperature range up to 105 C 400 kHz I2C-bus interface May be cascaded for large LCD applications (up to 1280 segments/elements possible) No external components required The definition of the abbreviations and acronyms used in this data sheet can be found in Section 22. PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 3. Ordering information Table 1. Ordering information Type number Package PCA85276ATT Name Description Version TSSOP56 plastic thin shrink small outline package, 56 leads; body width 6.1 mm SOT364-1 3.1 Ordering options Table 2. Ordering options Type number Sales item (12NC) Orderable part number IC revision Delivery form PCA85276ATT/A 935303864118 PCA85276ATT/AJ 1 tape and reel, 13 inch 4. Marking Table 3. PCA85276 Product data sheet Marking codes Type number Marking code PCA85276ATT PCA85276TT All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 5. Block diagram %3 %3 %3 %3 6WR6 9/&' %$&.3/$1( 2873876 ',63/$<6(*0(172873876 ',63/$<5(*,67(5 /&' 92/7$*( 6(/(&725 966 &/. 6<1& 26& ',63/$< &21752//(5 /&'%,$6 *(1(5$725 &/2&.6(/(&7 $1'7,0,1* 287387%$1.6(/(&7 $1'%/,1.&21752/ ',63/$< 5$0 %/,1.(5 7,0(%$6( 26&,//$725 3&$ ,1387 ),/7(56 ,&%86 &21752//(5 &200$1' '(&2'(5 :5,7('$7$ &21752/ '$7$32,17(5$1' $872,1&5(0(17 9'' 6&/ 6'$ 68%$''5(66 &2817(5 6$ $ $ $ DDD Fig 1. Block diagram of PCA85276 PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 6. Pinning information 6.1 Pinning %3 %3 %3 9/&' %3 966 6 6$ 6 $ 6 $ 6 $ 6 26& 6 9'' 6 &/. 6 6<1& 6 6&/ 6 6'$ 6 6 3&$$77 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DDD Top view. For mechanical details, see Figure 28. Fig 2. PCA85276 Product data sheet Pinning diagram for PCA85276ATT (TSSOP56) All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 6.2 Pin description Table 4. Pin description of PCA85276ATT (TSSOP56) Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol PCA85276 Product data sheet Pin Description PCA85276ATT Type SDA 44 input/output I2C-bus serial data line SCL 45 input I2C-bus serial clock CLK 47 input/output clock line VDD 48 supply supply voltage SYNC 46 input/output cascade synchronization; if not used it must be left open OSC 49 input internal oscillator enable A0, A1 50, 51 input subaddress inputs T1 52 input dedicated testing pin; to be tied to VSS in application mode SA0 53 input I2C-bus address input VSS 54 supply ground supply voltage VLCD 55 supply LCD supply voltage BP0, BP2, BP1, BP3 56, 1, 2, 3 output LCD backplane outputs S0 to S39 4 to 43 output LCD segment outputs All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7. Functional description The PCA85276 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot-matrix displays. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. 7.1 Commands of PCA85276 The commands available to the PCA85276 are defined in Table 5. Table 5. Definition of the PCA85276 commands Bit position labeled as - is not used. Command Operation Code Reference Bit 7 6 5 4 3 2 1 mode-set C 1 0 - E B M[1:0] load-data-pointer C 0 P[5:0] device-select C 1 1 0 0 0 A[1:0] bank-select C 1 1 1 1 0 I blink-select C 1 1 1 0 AB BF[1:0] 0 Table 7 Table 8 Table 9 O Table 10 Table 11 All available commands carry a continuation bit C in their most significant bit position as shown in Figure 21. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that the command byte is the last in the transfer. Further bytes are regarded as display data (see Table 6). PCA85276 Product data sheet Table 6. C bit description Bit Symbol 7 C Value Description continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.1.1 Command: mode-set The mode-set command allows configuring the multiplex mode, the bias levels and enabling or disabling the display. Table 7. Mode-set command bit description Bit Symbol Value Description 7 C 0, 1 see Table 6 6 to 5 - 10 fixed value 4 - - unused 3 E 2 display status[1] 0 disabled (blank)[2] 1 enabled LCD bias configuration[3] B 1 to 0 0 1 3 bias 1 1 2 bias M[1:0] LCD drive mode selection 01 static; BP0 10 1:2 multiplex; BP0, BP1 11 1:3 multiplex; BP0, BP1, BP2 00 1:4 multiplex; BP0, BP1, BP2, BP3 [1] The possibility to disable the display allows implementation of blinking under external control. [2] The display is disabled by setting all backplane and segment outputs to VLCD. [3] Not applicable for static drive mode. 7.1.2 Command: load-data-pointer The load-data-pointer command defines the display RAM address where the following display data are sent to. Table 8. Load-data-pointer command bit description See Section 7.3.1. Bit Symbol Value Description 7 C 0, 1 see Table 6 6 - 0 fixed value 5 to 0 P[5:0] 000000 to 100111 6-bit binary value, 0 to 39; transferred to the data pointer to define one of forty display RAM addresses 7.1.3 Command: device-select The device-select command allows defining the subaddress counter value. Table 9. Device-select command bit description See Section 7.3.2. PCA85276 Product data sheet Bit Symbol Value Description 7 C 0, 1 see Table 6 6 to 2 - 11000 fixed value 1 to 0 A[1:0] 00 to 11 2-bit binary value, 0 to 3; transferred to the subaddress counter to define one of four hardware subaddresses All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.1.4 Command: bank-select The bank-select command controls where data is written to RAM and where it is displayed from. Table 10. Bank-select command bit description See Section 7.3.5. Bit Symbol Value Description Static 7 C 0, 1 see Table 6 6 to 2 - 11110 fixed value 1 I 0 [1] 1:2 multiplex[1] input bank selection; storage of arriving display data 0 RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 O output bank selection; retrieval of LCD display data 0 RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. 7.1.5 Command: blink-select The blink-select command allows configuring the blink mode and the blink frequency. Table 11. Blink-select command bit description See Section 7.1.5.1. Bit Symbol Value Description 7 C 0, 1 see Table 6 6 to 3 - 1110 fixed value 2 AB 1 to 0 7.1.5.1 blink mode selection 0 normal blinking[1] 1 alternate RAM bank blinking[2] BF[1:0] blink frequency selection 00 off 01 1 10 2 11 3 [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. Blinking The display blinking capabilities of the PCA85276 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 11). The blink frequencies are derived from the clock frequency. The ratio between the clock and blink frequencies depends on the blink mode selected (see Table 12). PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver An additional feature is for an arbitrary selection of LCD segments/elements to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. With the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of LCD segments/elements can blink by selectively changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 7). Table 12. Blink frequencies Blink mode Blink frequency[1] off - 1 f clk f blink = ---------768 2 f clk f blink = ------------1536 3 f clk f blink = ------------3072 [1] The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see Table 20. 7.2 Clock and frame frequency 7.2.1 Internal clock The internal logic of the PCA85276 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCA85276 in the system that are connected in cascade. 7.2.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame frequency is determined by the clock frequency (fclk). Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.2.3 Timing The PCA85276 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCA85276 in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame frequency signal. The frame frequency signal is a fixed division of the clock f clk frequency from either the internal or an external clock: f fr = ------24 PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.3 Display RAM The display RAM is a static 40 4-bit RAM which stores LCD data. There is a one-to-one correspondence between * the bits in the RAM bitmap and the LCD segments/elements * the RAM columns and the segment outputs * the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. GLVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 GLVSOD\5$0ELWV URZV EDFNSODQHRXWSXWV %3 PEH The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs; and between the bits in a RAM row and the backplane outputs. Fig 3. Display RAM bitmap When display data is transmitted to the PCA85276, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in Figure 4; the RAM filling organization depicted applies equally to other LCD types. * In static drive mode the eight transmitted data bits are placed into row 0 as one byte * In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as four successive 2-bit RAM words * In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see Section 7.3.3) * In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 55 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx /&'VHJPHQWV 6Q 6Q VWDWLF E F URZV GLVSOD\5$0 URZVEDFNSODQH RXWSXWV %3 '3 D Rev. 2 -- 9 April 2015 All information provided in this document is subject to legal disclaimers. E %3 H 6Q F 6Q '3 G 6Q D E 6Q %3 F %3 F G Q Q F [ [ [ E [ [ [ D [ [ [ I [ [ [ J [ [ [ H [ [ [ G [ [ [ '3 [ [ [ 06% /6% F E D I J H G '3 URZV GLVSOD\5$0 URZVEDFNSODQH RXWSXWV %3 Q Q Q Q D E [ [ I J [ [ H F [ [ G '3 [ [ 06% D E /6% I J H F G '3 Q URZV GLVSOD\5$0 E URZVEDFNSODQH '3 RXWSXWV %3 F [ Q Q D G J [ I H [ [ 06% /6% E '3 F D G J I H '3 %3 Q URZV GLVSOD\5$0 D URZVEDFNSODQH F %3 RXWSXWV %3 E '3 Q I H J G 06% D F E '3 I /6% H J G DDM x = data bit unchanged. Fig 4. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus PCA85276 11 of 55 (c) NXP Semiconductors N.V. 2015. All rights reserved. %3 J H Q Automotive 40 x 4 LCD driver E I PXOWLSOH[ Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWV V E\WH E\WH E\WH E\WH E\WH D 6Q 6Q %3 '3 G Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWV V E\WH E\WH E\WH J H Q %3 I PXOWLSOH[ Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWV V E\WH E\WH J 6Q Q %3 I PXOWLSOH[ %3 6Q 6Q G 6Q 6Q 6Q J H WUDQVPLWWHGGLVSOD\E\WH FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWV V E\WH I 6Q GLVSOD\5$0ILOOLQJRUGHU D 6Q 6Q /&'EDFNSODQHV NXP Semiconductors PCA85276 Product data sheet GULYHPRGH PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.3.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 8). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 4. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: * * * * In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access terminates early, then the state of the data pointer is unknown. So, the data pointer must be rewritten prior to further RAM accesses. 7.3.2 Subaddress counter The storage of display data is determined by the contents of the subaddress counter. Storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to A0 and A1. The subaddress counter value is defined by the device-select command (see Table 9). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85276 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. The hardware subaddress must not be changed while the device is being accessed on the I2C-bus interface. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.3.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in Table 13 (see Figure 4 as well). Table 13. Standard RAM filling in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 - - - - - - - - - - : If the bit at position BP2/S2 would be written by a second byte transmitted, then the mapping of the segment bits would change as illustrated in Table 14. Table 14. Entire RAM filling by rewriting in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 - - - - - - - - - - : 3 4 5 6 7 8 9 : In the case described in Table 14 the RAM has to be written entirely and BP2/S2, BP2/S5, BP2/S8 etc. have to be connected to segments/elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows: * In the first write to the RAM, bits a7 to a0 are written * The data-pointer (see Section 7.3.1 on page 12) has to be set to the address of bit a1 * In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6 * The data-pointer has to be set to the address of bit b1 * In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6 Depending on the method of writing to the RAM (standard or entire filling by rewriting), some segments/elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.3.4 Writing over the RAM address boundary In all multiplex drive modes, depending on the setting of the data pointer, it is possible to fill the RAM over the RAM address boundary. If the PCA85276 is part of a cascade the additional bits fall into the next device that also generates the acknowledge signal. If the PCA85276 is a single device or the last device in a cascade, the additional bits are discarded and no acknowledge signal is generated. 7.3.5 Bank selection 7.3.5.1 Output bank selector The output bank selector (see Table 10 on page 8) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. * In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the contents of row 1, row 2, and then row 3 * In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially * In 1:2 multiplex mode, rows 0 and 1 are selected * In static mode, row 0 is selected 7.3.5.2 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded by using the bank-select command (see Table 10). The input bank selector functions independently to the output bank selector. 7.3.5.3 RAM bank switching The PCA85276 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see Figure 5). The RAM bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver GLVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 6WDWLFGULYHPRGH GLVSOD\5$0ELWV URZV EDFNSODQHRXWSXWV %3 EDQN EDQN 0XOWLSOH[GULYHPRGH EDQN EDQN DDD Fig 5. RAM banks in static and multiplex driving mode 1:2 There are two banks; bank 0 and bank 1. Figure 5 shows the location of these banks relative to the RAM map. Input and output banks can be set independently from one another with the Bank-select command (see Table 10 on page 8). Figure 6 shows the concept. LQSXWEDQNVHOHFWLRQ FRQWUROVWKHLQSXW GDWDSDWK RXWSXWEDQNVHOHFWLRQ FRQWUROVWKHRXWSXW GDWDSDWK %$1. 0,&52&21752//(5 5$0 ',63/$< %$1. DDD Fig 6. Bank selection In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. In Figure 7 an example is shown for 1:2 multiplex drive mode where the displayed data is read from the first two rows of the memory (bank 0), while the transmitted data is stored in the second two rows of the memory (bank 1). PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 15 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver FROXPQV GLVSOD\5$0FROXPQVVHJPHQWRXWSXWV 6 RXWSXW5$0EDQN URZV WRWKH/&' GLVSOD\5$0URZV EDFNSODQHRXWSXWV %3 WRWKH5$0 LQSXW5$0EDQN DDD Fig 7. Example of the Bank-select command with multiplex drive mode 1:2 7.4 Initialization At power-on the status of the I2C-bus and the registers of the PCA85276 is undefined. Therefore the PCA85276 should be initialized as quickly as possible after power-on to ensure a proper bus communication and to avoid display artifacts. The following instructions should be accomplished for initialization: * I2C-bus (see Section 8) initialization - generating a START condition - sending 0h (1 byte) and ignoring the acknowledge - generating a STOP condition * Mode-set command (see Table 7), setting - bit E = 0 - bit B to the required LCD bias configuration - bits M[1:0] to the required LCD drive mode * Load-data-pointer command (see Table 8), setting - bits P[5:0] to 0h (or any other required address) * Device-select command (see Table 9), setting - bits A[1:0] to the required hardware subaddress (for example, 0h) * Bank-select command (see Table 10), setting - bit I to 0 - bit O to 0 * Blink-select command (see Table 11), setting - bit AB to 0 or 1 - bits BF[1:0] to 00 (or to a desired blinking mode) * writing meaningful information (for example, a logo) into the display RAM After the initialization, the display can be switched on by setting bit E = 1 with the mode-set command. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 16 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.5 Possible display configurations The possible display configurations of the PCA85276 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 15. All of these configurations can be implemented in the typical system shown in Figure 9. GRWPDWUL[ VHJPHQWZLWKGRW VHJPHQWZLWKGRWDQGDFFHQW DDD Fig 8. Example of displays suitable for PCA85276 Table 15. Selection of possible display configurations Number of Backplanes PCA85276 Product data sheet Icons Digits/Characters 7-segment[1] 14-segment[2] Dot matrix: segments/ elements 4 160 20 10 160 (4 40) 3 120 15 7 120 (3 40) 2 80 10 5 80 (2 40) 1 40 5 2 40 (1 40) [1] 7 segment display has 8 segments/elements including the decimal point. [2] 14 segment display has 16 segments/elements including decimal point and accent dot. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 17 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 9'' 5 WU &% 9/&' 9'' VHJPHQWGULYHV 6'$ /&'3$1(/ +267 0,&52 &21752//(5 6&/ 3&$ 26& $ $ EDFNSODQHV XSWR HOHPHQWV $ 6$ 966 966 DDD The resistance of the power lines must be kept to a minimum. Fig 9. Typical system configuration The host microcontroller maintains the 2-line I2C-bus communication channel with the PCA85276. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. 7.5.1 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three impedances connected between VLCD and VSS. The center impedance is bypassed by switch if the 12 bias voltage level for the 1:2 multiplex drive mode configuration is selected. 7.5.2 Display register The display register holds the display data while the corresponding multiplex signals are generated. 7.5.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 16. Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 18 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver Table 16. Biasing characteristics LCD drive mode Number of: LCD bias Backplanes Levels configuration V off RMS ------------------------V LCD V on RMS -----------------------V LCD static V on RMS D = -----------------------V off RMS 1 2 static 0 1 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 4 1 3 0.333 0.638 1.915 4 1 3 0.333 0.577 1.732 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth(off). Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on RMS = V LCD a 2 + 2a + n -----------------------------2 n 1 + a (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off RMS = V LCD a 2 - 2a + n -----------------------------2 n 1 + a (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on RMS D = ----------------------- = V off RMS 2 a + 2a + n --------------------------2 a - 2a + n (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with PCA85276 Product data sheet 1 2 bias is 1 2 21 bias is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 19 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: * 1:3 multiplex (12 bias): V LCD = 6 V off RMS = 2.449V off RMS 4 3 - = 2.309V off RMS * 1:4 multiplex (12 bias): V LCD = --------------------3 These compare with V LCD = 3V off RMS when 13 bias is used. VLCD is sometimes referred as the LCD operating voltage. 7.5.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 10. For a good contrast performance, the following rules should be followed: V on RMS V th on (4) V off RMS V th off (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation voltage Vsat. It is important to match the module properties to those of the driver in order to achieve optimum performance. 5HODWLYH7UDQVPLVVLRQ 9WK RII 2)) 6(*0(17 9WK RQ *5(< 6(*0(17 9506>9@ 21 6(*0(17 DDD Fig 10. Electro-optical characteristic: relative transmission curve of the liquid PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 20 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.5.4 LCD drive mode waveforms 7.5.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 11. 7IU /&'VHJPHQWV 9/&' %3 966 VWDWH RQ 9/&' VWDWH RII 6Q 966 9/&' 6Q 966 D :DYHIRUPVDWGULYHU 9/&' VWDWH 9 9/&' 9/&' VWDWH 9 9/&' E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) VBP0(t). Voff(RMS) = 0 V. Fig 11. Static drive mode waveforms PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 21 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.5.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85276 allows the use of 12 bias or 13 bias in this mode as shown in Figure 12 and Figure 13. 7IU 9/&' %3 /&'VHJPHQWV 9/&' 966 VWDWH 9/&' %3 VWDWH 9/&' 966 9/&' 6Q 966 9/&' 6Q 966 D :DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.354VLCD. Fig 12. Waveforms for the 1:2 multiplex drive mode with 12 bias PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 22 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7IU 9/&' %3 %3 /&'VHJPHQWV 9/&' 9/&' 966 VWDWH 9/&' 9/&' VWDWH 9/&' 966 9/&' 6Q 9/&' 9/&' 966 9/&' 6Q 9/&' 9/&' 966 D :DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9/&' 9 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 13. Waveforms for the 1:2 multiplex drive mode with 13 bias PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 23 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.5.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 14. 7IU %3 9/&' 9/&' /&'VHJPHQWV 9/&' 966 VWDWH 9/&' %3 %3 6Q 6Q 6Q VWDWH 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 D :DYHIRUPVDWGULYHU 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 14. Waveforms for the 1:3 multiplex drive mode with 13 bias PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 24 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.5.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 15. 7IU %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' /&'VHJPHQWV VWDWH VWDWH D :DYHIRUPVDWGULYHU E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 15. Waveforms for the 1:4 multiplex drive mode with 13 bias PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 25 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 7.6 Backplane and segment outputs 7.6.1 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. * In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities * In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities * In static drive mode, the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements 7.6.2 Segment outputs The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 26 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 8. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time is interpreted as a control signal (see Figure 16). 6'$ 6&/ GDWDOLQH VWDEOH GDWDYDOLG FKDQJH RIGDWD DOORZHG PED Fig 16. Bit transfer 8.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P. The START and STOP conditions are illustrated in Figure 17. 6'$ 6'$ 6&/ 6&/ 6 3 67$57FRQGLWLRQ 6723FRQGLWLRQ PEF Fig 17. Definition of START and STOP conditions 8.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 18. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 27 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 0$67(5 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 6'$ 6&/ PJD Fig 18. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. * A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte * A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered) * A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition Acknowledgement on the I2C-bus is illustrated in Figure 19. GDWDRXWSXW E\WUDQVPLWWHU QRWDFNQRZOHGJH GDWDRXWSXW E\UHFHLYHU DFNQRZOHGJH 6&/IURP PDVWHU 6 67$57 FRQGLWLRQ FORFNSXOVHIRU DFNQRZOHGJHPHQW PEF Fig 19. Acknowledgement of the I2C-bus PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 28 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 8.5 I2C-bus controller The PCA85276 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA85276 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0 and A1 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0 and A1 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.7 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the PCA85276. The entire I2C-bus slave address byte is shown in Table 17. Table 17. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 MSB 0 0 LSB 1 1 1 0 0 SA0 R/W The PCA85276 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCA85276 will respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1). Having two reserved slave addresses allows the following on the same I2C-bus: * Up to 8 PCA85276 for very large LCD applications * The use of two types of LCD multiplex drive modes The I2C-bus protocol is shown in Figure 20. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two possible PCA85276 slave addresses available. All PCA85276 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCA85276 whose SA0 inputs are set to the alternative level. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 29 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver DFNQRZOHGJH E\$$DQG$ VHOHFWHG 3&$RQO\ DFNQRZOHGJHE\ DOODGGUHVVHG 3&$ 5: VODYHDGGUHVV 6 6 $ $ & E\WH &200$1' $ QE\WH V ',63/$<'$7$ $ 3 QE\WH V XSGDWHGDWDSRLQWHUV DQGLIQHFHVVDU\ VXEDGGUHVVFRXQWHU DDD Fig 20. I2C-bus protocol After an acknowledgement, one or more command bytes follow that define the status of each addressed PCA85276. The last command byte sent is identified by resetting its most significant bit, continuation bit C (see Figure 21). The command bytes are also acknowledged by all addressed PCA85276 on the bus. 06% & /6% 5(672)23&2'( PVD Fig 21. Format of command byte After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCA85276 device. An acknowledgement after each byte is asserted only by the PCA85276 that are addressed via address lines A0 and A1. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 30 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 9. Internal circuitry 9'' 9'' 966 966 6$ 9'' &/. 6&/ 966 9'' 966 26& 966 9'' 6'$ 6<1& 966 966 9'' $$$ 966 9/&' %3%3 %3%3 966 9/&' 9/&' 6WR6 966 966 PGE Fig 22. Device protection circuits PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 31 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 10. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. 11. Limiting values Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Min Max Unit supply voltage 0.5 +6.5 V VLCD LCD supply voltage 0.5 +9.0 V VI input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0, A1, T1 0.5 +6.5 V VO output voltage on each of the pins S0 to S39, BP0 to BP3 0.5 +9.0 V II input current 10 +10 mA IO output current 10 +10 mA IDD supply current 50 +50 mA IDD(LCD) LCD supply current 50 +50 mA ISS ground supply current 50 +50 mA Ptot total power dissipation - 400 mW Po output power VESD electrostatic discharge voltage latch-up current Ilu Tstg storage temperature Tamb ambient temperature Conditions - 100 mW HBM [1] - 5000 V CDM [2] - 2000 V VLU = 11.5 V [3] - 200 mA [4] 55 +150 C 40 +105 C operating device [1] Pass level; Human Body Model (HBM), according to Ref. 8 "JESD22-A114" [2] Pass level; Charged-Device Model (CDM), according to Ref. 9 "JESD22-C101" [3] Pass level; latch-up testing according to Ref. 10 "JESD78" at maximum ambient temperature (Tamb(max)). [4] According to the store and transport requirements (see Ref. 14 "UM10569") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 12. Static characteristics Table 19. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit supply voltage VLCD 6.5 V 1.8 - 5.5 V VLCD > 6.5 V 2.5 - 5.5 V VDD < 2.5 V 2.5 - 6.5 V 2.5 - 8.0 V - 3.5 7 A - 2.7 - A - 23 32 A - 13 - A VSS - 0.3VDD V 0.7VDD - VDD V on pins CLK and SYNC 1 - - mA on pin SDA 3 - - mA Supplies VDD VLCD LCD supply voltage VDD 2.5 V supply current IDD fclk(ext) = 1536 Hz [1][2] VDD = 3.0 V; Tamb = 25 C IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [1] VLCD = 3.0 V; Tamb = 25 C Logic[3] VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V [4][5] IOH(CLK) HIGH-level output current on pin CLK output source current; VOH = 4.6 V; VDD = 5 V 1 - - mA IL leakage current VI = VDD or VSS; on pins CLK, SCL, SDA, A0, A1, T1, SA0 1 - +1 A IL(OSC) leakage current on pin OSC VI = VDD 1 - +1 A CI input capacitance - - 7 pF 100 - +100 mV on pins BP0 to BP3 - 1.5 - k on pins S0 to S39 - 6.0 - k [6] LCD outputs VO output voltage variation on pins BP0 to BP3 and S0 to S39 RO output resistance VLCD = 5 V [7] [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] For typical values, see Figure 23. [3] The I2C-bus interface of the PCA85276 is 5 V tolerant. [4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 18 (see Figure 22 as well). [5] Propagation delay of driver between clock (CLK) and LCD driving signals. [6] Periodically sampled, not 100 % tested. [7] Outputs measured one at a time. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 33 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver DDO ,'' $ 9'' 9 Tamb = 30 C; 1:4 multiplex drive mode; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected; I2C-bus inactive. Fig 23. Typical IDD with respect to VDD PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 34 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 13. Dynamic characteristics Table 20. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock fclk(int) internal clock frequency fclk(ext) external clock frequency ffr frame frequency [1] 3505 4800 6240 Hz 960 - 6720 Hz internal clock 146 200 260 Hz external clock 40 - 280 Hz tclk(H) HIGH-level clock time 60 - - s tclk(L) LOW-level clock time 60 - - s - 30 - ns Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL SYNC LOW time tPD(drv) driver propagation delay VLCD = 5 V [2] 1 - - s - - 30 s I2C-bus[3] Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s fSCL < 125 kHz - - 1.0 s tf fall time of both SDA and SCL signals - - 0.3 s Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns on the I2C-bus [1] Typical output duty factor: 50 % measured at the CLK output pin. [2] Not tested in production. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 35 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. IFON WFON + WFON / 9'' &/. 9'' 9'' 6<1& 9'' W3' 6<1&B1 W6<1&B1/ %3Q6Q W3' GUY DDD Fig 24. Driver timing waveforms 6'$ W%8) W/2: WI 6&/ W+'67$ WU W+''$7 W+,*+ W68'$7 6'$ W6867$ W68672 PJD Fig 25. I2C-bus timing waveforms PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 36 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 14. Application information 14.1 Cascaded operation Large display configurations of up to 8 PCA85276 can be recognized on the same I2C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable I2C-bus slave address (SA0). Table 21. Addressing cascaded PCA85276 Cluster Bit SA0 Pin A1 Pin A0 Device 1 0 0 0 0 0 1 1 1 0 2 1 1 3 0 0 4 0 1 5 1 0 6 1 1 7 2 1 When cascaded PCA85276 are synchronized, they can share the backplane signals from one of the devices in the cascade. The other PCA85276 of the cascade contribute additional segment outputs. The backplanes can either be connected together to enhance the drive capability or some can be left open-circuit (such as the ones from the slave in Figure 26) or just some of the master and some of the slave will be taken to facilitate the layout of the PCB. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 37 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 9'' 9/&' 6'$ VHJPHQWGULYHV 6&/ 6<1& 3&$ &/. %3WR%3 RSHQFLUFXLW 26& $ $ $ 6$ 966 /&'3$1(/ 9/&' 9'' 5 WU &E 9'' 9/&' VHJPHQWGULYHV 6'$ +267 0,&52 &21752//(5 6&/ 6<1& 3&$ &/. %3WR%3 26& $ 966 EDFNSODQHV $ $ 6$ 966 DDD (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 26. Cascaded PCA85276 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCA85276. Synchronization is guaranteed after a power-on and initialization. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex drive mode when PCA85276 with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCA85276 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCA85276 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCA85276 are shown in Figure 27. The PCA85276 can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. Figure 27 shows the timing of the synchronization signals. Only one master but multiple slaves are allowed in a cascade. All devices in the cascade have to use the same clock whether it is supplied externally or provided by the master. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 38 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver If an external clock source is used, all PCA85276 in the cascade must be configured such as to receive the clock from that external source (pin OSC connected to VDD). Thereby it must be ensured that the clock tree is designed such that on all PCA85276 the clock propagation delay from the clock source to all PCA85276 in the cascade is as equal as possible since otherwise synchronization artifacts may occur. In mixed cascading configurations, care has to be taken that the specifications of the individual cascaded devices are always met. 7IU IIU %3 6<1& D VWDWLFGULYHPRGH %3 ELDV %3 ELDV 6<1& E PXOWLSOH[GULYHPRGH %3 ELDV 6<1& F PXOWLSOH[GULYHPRGH %3 ELDV 6<1& G PXOWLSOH[GULYHPRGH PJO Fig 27. Synchronization of the cascade for the various PCA85276 drive modes 15. Test information 15.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 39 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 16. Package outline 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ( ' $ ; F +( \ Y 0 $ = 4 $ $ $ SLQLQGH[ $ /S / GHWDLO; Z 0 ES H PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 28. Package outline SOT364-1 (TSSOP56) of PCA85276ATT PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 40 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 41 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 18. Packing information 18.1 Tape and reel information For tape and reel packing information, please see Ref. 12 "SOT364-1_118" on page 49. 19. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 19.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 19.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 19.3 Wave soldering Key characteristics in wave soldering are: PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 42 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities 19.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23 Table 22. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 23. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29. PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 43 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 20. Footprint information PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 44 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH 627 +[ *[ 3 +\ *\ %\ $\ & ' [ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\ VRWBIU Fig 30. Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCA85276ATT PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 45 of 55 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA85276 Product data sheet 21. Appendix 21.1 LCD segment driver selection Table 24. Selection of LCD segment drivers Type name Number of elements at MUX ffr (Hz) Interface Package AECQ100 PCA8553DTT 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 I2C / SPI TSSOP56 Y PCA8546ATT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 I2C TSSOP56 Y PCA8546BTT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 SPI TSSOP56 Y 1.8 to 5.5 2.5 to 9 60 to 300[1] Y 40 to 95 I2C TQFP64 Y 60 to 300[1] Y Y 40 to 95 SPI TQFP64 Y N N 40 to 85 I2C LQFP80 N N 40 to 95 I2C LQFP80 Y Y 40 to 105 I2C LQFP80 Y TSSOP56 N 88 - - - Rev. 2 -- 9 April 2015 All information provided in this document is subject to legal disclaimers. PCA8547BHT 44 88 176 - - - 1.8 to 5.5 2.5 to 9 PCF85134HL 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 PCA85134H PCA8543AHL 60 60 - 176 - 1:9 VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. 1:2 1:3 44 1:6 1:8 VLCD (V) 1:1 PCA8547AHT 1:4 VDD (V) 120 180 240 120 - 240 - - - 1.8 to 5.5 2.5 to 8 2.5 to 5.5 2.5 to 9 82 Y N 60 to 300[1] 300[1] Y PCF8545ATT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to N N 40 to 85 I2C PCF8545BTT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] N N 40 to 85 SPI TSSOP56 N PCF8536AT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 85 I2C TSSOP56 N 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 85 SPI TSSOP56 N 300[1] TSSOP56 Y PCF8536BT - - - 176 252 320 - - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to N N 40 to 95 PCA8536BT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 SPI TSSOP56 Y PCF8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 85 I2C TQFP64 N 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 85 SPI TQFP64 N 300[1] PCF8537BH 44 88 - 176 276 352 - 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to Y Y 40 to 95 TQFP64 Y PCA8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 95 SPI TQFP64 Y PCA9620H 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 105 I2C LQFP80 Y 2.5 to 5.5 2.5 to 9 300[1] Y 40 to 105 I2C Bare die Y PCA9620U 60 120 - 240 320 480 - 60 to Y PCF8576DU 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N PCF8576EUG 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N N 40 to 105 I2C Bare die Y N 40 to 85 I2C Bare die N N 40 to 95 I2C Bare die Y PCA8576FUG PCF85133U PCA85133U 40 80 80 80 120 160 - 160 240 320 160 240 320 - - - 1.8 to 5.5 2.5 to 8 200 N 1.8 to 5.5 2.5 to 6.5 82, 110[2] 1.8 to 5.5 2.5 to 8 110[2] 82, N N PCA85276 46 of 55 (c) NXP Semiconductors N.V. 2015. All rights reserved. PCA8537AH I2C Automotive 40 x 4 LCD driver PCA8536AT I2C xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Selection of LCD segment drivers ...continued Type name Number of elements at MUX ffr (Hz) VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. AECQ100 PCA85233UG 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220[2] N N 40 to 105 I2C Bare die Y PCF85132U 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90[1] N N 40 to 85 I2C Bare die N Y 40 to 105 I2C Bare die Y N 40 to 95 I2C Bare die Y N N 40 to 95 I2C Bare die Y Y Y 40 to 85 I2C / SPI Bare die N Y 40 to 105 I2C Bare die Y PCA85132U 408 - 160 320 480 640 - PCA85232U 160 320 480 640 - PCF8538UG 102 204 - PCA8538UG 102 204 - Rev. 2 -- 9 April 2015 All information provided in this document is subject to legal disclaimers. [1] Software programmable. [2] Hardware selectable. - 1:9 Interface Package 1:2 1:3 102 204 - 1:6 1:8 VLCD (V) 1:1 PCA8530DUG 1:4 VDD (V) - 2.5 to 5.5 4 to 12 1.8 to 5.5 1.8 to 8 1.8 to 5.5 1.8 to 8 45 to 300[1] 60 to 90[1] 117 to 176[1] 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] 408 612 816 918 2.5 to 5.5 4 to 12 300[1] 45 to Y N Y / SPI / SPI NXP Semiconductors PCA85276 Product data sheet Table 24. PCA85276 Automotive 40 x 4 LCD driver 47 of 55 (c) NXP Semiconductors N.V. 2015. All rights reserved. PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 22. Abbreviations Table 25. Acronym PCA85276 Product data sheet Abbreviations Description AEC Automotive Electronics Council CMOS Complementary Metal-Oxide Semiconductor CDM Charged Device Model DC Direct Current HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LCD Liquid Crystal Display LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board RAM Random Access Memory RC Resistance and Capacitance RMS Root Mean Square SCL Serial CLock line SDA Serial DAta Line SMD Surface-Mount Device All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 48 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 23. References [1] AN10365 -- Surface mount reflow soldering description [2] AN10853 -- ESD and EMC sensitivity of IC [3] AN11267 -- EMC and system level ESD design guidelines for LCD drivers [4] AN11494 -- Cascading NXP LCD segment drivers [5] IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices [6] IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena [7] IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [8] JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [9] JESD22-C101 -- Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [10] JESD78 -- IC Latch-Up Test [11] JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [12] SOT364-1_118 -- TSSOP56; Reel pack; SMD, 13", packing information [13] UM10204 -- I2C-bus specification and user manual [14] UM10569 -- Store and transport requirements PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 49 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 24. Revision history Table 26. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA85276 v.2 20150409 Product data sheet - PCA85276 v.1 Modifications: PCA85276 v.1 PCA85276 Product data sheet * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * * * * Legal texts have been adapted to the new company name where appropriate. Changed pin configuration due to redesign Enhanced SYNC pin description in Table 4 Changed typical value of IDD and IDD(LCD) in Table 19 Adjusted description of initialization (Section 7.4) 20140211 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 - (c) NXP Semiconductors N.V. 2015. All rights reserved. 50 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 25. Legal information 25.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 25.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 25.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA85276 Product data sheet Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 51 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 25.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP Semiconductors N.V. 26. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 52 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 27. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description of PCA85276ATT (TSSOP56) . .5 Definition of the PCA85276 commands . . . . . . .6 C bit description . . . . . . . . . . . . . . . . . . . . . . . . .6 Mode-set command bit description . . . . . . . . . .7 Load-data-pointer command bit description . . . .7 Device-select command bit description . . . . . . .7 Bank-select command bit description . . . . . . . .8 Blink-select command bit description . . . . . . . . .8 Blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .9 Standard RAM filling in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Entire RAM filling by rewriting in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Selection of possible display configurations . . .17 Biasing characteristics . . . . . . . . . . . . . . . . . . .19 I2C slave address byte . . . . . . . . . . . . . . . . . . .29 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32 Static characteristics . . . . . . . . . . . . . . . . . . . .33 Dynamic characteristics . . . . . . . . . . . . . . . . . .35 Addressing cascaded PCA85276 . . . . . . . . . .37 SnPb eutectic process (from J-STD-020D) . . .43 Lead-free process (from J-STD-020D) . . . . . .43 Selection of LCD segment drivers . . . . . . . . . .46 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .48 Revision history . . . . . . . . . . . . . . . . . . . . . . . .50 PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 53 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 28. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Block diagram of PCA85276 . . . . . . . . . . . . . . . . .3 Pinning diagram for PCA85276ATT (TSSOP56) . .4 Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .10 Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus . . . . . . . . . . . . . . . . 11 RAM banks in static and multiplex driving mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Example of the Bank-select command with multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .16 Example of displays suitable for PCA85276 . . . .17 Typical system configuration . . . . . . . . . . . . . . . .18 Electro-optical characteristic: relative transmission curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .20 Static drive mode waveforms . . . . . . . . . . . . . . . .21 Waveforms for the 1:2 multiplex drive mode with 12 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Waveforms for the 1:2 multiplex drive mode with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Waveforms for the 1:3 multiplex drive mode with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Waveforms for the 1:4 multiplex drive mode with 13 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Definition of START and STOP conditions. . . . . .27 System configuration . . . . . . . . . . . . . . . . . . . . . .28 Acknowledgement of the I2C-bus . . . . . . . . . . . .28 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .30 Format of command byte . . . . . . . . . . . . . . . . . . .30 Device protection circuits . . . . . . . . . . . . . . . . . . .31 Typical IDD with respect to VDD . . . . . . . . . . . . . .34 Driver timing waveforms . . . . . . . . . . . . . . . . . . .36 I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .36 Cascaded PCA85276 configuration. . . . . . . . . . .38 Synchronization of the cascade for the various PCA85276 drive modes . . . . . . . . . . . . . . . . . . . .39 Package outline SOT364-1 (TSSOP56) of PCA85276ATT . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCA85276ATT . . . . . .45 PCA85276 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 9 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 54 of 55 PCA85276 NXP Semiconductors Automotive 40 x 4 LCD driver 29. Contents 1 2 3 3.1 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.5.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.5.1 7.3.5.2 7.3.5.3 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.3.1 7.5.4 7.5.4.1 7.5.4.2 7.5.4.3 7.5.4.4 7.6 7.6.1 7.6.2 8 8.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Commands of PCA85276 . . . . . . . . . . . . . . . . . 6 Command: mode-set . . . . . . . . . . . . . . . . . . . . 7 Command: load-data-pointer . . . . . . . . . . . . . . 7 Command: device-select . . . . . . . . . . . . . . . . . 7 Command: bank-select. . . . . . . . . . . . . . . . . . . 8 Command: blink-select . . . . . . . . . . . . . . . . . . . 8 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clock and frame frequency. . . . . . . . . . . . . . . . 9 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 12 RAM writing in 1:3 multiplex drive mode. . . . . 13 Writing over the RAM address boundary . . . . 14 Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 14 Output bank selector . . . . . . . . . . . . . . . . . . . 14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 14 RAM bank switching . . . . . . . . . . . . . . . . . . . . 14 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Possible display configurations . . . . . . . . . . . 17 LCD bias generator . . . . . . . . . . . . . . . . . . . . 18 Display register . . . . . . . . . . . . . . . . . . . . . . . . 18 LCD voltage selector . . . . . . . . . . . . . . . . . . . 18 Electro-optical performance . . . . . . . . . . . . . . 20 LCD drive mode waveforms . . . . . . . . . . . . . . 21 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 21 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 22 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 24 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 25 Backplane and segment outputs . . . . . . . . . . 26 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 26 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 26 Characteristics of the I2C-bus . . . . . . . . . . . . 27 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 13 14 14.1 15 15.1 16 17 18 18.1 19 19.1 19.2 19.3 19.4 20 21 21.1 22 23 24 25 25.1 25.2 25.3 25.4 26 27 28 29 START and STOP conditions. . . . . . . . . . . . . System configuration . . . . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Cascaded operation. . . . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tape and reel information . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Footprint information . . . . . . . . . . . . . . . . . . . Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD segment driver selection . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 29 29 31 32 32 33 35 37 37 39 39 40 41 42 42 42 42 42 42 43 44 46 46 48 49 50 51 51 51 51 52 52 53 54 55 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 April 2015 Document identifier: PCA85276 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: PCA85276ATT/AJ