CD74HC126E96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS144A

Features

• Three-State Outputs

• Separate Output Enable Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC126 and ’HCT126 contain four independent three-

state buffers, each having its own output enable input, which

when “low” puts the output in the high-impedance state.

Pinout

CD54HC126, CD54HC126

(CERDIP)

CD74HC126, CD74HC126

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC126F3A -55 to 125 14 Ld CERDIP

CD74HC126E -55 to 125 14 Ld PDIP

CD74HC126M -55 to 125 14 Ld SOIC

CD54HCT126F3A -55 to 125 14 Ld CERDIP

CD74HCT126E -55 to 125 14 Ld PDIP

CD74HCT126M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local TI sales office

or customer service for ordering information.

1OE

2OE

GND

VCC

4OE

3OE

November 1997 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC126,

CD54/74HCT126

High Speed CMOS Logic

Quad Buffer, Three-State

[ /Title

(CD74

HC126

CD74

HCT12

Sub-

ect

(High

Speed

CMOS

Logic

Quad

Buffer,

Three-

State)

Functional Diagram

Logic Diagram

TRUTH TABLE

INPUTS OUTPUTS

nA nOE nY

HHH

LHL

XLZ

NOTE:

H = High Voltage Level

L = Low Voltage Level

X = Don’t Care

Z = High Impedance, OFF State

2OE

4OE

GND = 7

VCC = 14

1OE

3OE

nOE

CD54/74HC126, CD54/74HCT126

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or

VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or

VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Le v el Output

Voltage

TTL Loads

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

CD54/74HC126, CD54/74HCT126

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

Three-State Leakage

Current IOZ VIL or

VIH -6--±0.5 - ±5-±10 µA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2-- 2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or

VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-6 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or

VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

6 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC to

GND 0 5.5 - - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 4)

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

Three-State Leakage

Current IOZ VIL or

VIH - 5.5 - - ±0.5 - ±5-±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nA, nOE 1

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical

Speciﬁcations table, e.g., 360µA max at 25oC.

CD54/74HC126, CD54/74HCT126

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

HC TYPES

Propagation Delay Data

to Outputs tPLH, tPHL CL= 50pF 2 - 100 125 150 ns

4.5 - 20 25 30 ns

CL= 15pF 5 8 - - - ns

CL = 50pF 6 - 17 21 36 ns

Enable Dela y Time tPZL, tPZH CL= 50pF 2 - 125 155 190 ns

4.5 - 25 31 38 ns

CL= 15pF 5 10 - - - ns

CL = 50pF 6 - 21 26 32 ns

Disabling Delay Time tPLZ, tPHZ CL = 50pF 2 - 125 155 190 ns

CL= 50pF 4.5 - 25 31 38 ns

CL= 15pF 5 10 - - - ns

CL = 50pF 6 - 21 26 32 ns

Output Transition Times tTLH, tTHL CL= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns

Input Capacitance CI---1010 10pF

Three-State Output

Capacitance CO---2020 20pF

Power Dissipation

Capacitance

(Notes 5, 6)

CPD - 5 30 - - - pF

HCT TYPES

Propagation Delay Time

to Outputs tPLH, tPHL CL= 50pF 4.5 - 24 30 36 ns

CL= 15pF 5 9 - - - ns

Output Enable Time tPZL, tPZH CL= 50pF 4.5 - 25 31 38 ns

CL= 15pF 5 10 - - - ns

Output Disabling Time tPLZ, tPHZ CL= 50pF 4.5 - 28 35 42 ns

CL= 15pF 5 11 - - - ns

Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 12 15 18 ns

Input Capacitance CI---1010 10pF

Three-State Output

Capacitance CO---2020 20pF

Power Dissipation

Capacitance

(Notes 5, 6)

CPD - 5 36 - - - pF

NOTES:

5. CPD is used to determine the dynamic power consumption, per multiplexer.

6. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CD54/74HC126, CD54/74HCT126

Test Circuits and Waveforms

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

50% 10%

90%

GND

VCC

10%

90% 50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

6ns 6ns

tPZH

tPHZ

tPZL

tPLZ

0.3

2.7

GND

10%

90%

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED OUTPUTS

DISABLED OUTPUTS

ENABLED

tr6ns

tPZH

tPHZ

tPZL

tPLZ

6ns tf

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR tPLZ AND tPZL

GND FOR tPHZ AND tPZH

OUTPUT

RL = 1kΩ

50pF

CD54/74HC126, CD54/74HCT126

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.