1
LTC1857/LTC1858/LTC1859
185789f
8-Channel, 12-/14-/16-Bit,
100ksps SoftSpan A/D Converters
with Shutdown
The LTC
®
1857/LTC1858/LTC1859 are 8-channel, low
power, 12-/14-/16-bit, 100ksps, analog-to-digital con-
verters (ADCs). These SoftSpan
TM
ADCs can be software-
programmed for 0V to 5V, 0V to 10V, ±5V or ±10V input
spans and operate from a single 5V supply. The 8-chan-
nel multiplexer can be programmed for single-ended
inputs or pairs of differential inputs or combinations of
both. In addition, all channels are fault protected to ±25V.
A fault condition on any channel will not affect the
conversion result of the selected channel.
An onboard high performance sample-and-hold and pre-
cision reference minimize external components. The low
40mW power dissipation is made even more attractive
with two user selectable power shutdown modes. DC speci-
fications include ±3LSB INL for the LTC1859, ±1.5LSB
INL for the LTC1858 and ±1LSB for the LTC1857.
The internal clock is trimmed for 5µs maximum conver-
sion time and the sampling rate is guaranteed at 100ksps.
A separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
■
Sample Rate: 100ksps
■
8-Channel Multiplexer with ±25V Protection
■
Single 5V Supply
■
Software-Programmable Input Ranges:
0V to 5V, 0V to 10V, ±5V or ±10V
Single Ended or Differential
■
±3LSB INL for the LTC1859, ±1.5LSB INL for the
LTC1858, ±1LSB INL for the LTC1857
■
Power Dissipation: 40mW (Typ)
■
SPI/MICROWIRE
TM
Compatible Serial I/O
■
Power Shutdown: Nap and Sleep
■
Signal-to-Noise Ratio: 87dB (Typ) for the LTC1859
■
Operates with Internal or External Reference
■
Internal Synchronized Clock
■
28-Pin SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
MUXOUT
+
MUXOUT
–
ADC
+
ADC
–
AGND1
CONVST
RD
SCK
SDI
DGND
SDO
BUSY
OV
DD
DV
DD
AV
DD
AGND3
AGND2
REFCOMP
V
REF
LTC1857/
LTC1858/
LTC1859
SOFTWARE-PROGRAMMABLE
SINGLE-ENDED OR
DIFFERENTIAL INPUTS
(0V TO 5V, 0V TO 10V,
±5V OR ±10V)
10µF
10µF1µF
10µF
3V TO 5V
5V
5V
2.5V
10µF
µP
CONTROL
LINES
100kHz, 12-Bit/14-Bit/16-Bit Sampling ADC
■
Industrial Process Control
■
Multiplexed Data Acquisition Systems
■
High Speed Data Acquisition for PCs
■
Digital Signal Processing
SoftSpan is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
CODE
–32768
INL (LSB)
0
0.5
1.0
0
1859 TA02
–0.5
–1.0
–2.0 –16384 16384 32767
–1.5
2.0
1.5
LTC1859 Typical INL Curve
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1857/LTC1858/LTC1859
185789f
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
IS
Supply Voltage (OV
DD
= DV
DD
= AV
DD
= V
DD
) ........... 6V
Ground Voltage Difference
DGND, AGND1, AGND2, AGND3 ...................... ±0.3V
Analog Input Voltage
ADC
+
, ADC
–
(Note 3) ...................(AGND1 – 0.3V) to (AV
DD
+ 0.3V)
CH0-CH7, COM .................................................. ±25V
Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10V
Digital Output Voltage .... (DGND – 0.3V) to (DV
DD
+ 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1857C/LTC1858C/LTC1859C ............ 0°C to 70°C
LTC1857I/LTC1858I/LTC1859I .......... –40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°CT
JMAX
= 110°C, θ
JA
= 95°C/W
(Notes 1, 2)
ORDER PART
NUMBER
LTC1857CG
LTC1857IG
LTC1858CG
LTC1858IG
LTC1859CG
LTC1859IG
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PACKAGE/ORDER I FOR ATIO
UU
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
MUXOUT
+
MUXOUT
–
ADC
+
ADC
–
AGND1
CONVST
RD
SCK
SDI
DGND
SDO
BUSY
OV
DD
DV
DD
AV
DD
AGND3
AGND2
REFCOMP
V
REF
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
MUXOUT connected to ADC inputs. (Notes 5, 6)
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
WU
LTC1857 LTC1858 LTC1859
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution ●12 14 16 Bits
No Missing Codes ●12 14 15 Bits
Transition Noise 0.06 0.26 1 LSB
RMS
Integral Linearity Error (Notes 7, 15) ●±1±1.5 ±3LSB
Differential Linearity Error (Note 15) ●–1 1 –1 1.5 –2 4 LSB
Bipolar Zero Error (Note 8) ●±9±17 ±28 LSB
Bipolar Zero Error Drift ±0.1 ±0.1 ±0.1 ppm/°C
Bipolar Zero Error Match ±4±6±10 LSB
Unipolar Zero Error (Note 8) ●±6±15 ±25 LSB
Unipolar Zero Error Drift ±1±1±1 ppm/°C
Unipolar Zero Error Match ±1.2 ±2±8LSB
Bipolar Full-Scale Error External Reference (Note 11) ●±0.35 ±0.15 ±0.1 %
Internal Reference (Note 11) ±0.45 ±0.40 ±0.4 %
Bipolar Full-Scale Error Drift External Reference ±2.5 ±2.5 ±2.5 ppm/°C
Internal Reference ±7±7±7 ppm/°C
Bipolar Full-Scale Error Match ±5±10 ±15 LSB
Unipolar Full-Scale Error External Reference (Note 11) ●±0.45 ±0.25 ±0.20 %
Internal Reference (Note 11) ±0.75 ±0.85 ±0.75 %
Unipolar Full-Scale Error Drift External Reference ±2.5 ±2.5 ±2.5 ppm/°C
Internal Reference ±7±7±7 ppm/°C
Unipolar Full-Scale Error Match ±5±12 ±15 LSB
Input Common Mode Range Unipolar Mode ●0 to 10 0 to 10 0 to 10 V
Bipolar Mode ●±10 ±10 ±10 V
Input Common Mode Rejection Ratio 96 96 96 dB
3
LTC1857/LTC1858/LTC1859
185789f
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
A ALOG I PUT
UU
PARAMETER CONDITIONS MIN TYP MAX UNITS
Analog Input Range CH0 to CH7, COM 0 to 5, 0 to 10 V
±5, ±10 V
ADC
+
, ADC
–
(Note 3) 0 to 2.048 V
0 to 4.096 V
ADC
–
±1.024 V
ADC
–
±2.048 V
Impedance CH0 to CH7, COM
Unipolar 42 kΩ
Bipolar 31 kΩ
MUXOUT
+
, MUXOUT
–
Unipolar 10 kΩ
Bipolar 5 kΩ
ADC
+
, ADC
–
Hi-Z kΩ
Capacitance CH0 to CH7, COM 5 pF
Sample Mode ADC
+
, ADC
–
0V to 2.048V, ±1.024V 24 pF
0V to 4.096V, ±2.048V 12 pF
Hold Mode ADC
+
, ADC
–
4pF
Input Leakage Current ADC
+
, ADC
–
, CONVST = Low ●±1µA
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. MUXOUT connected to ADC inputs. (Notes 5 and 12)
LTC1857 LTC1858 LTC1859
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 74 83 87 dB
THD Total Harmonic Distortion 1kHz Input Signal, –101 –101 –101 dB
First Five Harmonics
Peak Harmonic or Spurious Noise 1kHz Input Signal –103 –103 –103 dB
Channel-to-Channel Isolation 1kHz Input Signal –120 –120 –120 dB
–3dB Input Bandwidth 1 1 1 MHz
Aperture Delay –70 –70 –70 ns
Aperture Jitter 60 60 60 ps
Transient Response Full-Scale Step 4 4 4 µs
(Note 9)
Overvoltage Recovery (Note 13) 150 150 150 ns
DY A IC ACCURACY
U
W
4
LTC1857/LTC1858/LTC1859
185789f
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 ●2.475 2.50 2.525 V
V
REF
Output Temperature Coefficient I
OUT
= 0 ±10 ppm/°C
V
REF
Output Impedance –0.1mA ≤ I
OUT
≤ 0.1mA 8 kΩ
V
REFCOMP
Output Voltage I
OUT
= 0 4.096 V
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 5pF
V
OH
High Level Output Voltage V
DD
= 4.75V, I
O
= –10µA, OV
DD
= V
DD
4.74 V
V
DD
= 4.75V, I
O
= –200µA, OV
DD
= V
DD
●4V
V
OL
Low Level Output Voltage V
DD
= 4.75V, I
O
= 160µA, OV
DD
= V
DD
0.05 V
V
DD
= 4.75V, I
O
= 1.6mA, OV
DD
= V
DD
●0.10 0.4 V
I
OZ
Hi-Z Output Leakage V
OUT
= 0V to V
DD
, RD = High ●±10 µA
C
OZ
Hi-Z Output Capacitance RD = High 15 pF
I
SOURCE
Output Source Current V
OUT
= 0V –10 mA
I
SINK
Output Sink Current V
OUT
= V
DD
10 mA
I TER AL REFERE CE CHARACTERISTICS
UU U
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
PARAMETER CONDITIONS MIN TYP MAX UNITS
Positive Supply Voltage (Notes 9 and 10) 4.75 5.00 5.25 V
Positive Supply Current ●8.0 13 mA
Nap Mode 5.5 8 mA
Sleep Mode CONVST = 0V or 5V 8.0 15 µA
Power Dissipation 40.0 mW
Nap Mode 27.5 mW
Sleep Mode CONVST = 0V or 5V 40.0 µW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
WU
5
LTC1857/LTC1858/LTC1859
185789f
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
UW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency Through CH0 to CH7 Inputs ●100 kHz
Through ADC
+
, ADC
–
Only 166 kHz
t
CONV
Conversion Time ●45µs
t
ACQ
Acquisition Time Through CH0 to CH7 Inputs ●4µs
Through ADC
+
, ADC
–
Only 1 µs
f
SCK
SCK Frequency (Note 14) ●0 20 MHz
t
r
SDO Rise Time See Test Circuits 6 ns
t
f
SDO Fall Time See Test Circuits 6 ns
t
1
CONVST High Time ●40 ns
t
2
CONVST to BUSY Delay C
L
= 25pF, See Test Circuits ●15 30 ns
t
3
SCK Period ●50 ns
t
4
SCK High ●10 ns
t
5
SCK Low ●10 ns
t
6
Delay Time, SCK↓ to SDO Valid C
L
= 25pF, See Test Circuits ●25 45 ns
t
7
Time from Previous SDO Data Remains C
L
= 25pF, See Test Circuits ●520 ns
Valid After SCK↓
t
8
SDO Valid After RD↓C
L
= 25pF, See Test Circuits ●11 30 ns
t
9
RD↓ to SCK Setup Time ●20 ns
t
10
SDI Setup Time Before SCK↑●0ns
t
11
SDI Hold Time After SCK↑●7ns
t
12
SDO Valid Before BUSY↑RD = Low, C
L
= 25pF, See Test Circuits ●520 ns
t
13
Bus Relinquish Time See Test Circuits ●10 30 ns
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AV
DD
=
DV
DD
= OV
DD
= V
DD
, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above V
DD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 100kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC
+
with respect to
ADC
–
tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specifications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 14: t
6
of 45ns maximum allows f
SCK
up to 10MHz for rising capture
with 50% duty cycle and f
SCK
up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specification is referred to the ±10V input range.
6
LTC1857/LTC1858/LTC1859
185789f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC1859 Nonaveraged
4096-Point FFT Plot
LTC1859 SINAD
vs Input Frequency
LTC1859 Total Harmonic
Distortion vs Input Frequency
LTC1859 Typical INL Curve LTC1859 Typical DNL Curve
LTC1859 Channel-to-Channel
Offset Error Matching vs
Temperature
CODE
–32768
DNL (LSB)
0
0.5
1.0
0
1859 G02
–0.5
–1.0
–2.0 –16384 16384 32767
–1.5
2.0
1.5
FREQUENCY (kHz)
01525 50
1869 G03
510 20 30 40 45
35
MAGNITUDE (dB)
–60
–40
–20
0
–80
–100
–70
–50
–30
–10
–90
–110
–130
–120
f
SAMPLE
= 100kHz
f
IN
= 1kHz
SINAD = 86.95dB
THD = –101.42dB
INPUT FREQUENCY (kHz)
1
74
SINAD (dB)
78
82
90
10 100
1859 G04
86
76
80
88
84
INPUT FREQUENCY (kHz)
1
–110
TOTAL HARMONIC DISTORTION (dB)
–100
–90
–70
10 100
1859 G05
–80
TEMPERATURE (°C)
–50
–1.0
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
–0.5
0
0.5
1.0
–25 0 25 50
1959 G06
75 100
BIPOLAR MODE
UNIPOLAR MODE
CODE
–32768
INL (LSB)
0
0.5
1.0
0
1859 TA02
–0.5
–1.0
–2.0 –16384 16384 32767
–1.5
2.0
1.5
Change in REFCOMP Voltage
vs Load Current
Internal Reference Voltage
vs Temperature
LTC1859 Channel-to-Channel Gain
Error Matching vs Temperature
TEMPERATURE (°C)
–50
–1.0
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
–0.5
0
0.5
1.0
–25 0 25 50
1959 G07
75 100
BIPOLAR MODE
UNIPOLAR MODE
TEMPERATURE (°C)
–50
INTERNAL REFERENCE VOLTAGE (V)
25 75
1859 G08
–25 0 50
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480 100
LOAD CURRENT (mA)
–50
–0.04
CHANGE IN REFCOMP VOLTAGE (V)
–0.02
0
0.02
0.04
–40 –30 –20 –10
1859 G09
010
7
LTC1857/LTC1858/LTC1859
185789f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
UU
U
PI FU CTIO S
COM (Pin 1): Common Input. This is the reference point
for all single-ended inputs. It must be free of noise and is
usually connected to the analog ground plane.
CH0 (Pin 2): Analog MUX Input.
CH1 (Pin 3): Analog MUX Input.
CH2 (Pin 4): Analog MUX Input.
CH3 (Pin 5): Analog MUX Input.
CH4 (Pin 6): Analog MUX Input.
CH5 (Pin 7): Analog MUX Input.
CH6 (Pin 8): Analog MUX Input.
CH7 (Pin 9): Analog MUX Input.
MUXOUT
+
(Pin 10): Positive MUX Output. Output of the
analog multiplexer. Connect to ADC
+
for normal operation.
MUXOUT
–
(Pin 11): Negative MUX Output. Output of the
analog multiplexer. Connect to ADC
–
for normal operation.
ADC
+
(Pin 12): Positive Analog Input to the Analog-to-
Digital Converter.
ADC
–
(Pin 13): Negative Analog Input to the Analog-to-
Digital Converter.
AGND1 (Pin 14): Analog Ground.
V
REF
(Pin 15): 2.5V Reference Output. Bypass to analog
ground with a 1µF tantalum capacitor.
REFCOMP (Pin 16): Reference Buffer Output. Bypass to
analog ground with a 10µF tantalum and a 0.1µF ceramic
capacitor. Nominal output voltage is 4.096V.
AGND2 (Pin 17): Analog Ground.
AGND3 (Pin 18): Analog Ground. This is the substrate
connection.
AV
DD
(Pin 19): 5V Analog Supply. Bypass to analog ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
DV
DD
(Pin 20): 5V Digital Supply. Bypass to digital ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
OV
DD
(Pin 21): Positive Supply for the Digital Output
Buffers (3V to 5V). Bypass to digital ground with a 0.1µF
ceramic and a 10µF tantalum capacitor.
BUSY (Pin 22): Output shows converter status. It is low
when a conversion is in progress.
SDO (Pin 23): Serial Data Output.
LTC1859 Power Supply
Feedthrough vs Ripple Frequency Supply Current vs Supply Voltage Supply Current vs Temperature
RIPPLE FREQUENCY (Hz)
–60
POWER SUPPLY FEEDTHROUGH (dB)
–40
–20
–10
100 10k 100k 1M
1859 G10
–80
1k
–30
–50
–70
fSAMPLE = 100kHz
VRIPPLE = 60mV
SUPPLY VOLTAGE (V)
4.5
SUPPLY CURRENT (mA)
8.0
8.5
5.5
1859 G11
7.5
7.0 4.75 55.25
9.0 f
SAMPLE
= 100kHz
TEMPERATURE (°C)
–50
7.0
POSITIVE SUPPLY CURRENT (mA)
7.5
8.0
8.5
9.0
–25 0 25 50
1859 G12
75 100
fSAMPLE = 100kHz
8
LTC1857/LTC1858/LTC1859
185789f
UU
W
FU CTIO AL BLOCK DIAGRA
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AND
RANGE
SELECT
AGND3
AGND2REFCOMPV
REF
ADC
–
MUXOUT
+
MUXOUT
–
ADC
+
DGND
AV
DD
DV
DD
MUX ADDRESS AND RANGE
DATA OUT
CONVST
SDI
BUSY
SCK
RD
OV
DD
SDO
1859 BD
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
CH7
CH1
•
•
•
CH0
DGND (Pin 24): Digital Ground.
SDI (Pin 25): Serial Data Input.
SCK (Pin 26): Serial Data Clock.
UU
U
PI FU CTIO S
RD (Pin 27): Read Input. This active low signal enables the
digital output pin SDO.
CONVST (Pin 28): Conversion Start. This active high
signal starts a conversion on its rising edge.
Load Circuits for Access Timing
1k
(A) Hi-Z TO VOH AND VOL TO VOH
25pF
1k
5V
DNDN
(B) Hi-Z TO VOL AND VOH TO VOL
25pF
1859 TC01
Load Circuits for Output Float Delay
1k
(A) VOH TO Hi-Z
25pF
1k
5V
DNDN
(B) VOL TO Hi-Z
25pF
1859 TC02
TEST CIRCUITS
9
LTC1857/LTC1858/LTC1859
185789f
t1
(For Short Pulse Mode)
t
1
CONVST 50%
1859 TD01
50%
t2 (CONVST to BUSY Delay)
t2
CONVST
BUSY
2.4V
0.4V
1859 TD02
t3, t4, t5 (SCK Timing)
SCK
1859 TD03
t4t5
t3
t
6
(Delay Time, SCK↓ to SDO Valid)
t
7
(Time from Previous Data Remains Valid After SCK↓)
t
6
t
7
SCK
SDO 2.4V
0.4V
0.4V
1859 TD04
t8 (SDO Valid After RD↓)
t8
RD
SDO 2.4V
0.4V
0.4V
1859 TD05
Hi-Z
t
9
(RD↓ to SCK Setup Time)
t
9
0.4V
2.4V
1959 TD06
RD
SCK
t
10
(SDI Setup Time Before SCK↑)
t
10
SCK
SDI 2.4V
2.4V
0.4V
1859 TD07
t11 (SDI Hold Time After SCK↑)
t11
SCK
SDI 2.4V
2.4V
0.4V
1859 TD08
TI I G DIAGRA S
WUW
t12 (SDO Valid Before BUSY↑, RD = 0)
t12
BUSY
SDO 2.4V B15
2.4V
1859 TD09
t13 (BUS Relinquish Time)
t13
RD
SDO
2.4V
1859 TD10
10%
90% Hi-Z
10
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
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OVERVIEW
The LTC1857/LTC1858/LTC1859 are innovative, multi-
channel ADCs that provide software-selectable input ranges
for each of their eight input channels. Using on-chip
resistors and switches, it provides an attenuation and
offset that can be programmed for each channel on the fly.
The precisely trimmed attenuators ensure accurate input
ranges. Because they precede the multiplexer, errors due
to multiplexer on-resistance are eliminated.
The input word that selects the input channel also selects
the desired input range for that channel. The available
ranges are 0V to 5V, 0V to 10V (unipolar), ±5V and ±10V
(bipolar). They are achieved with the ADC running on a
single 5V supply. In addition to the range selection, single
ended or differential inputs may be selected for each
channel or pair of channels. Finally, overrange protection
is provided for unselected channels. An overrange condi-
tion on an unused channel will not affect the conversion
result on the selected channel.
CONVERSION DETAILS
The LTC1857/LTC1858/LTC1859 use a successive approxi-
mation algorithm and an internal sample-and-hold circuit
to convert an analog signal to a 12-/14-/16-bit serial out-
put respectively. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
The analog signals applied at the MUX input channels are
rescaled by the resistor divider network formed by R1, R2
and R3 as shown below. The rescaled signals appear on
the MUXOUT (Pins 10, 11) which are also connected to the
ADC inputs (Pins 12, 13) under normal operation.
Before starting a conversion, an 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges to
select the MUX address, input range and power down
mode. The ADC enters acquisition mode on the falling
edge of the sixth clock in the 8-bit data word and ends on
the rising edge of the CONVST signal which also starts a
conversion (see Figure 7). A minimum time of 4µs will
provide enough time for the sample-and-hold capacitors
to acquire the analog signal. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal differential 12-/14-/
16-bit capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a high speed comparator.
At the end of a conversion, the DAC output balances the
analog input (ADC
+
– ADC
–
). The SAR contents (a 16-bit
data word) which represents the difference of ADC
+
and
ADC
–
are loaded into the 12-/14-/16-bit shift register.
DRIVING THE ANALOG INPUTS
The nominal input ranges for the LTC1857/LTC1858/
LTC1859 are 0V to 5V, 0V to 10V, ±5V and ±10V and the
MUX inputs are overvoltage protected to ±25V. The input
impedance is typically 42kΩ in unipolar mode and 31kΩ
in bipolar mode, therefore, it should be driven with a low
impedance source. Wideband noise coupling into the
input can be minimized by placing a 3000pF capacitor at
the input as shown in Figure 2. An NPO-type capacitor
gives the lowest distortion. Place the capacitor as close to
the device input pin as possible. If an amplifier is to be used
to drive the input, care should be taken to select an
amplifier with adequate accuracy, linearity and noise for
the application. The following list is a summary of the op
amps that are suitable for driving the LTC1857/LTC1858/
LTC1859. More detailed information is available in the
Linear Technology data books and online at
www.linear.com.
LT
®
1007: Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
MUX
INPUT
R1
25k
REFCOMP
CH SEL
R3
10k
1859 AI03
R2
17k
MUXOUT
BIPOLAR
11
LTC1857/LTC1858/LTC1859
185789f
LT1227: 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1468/LT1469: Single and dual 90MHz, 16-bit accurate
op amp. Good AC/DC specs.
LT1677: Single, low noise op amp. Rail-to-rail input and
output. Up to ±15V supplies.
APPLICATIO S I FOR ATIO
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3000pF
1859 F02
A
IN+
A
IN–
CH0
CH1
MUXOUT
+
MUXOUT
–
ADC
+
ADC
–
•
•
•
•
Figure 2. Analog Input Filtering
Figure 1. LTC1857/LTC1858/LTC1859 Simplified Equivalent Circuit
LT1792: Single, low noise JFET input op amp, ±5V
supplies.
LT1793: Single, low noise JFET input op amp, 10pA bias
current, ±5V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps. Up to ±15V supplies.
LT1844/LT1885: Dual and quad, 400pA bias current, rail-
to-rail output op amps. Up to ±15V supplies. Faster
response and settling time.
INTERNAL VOLTAGE REFERENCE
The LTC1857/LTC1858/LTC1859 have an on-chip, tem-
perature compensated, curvature corrected, bandgap ref-
erence, which is factory trimmed to 2.50V. The full-scale
range of the LTC1857/LTC1858/LTC1859 is equal to ±5V,
0V to 5V, ±10V or 0V to 10V. The output of the reference
is connected to the input of a gain of 1.6384x buffer
through an 8k resistor (see Figure 3). The input to the
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AND
RANGE
SELECT
AGND3
AGND2REFCOMPV
REF
ADC
–
MUXOUT
+
MUXOUT
–
ADC
+
DGND
AV
DD
DV
DD
MUX ADDRESS AND RANGE
DATA OUT
CONVST
SDI
BUSY
SCK
RD
OV
DD
SDO
1859 BD
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
CH7
CH1
•
•
•
CH0
12
LTC1857/LTC1858/LTC1859
185789f
buffer or the output of the reference is available at V
REF
(Pin 15). The internal reference can be overdriven with an
external reference if more accuracy is needed. The buffer
output drives the internal DAC and is available at REFCOMP
(Pin 16). The REFCOMP pin can be used to drive a steady
DC load of less than 2mA. Driving an AC load is not
recommended because it can cause the performance of
the converter to degrade.
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, … FS – 1.5LSB). The output code is natural binary
with 1LSB = FS/65536. Figure 4b shows the input/output
transfer characteristics for the bipolar mode in two’s
complement format.
FULL SCALE AND OFFSET
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during
a calibration sequence. Offset error must be adjusted
before full-scale error. Zero offset is achieved by adjusting
the offset applied to the “–” input. For single-ended inputs,
this offset should be applied to the COM pin. For differen-
tial inputs, the “–” input is dictated by the MUX address.
For unipolar zero offset error, apply 0.5LSB (actual voltage
will vary with input span selected) to the “+” input and
adjust the offset at the “–” input until the output code
flickers between 0000 0000 0000 0000 and 0000 0000
0000 0001 for the LTC1859, between 00 0000 0000 0000
and 00 0000 0000 0001 for the LTC1858 and between
0000 0000 0000 and 0000 0000 0001 for the LTC1857.
For bipolar zero error, apply –0.5LSB (actual voltage will
vary with input span selected) to the “+” input and adjust
the offset at the “–” input until the output code flickers
between 0000 0000 0000 0000 and 1111 1111 1111
1111 for the LTC1859, between 00 0000 0000 0000 and
APPLICATIO S I FOR ATIO
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Figure 3. Internal or External Reference Source
2.5V
REFERENCE
1859 F03
12-/14-/16-BIT
CAPACITIVE DAC
1.6384X BUFFER
8k
V
REF
1µF
15
2.5V
16 REFCOMP
0.1µF
4.096V
10µF
INPUT VOLTAGE (V)
0V
OUTPUT CODE
FS – 1LSB
1859 F4a
111...111
111...110
111...101
111...100
000...000
000...001
000...010
000...011
1
LSB
UNIPOLAR
ZERO
1LSB = FS
65536
INPUT VOLTAGE (V)
0V
OUTPUT CODE
–1
LSB
1859 F4b
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
1LSB = FS
65536
Figure 4a. Unipolar Transfer Characteristics (UNI = 1) Figure 4b. Bipolar Transfer Characteristics (UNI = 0)
For minimum code transition noise the V
REF
pin and the
REFCOMP pin should each be decoupled with a capacitor
to filter wideband noise from the reference and the buffer.
UNIPOLAR / BIPOLAR OPERATION
Figure 4a shows the ideal input/output characteristics for
the LTC1859. The code transitions occur midway between
13
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
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Figure 5. LTC1859 Histogram for 4096 Conversions
11 1111 1111 1111 for the LTC1858 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1857.
As mentioned earlier, the internal reference is factory
trimmed to 2.50V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed with an accurate external 2.5V ref-
erence applied to V
REF
. For unipolar inputs, an input volt-
age of FS – 1.5LSBs should be applied to the “+” input and
the appropriate reference adjusted until the output code
flickers between 1111 1111 1111 1110 and 1111 1111
1111 1111 for the LTC1859, between 11 1111 1111 1110
and 11 1111 1111 1111 for the LTC1858 and between
1111 1111 1110 and 1111 1111 1111 for the LTC1857.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111 for the LTC1859,
between 01 1111 1111 1110 and 01 1111 1111 1111 for
the LTC1858 and between 0111 1111 1110 and 0111 1111
1111 for the LTC1857.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica-
tions in the Converter Characteristics table.
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where a
DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution of
output code is shown for a DC input that has been digitized
4096 times. The distribution is Gaussian and the RMS
code transition is about 1LSB for the LTC1859.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4µs. No external adjustments
are required and, with the maximum acquisition time of 4µs,
throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1857/LTC1858/LTC1859 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1857/LTC1858/LTC1859 recognize 3V or
5V inputs. The LTC1857/LTC1858/LTC1859 have a dedi-
cated output supply pin (OVP) that controls the output
swings of the digital output pins (SDO, BUSY) and allows
the part to interface to either 3V or 5V digital systems. The
output is two’s complement binary for bipolar mode and
offset binary for unipolar mode.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CONVST and RD. To start a conversion and
put the sample-and-hold into the hold mode bring CONVST
high for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
Figures 6a and 6b show two different modes of operation
for the LTC1859. For the 12-bit LTC1857 and 14-bit
LTC1858, the last four and two bits of the SDO will output
zeros respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output is
available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
CODE
–4 –3
0
COUNT
200
600
800
1000
23
1800
1859 F05
400
–2 –1 0 14
1200
1400
1600
14
LTC1857/LTC1858/LTC1859
185789f
Figure 6a. Mode 1 for the LTC1859*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
Figure 6b. Mode 2 for the LTC1859*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
APPLICATIO S I FOR ATIO
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SGL/
DIFF
1
t
4
RD = 0
SCK
SDI
SDO
CONVST
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0 (LSB)
t
ACQ
t
7
t
6
t
2
t
CONV
t
1
t
10
t
11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
12345678 1516
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1
1859 F06a
B0 (LSB)
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t
5
t
3
t
12
t
12
SGL/
DIFF
1
t4
CONVST = RD
SCK
SDI
Hi-Z
SDO
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0 (LSB)
tACQ
t13
t2
tCONV
Hi-Z
t10 t11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
12345678 1516
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1
1859 F06b
B0 (LSB) Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t5
t3
t9
t8
t7
t6
Figure 7. Operating Sequence for the LTC1859*
SGL/
DIFF
1
t
4
RD
SCK
SDI
Hi-Z
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0 (LSB)
t
ACQ
t
13
t
2
t
1
t
CONV
Hi-Z
t
10
t
11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
12345678 1516
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1
1859 F07
B0 (LSB) Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t
5
t
3
t
9
t
8
t
7
t
6
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
15
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
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three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
SERIAL DATA INPUT (SDI) INTERFACE
The
LTC1857/LTC1858/LTC1859
communicate with mi-
croprocessors and other external circuitry via a synchro-
nous, full duplex, 3-wire serial interface (see Figure 7).
The shift clock (SCK) synchronizes the data transfer with
each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
An 8-bit input word is shifted into the SDI input which
configures the LTC1857/LTC1858/LTC1859 for the next
conversion. Simultaneously, the result of the previous
conversion is output on the SDO line. At the end of the data
exchange the requested conversion begins by applying a
rising edge on CONVST. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one conversion from the input word re-
questing it.
SGL/
DIFF
SELECT
1
SELECT
0UNI GAIN NAP
MUX ADDRESS
INPUT RANGE
POWER DOWN
SELECTION
1859 AI02
ODD
SIGN SLEEP
SDI
SDO SDO
WORD 0
SDI
WORD 1
DATA
TRANSFER
SDO
WORD 2
SDI
WORD 3
SDO
WORD 1
SDI
WORD 2
DATA
TRANSFER
t
CONV
A/D
CONVERSION
t
CONV
A/D
CONVERSION
1859 • AI01
Figure 8. Examples of Multiplexer Options on the LTC1857/LTC1858/LTC1859
0
1
2
3
4
5
6
7
CHANNEL
COM (
–
)
8 Single-Ended
+
+
+
+
+
+
+
0,1
CHANNEL
4 Differential
2,3
4,5
6,7
+
(
–
)
+
+
(
–
)
+
(
–
)
+
(
–
)
–
(
+
)
–
(
+
)
–
(
+
)
–
(
+
)
4
5
6
7
CHANNEL
COM (
–
)
Combinations of
Differential and Single-Ended
+
+
+
+
+
+
0,1
2,3
–
–
COM (UNUSED)
Changing the
MUX Assignment “On the Fly”
COM (
–
)
4,5
6,7
4,5
1ST CONVERSION 2ND CONVERSION
+
–
+
–
+
–
+
+
7
6
{
{
{
{
{{
{
{
{
1859 F08
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/
DIFF
SELECT
1 0
ODD
SIGN
10 00 + –
10 01 + –
10 10 + –
10 11 + –
11 00 + –
11 01 + –
11 10 + –
11 11 + –
SGL/
DIFF
ODD
SIGN
SELECT
1 0
00 00+–
00 01 +–
00 10 +–
00 11 + –
01 00–+
01 01 –+
01 10 –+
01 11 – +
0123456 7 0 1 2 3 4 5 6 7 COM
SINGLE-ENDED CHANNEL SELECTION
INPUT DATA WORD
The LTC1857/LTC1858/LTC1859 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges.
Further inputs on the SDI pin are then ignored until the next
conversion. The eight bits of the input word are defined as
follows:
16
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
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MUX ADDRESS
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM. Both the “+” and “–” inputs are sampled simulta-
neously so common mode noise is rejected.
INPUT RANGE (UNI, GAIN)
The fifth and sixth input bits (UNI, GAIN) determine the
input range for the conversion. When UNI is a logical one,
a unipolar conversion will be performed. When UNI is a
logical zero, a bipolar conversion will result. The GAIN
input bit determines the input span for the conversion.
When GAIN is a logical one, either 0V to 10V or ±10V input
spans will be selected depending on UNI. When GAIN is a
logical zero, either 0V to 5V or ±5V input spans will be
chosen. The input ranges for different UNI and GAIN
inputs are shown in Table 2.
Table 2. Input Range Selection
UNI GAIN INPUT RANGE
00 ±5V
1 0 0V to 5V
01 ±10V
1 1 0V to 10V
P
OWER DOWN SELECTION (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) deter-
mine the power shutdown mode of the LTC1857/LTC1858/
LTC1859. See Table 3. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the con-
version which is indicated by the rising edge of the BUSY
signal. Nap mode lasts until the falling edge of the 2nd SCK
(see Figure 9). Automatic nap will be achieved if Nap = 1
is selected each time an input word is written to the ADC.
Table 3. Power Down Selection
NAP SLEEP POWER DOWN MODE
0 0 Power On
1 0 Nap
X 1 Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previous
conversion result can be clocked out and the Sleep mode
will start on the falling edge of the last (16th) SCK. Notice
that the CONVST should stay either high or low in sleep
mode (see Figure 10). To wake up from the sleep mode,
apply a rising edge on the CONVST signal and then apply
Sleep = 0 on the next SDI word and the part will wake up
on the falling edge of the last (16th) SCK (see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10µA)
remain. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 16).
The wake-up time is typically 40ms with the recom-
mended 10µF capacitor connected on the REFCOMP pin.
DYNAMIC PERFORMANCE
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical LTC1859 FFT plot which yields a SINAD of 87dB
and THD of – 101dB.
17
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
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Figure 9. Nap Mode Operation for the LTC1859*
SGL/
DIFF
1
RD
SCK
SDI
Hi-Z
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP = 1 SLEEP = 0 DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0 (LSB)
tCONV
Hi-Z
NAP
tACQ tACQ
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
12345678 1516
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 MSB B11 B10 B9 B8 B1
1859 F09
B0 (LSB) Hi-Z
SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN
Figure 11. Wake Up from Sleep Mode for the LTC1859*
Figure 10. Sleep Mode Operation for the LTC1859*
SGL/
DIFF
1
RD
SCK
SDI
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP = 0 DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1 B0 (LSB)
WAKE-UP
TIME
READY
tCONV
SLEEP
SHIFT WAKE-UP CONFIGURATION WORD IN
SGL/
DIFF
12345678 1516
ODD/
SIGN
SELECT
1
SELECT
0UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB) B11 B10 B9 B8 B1
1859 F11
B0 (LSB)
A/D RESULT NOT VALID
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
tCONV
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
18
LTC1857/LTC1858/LTC1859
185789f
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows a typical SINAD of 87dB with
a 100kHz sampling rate and a 1kHz input.
TOTAL HARMONIC DISTORTION
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log V
2232422
1
++ +VV V
V
N
...
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics.
BOARD LAYOUT, POWER SUPPLIES
AND DECOUPLING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the
LTC1857/LTC1858/LTC1859
, a
printed circuit board is required. Layout for the printed
circuit board should ensure the digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
In applications where the MUX is connected to the ADC, it
is possible to get noise coupling into the ADC from the
trace connecting the MUXOUT to the ADC. Therefore,
reducing the length of the traces connecting the MUXOUT
pins (Pins 10, 11) to the ADC pins (Pins 12, 13) can
minimize the problem. The unused MUX inputs should be
grounded to prevent noise coupling into the inputs.
Figure 13 shows the power supply grounding that will help
obtain the best performance from the 12-bit/14-bit/16-bit
ADCs. Pay particular attention to the design of the analog
and digital ground planes. The DGND pin of the
LTC1857/
APPLICATIO S I FOR ATIO
WUUU
Figure 12. LTC1859 Nonaveraged 4096 Point FFT Plot
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–60
–40
–20
0
40
1859 F12
–80
–100
–70
–50
–30
–10
–90
–110
–130
–120
10 20 30
545
15 25 35 50
f
SAMPLE
= 100kHz
f
IN
= 1kHz
SINAD = 86.95dB
THD = –101.42dB
19
LTC1857/LTC1858/LTC1859
185789f
APPLICATIO S I FOR ATIO
WUUU
1859 F13
ADC+
LTC1857/LTC1858/LTC1859 DIGITAL
SYSTEM
OVDD
DGND
24 21
ADC–
10µF
DVDD
20
10µF
AVDD
19
AGND
14, 17, 18
10µF
REFCOMP
16
10µF
VREF
15
12
MUXOUT+
LTC1857/
LTC1858/
LTC1859
MUXOUT–
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
11 13
1µF
ANALOG GROUND PLANE
+
–
Figure 13. Power Supply Grounding Practice
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
LTC1858/LTC1859
can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply pins, the reference and reference buffer output
is very important. Low impedance common returns for
these bypass capacitors are essential to low noise opera-
tion of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
G28 SSOP 0204
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
20
LTC1857/LTC1858/LTC1859
185789f
© LINEAR TECHNOLOGY CORPORATION 2004
LT/TP 0904 1K • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
U
TYPICAL APPLICATIO
RELATED PARTS
2.5V
REFERENCE
INTERNAL
CLOCK
1.6384X
4.096V
8k
AGND1
CONTROL
LOGIC
SERIAL I/O
INPUT MUX
AND
RANGE
SELECT
AGND3
AGND2
REFCOMP
VREF
ADC–
MUXOUT+
MUXOUT–ADC+DGND
AVDD DVDD
MUX ADDRESS AND RANGE
DATA OUT
CONVST 28
25
22
26
27
21
23
3V TO 5V
SDI
BUSY
SCK
RD
OVDD
SDO
1859 TA03
12-/14-/16-BIT
SAMPLING ADC
+
–
COM
19 20
5V
5V
1
2
3
9CH7
14 11 10 12 13 15 16 17 18 24
1µF0.1µF
CH1
SINGLE-ENDED
OR DIFFERENTIAL
CHANNEL
SELECTION
(SEE TABLE 1)
INPUT RANGES:
0V TO 5V
0V TO 10V
±5V AND ±10V
•
•
•
CH0
10µF
0.1µF10µF
8-BIT SERIAL
DATA INPUT
16 SHIFT CLOCK CYCLES
16-BIT SERIAL DATA OUT
10µF0.1µF10µF0.1µF
PART NUMBER DESCRIPTION COMMENTS
Sampling ADCs
LTC1417 14-Bit, 400ksps Serial ADC 5V or ±5V, 20mW, 81dB SINAD and –95dB THD
LTC1418 14-Bit, 200ksps, Single 5V or ±5V ADC 15mW, Serial/Parallel I/O
LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
LTC1608 16-Bit, 500ksps, ±5V ADC 90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604
LTC1609 16-Bit, 200ksps Serial ADC Configurable Unipolar/Bipolar Input, Single 5V Supply
LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC Programmable MUX and Sequencer, Parallel I/O
LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADC Single 3V-5V, Programmable MUX and Sequencer, Parallel I/O
LTC1864/LTC1865 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP Single 5V Supply, 850µA with Autoshutdown
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP Single 3V Supply, 450µA with Autoshutdown
DACs
LTC1588/LTC1589 12-/14-/16-Bit, Serial, SoftSpan I
OUT
DACs Software-Selectable Spans, ±1LSB INL/DNL
LTC1592
LTC1595 16-Bit Serial Multiplying I
OUT
DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596 16-Bit Serial Multiplying I
OUT
DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial V
OUT
DAC Low Power, Low Gritch, 4-Quadrant Multiplication
Op Amps
LT1468/LT1469 Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amp Low Input Offset : 75µV/125µV