20 V, 500 mA, Low Noise LDO Regulator
with Soft Start
Data Sheet
ADP7105
Rev. B Document Feedback
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FEATURES
Input voltage range: 3.3 V to 20 V
Maximum output current: 500 mA
Low noise: 15 µV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V
Reverse current protection
Low dropout voltage: 350 mV at 500 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature: −2% to +1%
Low quiescent current: 900 μA at VIN = 10 V, IOUT = 500 mA
Low shutdown current: <50 µA at VIN = 12 V, stable with
small 1 µF ceramic output capacitor
3 fixed output voltage options: 1.8, 3.3 V and 5 V
Adjustable output from 1.22 V to 19 V
Programmable soft start for inrush current control
Foldback current-limit and thermal overload protection
User programmable precision UVLO/enable
Power-good indicator
8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulation of noise sensitive applications: ADC and DAC
circuits, precision amplifiers, high frequency oscillators,
clocks, and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
TYPICAL APPLICATION CIRCUITS
Figure 1. ADP7105 with Fixed Output Voltage, 5 V
Figure 2. ADP7105 with Adjustable Output Voltage, 5 V
GENERAL DESCRIPTION
The ADP7105 is a CMOS, low dropout (LDO) linear regulator
that operates from 3.3 V to 20 V and provides up to 500 mA of
output current. This high input voltage LDO is ideal for regula-
tion of high performance analog and mixed-signal circuits
operating from 1.22 V to 19 V rails. Using an advanced proprie-
tary architecture, the ADP7105 provides high power supply
rejection and low noise, and achieves excellent line and load
transient response with only a small 1 µF ceramic output
capacitor.
The ADP7105 is available in three fixed output voltage options
and an adjustable version that allows output voltages ranging
from 1.22 V to 19 V via an external feedback divider. The
ADP7105 allows an external soft start capacitor to be connected
to program the startup.
Note that throughout this data sheet, the sense function (SENSE) of
the SENSE/ADJ pin applies to fixed output voltage models only,
whereas the adjust input function (ADJ) applies to adjustable
output voltage models only. For example, Figure 1 shows the
sense function, and Figure 2 shows the adjust input function.
The ADP7105 output noise voltage is 15 μV rms and is inde-
pendent of the output voltage. A digital power-good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7105 is available in 8-lead, 3 mm × 3 mm LFCSP and
8-lead SOIC packages. The LFCSP offers a very compact solution
and provides excellent thermal performance for applications
that require up to 500 mA of output current in a small, low
profile footprint.
V
OUT
= 5V
V
IN
= 8V
PG
VOUT
VIN
PG
SS
GND
SENSE
EN/
UVLO
100kΩ
100kΩ
100kΩ
COUT
1µF
CSS
CIN
1µF
ON
OFF
+
+
11641-001
V
OUT
= 5V
V
IN
= 8V
PG
VOUTVIN
PG
GND
ADJ
EN/
UVLO 100kΩ
100kΩ
100kΩ
COUT
1µF
CIN
1µF
ON
OFF
++
13kΩ
40.2kΩ
SS CSS
11641-002
ADP7105 Data Sheet
Rev. B | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor, Recommended Specifications .... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 17
Applications Information .............................................................. 18
Capacitor Selection .................................................................... 18
Programmable Undervoltage Lockout (UVLO) .................... 19
Soft Start Function ..................................................................... 19
Power-Good Feature .................................................................. 20
Noise Reduction of the Adjustable ADP7105 ........................ 20
Current-Limit and Thermal Overload Protection ................. 21
Thermal Considerations ............................................................ 21
Printed Circuit Board Layout Considerations ............................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
10/15—Rev. A to Rev. B
Changes to Figure 60 and Figure 61............................................. 17
5/14—Rev. 0 to Rev. A
Change to UVLO Threshold Rising Parameter, Table 1 ............. 4
7/13—Revision 0: Initial Version
Data Sheet ADP7105
Rev. B | Page 3 of 26
SPECIFICATIONS
VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µ F, T A = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 3.3 20 V
OPERATING SUPPLY CURRENT IGND IOUT = 100 µA, VIN = 10 V 400 µA
IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C 900 µA
IOUT = 10 mA, VIN = 10 V 450 µA
IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 1050 µA
IOUT = 300 mA, VIN = 10 V 750 µA
IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 1400 µA
IOUT = 500 mA, VIN = 10 V 900 µA
OUT
IN
J
1600
µA
SHUTDOWN CURRENT IGND-SD EN = GND, VIN = 12 V 40 50 µA
EN = GND, VIN = 12 V, TJ = −40°C to +125°C 75 µA
INPUT REVERSE CURRENT IREV-INPUT EN = GND, VIN = 0 V, VOUT = 20 V 0.3 µA
EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to
+125°C
5 µA
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy VOUT IOUT = 10 mA −0.8 +0.8 %
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
−2 +1 %
Adjustable Output Voltage
Accuracy
VADJ IOUT = 10 mA 1.21 1.22 1.23 V
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
1.196 1.232 V
LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C −0.015 +0.015 %/V
LOAD REGULATION
1
∆V
OUT
/∆I
OUT
OUT
0.2
%/A
1 mA < IOUT < 500 mA, TJ = −40°C to +125°C 0.75 %/A
ADJ INPUT BIAS CURRENT2 ADJI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
ADJ connected to VOUT
10 nA
SENSE INPUT BIAS CURRENT2 SENSEI-BIAS 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
SENSE connected to VOUT, VOUT = 1.5 V
1 μA
DROPOUT VOLTAGE3 VDROPOUT IOUT = 10 mA 20 mV
IOUT = 10 mA, TJ = −40°C to +125°C 40 mV
OUT
100
mV
IOUT = 150 mA, TJ = −40°C to +125°C 175 mV
IOUT = 300 mA 200 mV
IOUT = 300 mA, TJ = −40°C to +125°C 325 mV
IOUT = 500 mA 350 mV
OUT
J
550
mV
START-UP TIME4 tSTART-UP CSS = 0 nF, IOUT = 10 mA 625 µs
CSS = 10 nF, IOUT = 10 mA 11.5 ms
CURRENT-LIMIT THRESHOLD5 ILIMIT 625 775 1000 mA
PG OUTPUT LOGIC LEVEL
PG Output Logic High PGHIGH IOH < 1 µA 1.0 V
PG Output Logic Low PGLOW IOL < 2 mA 0.4 V
PG OUTPUT THRESHOLD
Output Voltage Falling PGFALL −9.2 %
Output Voltage Rising PGRISE −6.5 %
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
ADP7105 Data Sheet
Rev. B | Page 4 of 26
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SOFT START SOURCE CURRENT SSI-SOURCE SS = GND 1 µA
PROGRAMMABLE EN/UVLO
UVLO Threshold Rising UVLORISE 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 1.18 1.22 1.28 V
UVLO Threshold Falling UVLOFALL 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in
series with the enable input pin
1.13 V
UVLO Hysteresis Current UVLOHYS VEN > 1.25 V, TJ = −40°C to +125°C 7.5 9.8 12 µA
Enable Pull-Down Current IEN-IN EN = VIN 500 nA
Start Threshold
V
START
J
3.2
V
Shutdown Threshold VSHUTDOWN TJ = −40°C to +125°C 2.45 V
Hysteresis 250 mV
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 15 µV rms
10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 15 µV rms
10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 15 µV rms
10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 15 µV rms
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V,
adjustable mode
18 µV rms
10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V, adjustable
mode
30 µV rms
10 Hz to 100 kHz, VIN = 20 V, VOUT = 15 V,
adjustable mode
65 µV rms
POWER SUPPLY REJECTION RATIO PSRR 100 kHz, VIN = 4.3 V, VOUT = 3.3 V 50 dB
100 kHz, VIN = 6 V, VOUT = 5 V 50 dB
10 kHz, VIN = 4.3 V, VOUT = 3.3 V 60 dB
10 kHz, VIN = 6 V, VOUT = 5 V 60 dB
100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 50 dB
100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 60 dB
100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 60 dB
10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 60 dB
10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 80 dB
10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 80 dB
1 Based on an endpoint calculation using 1 mA and 500 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2 The adjust input function (ADJ) of the SENSE/ADJ pin applies to adjustable output voltage models only; whereas the sense function (SENSE) applies to fixed output
voltage models only.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This specification applies only for
output voltages greater than 3.0 V.
4 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage falls to 90% of the specified typical value. For example, the current limit for a 5.0 V output
voltage is defined as the current that causes the output voltage to fall to 90% of 5.0 V, or 4.5 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Minimum Input and Output Capacitance1 CMIN TA = −40°C to +125°C 0.7 µF
Capacitor ESR RESR TA = −40°C to +125°C 0.001 0.2 Ω
1 Ensure that the minimum input and output capacitance is greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO regulator.
Data Sheet ADP7105
Rev. B | Page 5 of 26
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +22 V
VOUT to GND
−0.3 V to +20 V
EN/UVLO to GND −0.3 V to VIN
PG to GND −0.3 V to VIN
SENSE/ADJ to GND −0.3 V to VOUT
SS to GND −0.3 V to +3.6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7105 can be damaged when the junction
temperature (TJ) limit is exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor printed circuit board (PCB) thermal resistance, the
maximum ambient temperature may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JEDEC JESD51-7 and JESD51-9 for detailed
information on the board construction. For additional
information, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), available at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The package ΨJB is based on modeling and
calculation using a 4-layer board. JEDEC JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than through a
single path as in thermal resistance, θJB. Therefore, ΨJB thermal
paths include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
θJC is a parameter for surface-mount packages with top
mounted heat sinks. θJC is presented here for reference only.
Table 4. Thermal Resistance
Package Type θJA θJC ΨJB Unit
8-Lead LFCSP 40.1 27.1 17.2 °C/W
8-Lead SOIC 48.5 58.4 31.3 °C/W
ESD CAUTION
ADP7105 Data Sheet
Rev. B | Page 6 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration, LFCSP Package Figure 4. Pin Configuration, Narrow-Body SOIC Package
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor.
2 SENSE/ADJ
Sense (SENSE). SENSE measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load. This function applies to fixed voltage models only.
Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to
adjustable voltage models only.
3 GND Ground.
4 SS Soft Start. A capacitor connected to this pin determines the soft start time.
5 EN/UVLO
Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.
For automatic startup, connect EN to VIN.
Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,
the upper and lower thresholds are determined by the programming resistors.
6 GND Ground.
7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the
part is in shutdown mode, current-limit mode, or thermal shutdown, or if VOUT falls below 90%
of the nominal output voltage, PG immediately transitions low. If the power-good function is
not used, the pin can be left open or connected to ground.
8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor.
EPAD
Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance
and is electrically connected to GND inside the package. It is highly recommended that the
exposed pad be connected to the ground plane on the board.
NOTES
1. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
3GND
4SS
1VOUT
2SENSE/ADJ
6GND
5 EN/UVLO
8VIN
7PG
ADP7105
TOP VIEW
(Not to Scale)
11641-003
NOTES
1. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
VOUT
1
SENSE/ADJ
2
GND
3
SS
4
VIN
8
PG
7
GND
6
EN/UVLO
5
ADP7105
TOP VIEW
(Not to Scale)
11641-004
Data Sheet ADP7105
Rev. B | Page 7 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 7.5 V, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Figure 5. Output Voltage vs. Junction Temperature, VOUT = 3.3 V
Figure 6. Output Voltage vs. Load Current, VOUT = 3.3 V
Figure 7. Output Voltage vs. Input Voltage, VOUT = 3.3 V
Figure 8. Ground Current vs. Junction Temperature, VOUT = 3.3 V
Figure 9. Ground Current vs. Load Current, VOUT = 3.3 V
Figure 10. Ground Current vs. Input Voltage, VOUT = 3.3 V
3.25
3.27
3.29
3.31
3.33
3.35
V
OUT
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
–40 –5 25 85 125
T
J
(
°C
)
11641-005
3.25
3.27
3.29
3.31
3.33
3.35
0.1 110 100 1000
V
OUT
(V)
I
LOAD
(mA)
11641-006
3.25
3.27
3.29
3.31
3.33
3.35
46810 12 14 16 18 20
V
OUT
(V)
V
IN
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-007
0
200
400
600
800
1000
1200
GRO UND CURRE NT (µA)
–40 –5 25 85 125
T
J
(
°C
)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-008
0
100
200
300
400
500
600
700
800
0.1 110 100 1000
ILOAD (mA)
GRO UND CURRE NT (µA)
11641-009
0
200
400
600
800
1000
1200
4 6 8 10 12 14 16 18 20
GRO UND CURRE NT (µA)
V
IN
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-010
ADP7105 Data Sheet
Rev. B | Page 8 of 26
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
Figure 12. Dropout Voltage vs. Load Current, VOUT = 3.3 V
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3.3 V
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 3.3 V
Figure 15. Output Voltage vs. Junction Temperature, VOUT = 5 V
Figure 16. Output Voltage vs. Load Current, VOUT = 5 V
SHUT DO WN CURRENT (µA)
0
20
40
60
80
100
120
140
160
–50 –25 025 50 75 100 125
TEMPERAT URE ( °C)
3.3V
4.0V
6.0V
8.0V
12.0V
20.0V
11641-011
0
50
100
150
200
250
300
350
110 100 1000
DROPOUT V OLTAGE (mV)
I
LOAD
(mA)
V
OUT
= 3.3V
T
A
= 25° C
11641-012
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.1 3.2 3.3 3.4 3.5 3.6 3.7
V
OUT
(V)
V
IN
(V)
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
11641-013
0
200
400
600
800
1000
1200
1400
3.1 3.2 3.3 3.4 3.5 3.6 3.7
GRO UND CURRE NT (µA)
V
IN
(V)
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
11641-014
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
VOUT (V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
–40°C –5°C 25°C 85°C 125°C
T
J
(
°C
)
11641-015
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
0.1 110 100 1000
V
OUT
(V)
I
LOAD
(mA)
11641-016
Data Sheet ADP7105
Rev. B | Page 9 of 26
Figure 17. Output Voltage vs. Input Voltage, VOUT = 5 V
Figure 18. Ground Current vs. Junction Temperature, VOUT = 5 V
Figure 19. Ground Current vs. Load Current, VOUT = 5 V
Figure 20. Dropout Voltage vs. Load Current, VOUT = 5 V
Figure 21. Output Voltage vs. Input Voltage (in Dropout), VOUT = 5 V
Figure 22. Ground Current vs. Input Voltage (in Dropout), VOUT = 5 V
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
6 8 10 12 14 16 18 20
VOUT (V)
VIN (V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-017
0
100
200
300
400
500
600
700
800
900
1000
25 85 125
GRO UND CURRE NT (µA)
T
J
(° C)
–40 –5
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
11641-118
0
100
200
300
400
500
600
700
0.1 110 100 1000
GRO UND CURRE NT (µA)
I
LOAD
(mA)
11641-119
0
50
100
150
200
250
300
110 100 1000
DROPOUT V OLTAGE (mV)
I
LOAD
(mA)
V
OUT
= 5V
T
A
= 25° C
11641-018
4.55
4.60
4.65
4.70
4.75
4.80
4.85
4.90
4.95
5.00
5.05
4.8 4.9 5.0 5.1 5.2 5.3 5.4
V
OUT
(V)
V
IN
(V)
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
11641-019
–500
0
500
1000
1500
2000
2500
4.80 4.90 5.00 5.10 5.20 5.30 5.40
GRO UND CURRE NT (µA)
VIN (V)
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
11641-020
ADP7105 Data Sheet
Rev. B | Page 10 of 26
Figure 23. Output Voltage vs. Junction Temperature, VOUT = 1.8 V
Figure 24. Output Voltage vs. Load Current, VOUT = 1.8 V
Figure 25. Output Voltage vs. Input Voltage, VOUT = 1.8 V
Figure 26. Ground Current vs. Junction Temperature, VOUT = 1.8 V
Figure 27. Ground Current vs. Load Current, VOUT = 1.8 V
Figure 28. Ground Current vs. Input Voltage, VOUT = 1.8 V
1.75
1.77
1.79
1.81
1.83
1.85
V
OUT
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
–40 –5 25 85 125
T
J
(
°C
)
11641-021
V
OUT
(V)
1.75
1.77
1.79
1.81
1.83
1.85
0.1 110 100 1000
I
LOAD
(mA)
11641-022
1.75
1.77
1.79
1.81
1.83
1.85
2 4 6810 12 14 16 18 20
V
OUT
(V)
V
IN
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-023
0
100
200
300
400
500
600
700
800
900
25 85 125
GRO UND CURRE NT (µA)
TJ
(° C)
–40 –5
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
11641-126
0
100
200
300
400
500
600
700
0.1 110 100 1000
GRO UND CURRE NT (µA)
ILOAD (mA)
11641-127
0
200
400
600
800
1000
1200
2 4 6810 12 14 16 18 20
GRO UND CURRE NT (µA)
V
IN
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-024
Data Sheet ADP7105
Rev. B | Page 11 of 26
Figure 29. Output Voltage vs. Junction Temperature, VOUT = 5 V, Adjustable
Figure 30. Output Voltage vs. Load Current, VOUT = 5 V, Adjustable
Figure 31. Output Voltage vs. Input Voltage, VOUT = 5 V, Adjustable
Figure 32. Reverse Input Current vs. Temperature, VIN = 0 V, Different
Voltages on VOUT
Figure 33. Start-Up Time, VEN and VIN = 6 V, CIN and COUT = 1 µF, CSS = 10 nF,
IOUT = 10 mA, VOUT = 5 V
Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, VIN = 3.3 V
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
5.06
5.07
5.08
V
OUT
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
–40 –5 25 85 125
T
J
(
°C
)
11641-025
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
5.06
5.07
5.08
0.1 110 100 1000
V
OUT
(V)
I
LOAD
(mA)
11641-026
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
5.06
5.07
5.08
6810 12 14 16 18 20
V
OUT
(V)
V
IN
(V)
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
11641-027
0
0.5
1.0
1.5
2.0
–40 –20 020 40 60 80 100 120 140
REVERS E INPUT CURRENT (µA)
TEMPERAT URE ( °C)
3.3V
4V
5V
6V
8V
10V
12V
15V
18V
20V
11641-054
CH1 2.00V CH2 2.00V M2.00ms A CH1 3.00V
T 5.95ms
CH3 20mA
3
2
1
EN
V
OUT
I
IN
11641-133
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-028
ADP7105 Data Sheet
Rev. B | Page 12 of 26
Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.8 V
Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V
Figure 37. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V
Figure 38. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6.5 V
Figure 39. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V
Figure 40. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-029
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-030
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-031
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR ( dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-032
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-033
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LO AD = 500mA
LO AD = 300mA
LO AD = 100mA
LO AD = 10mA
LO AD = 1mA
11641-034
Data Sheet ADP7105
Rev. B | Page 13 of 26
Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.3 V
Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V
Figure 43. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V,
Adjustable
Figure 44. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V,
Adjustable with Noise Reduction Circuit
Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz,
VOUT = 5 V
Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz,
VOUT = 5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR ( dB)
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LO AD = 500mA
LO AD = 300mA
LO AD = 100mA
LO AD = 10mA
LO AD = 1mA
11641-035
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-036
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LO AD = 500mA
LO AD = 300mA
LO AD = 100mA
LO AD = 10mA
LO AD = 1mA
11641-037
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR ( dB)
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-038
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
00.25 0.50 0.75 1.00 1.25 1.50
PSRR (dB)
HEADROOM V OLTAGE (V)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-039
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
00.25 0.50 0.75 1.00 1.25 1.50
PSRR (dB)
HEADROOM V OLTAGE (V)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-040
ADP7105 Data Sheet
Rev. B | Page 14 of 26
Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz,
VOUT = 5 V
Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz,
VOUT = 5 V
Figure 49. Output Noise vs. Load Current and Output Voltage,
COUT = 1 μF
Figure 50. Output Noise Spectral Density, ILOAD = 10 mA, COUT = 1 μF
Figure 51. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 1.8 V, VIN = 5 V
Figure 52. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 3.3 V, VIN = 5 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
00.25 0.50 0.75 1.00 1.25 1.50
PSRR (dB)
HEADROOM V OLTAGE (V)
LO AD = 500mA
LO AD = 300mA
LO AD = 100mA
LO AD = 10mA
LO AD = 1mA
11641-041
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
00.25 0.50 0.75 1.00 1.25 1.50
PSRR (dB)
HEADROOM V OLTAGE (V)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-042
5
0
10
15
20
25
30
0.010.0010.00010.00001 0.1 1
NOISE (µV rms)
I
LOAD
(A)
3.3V
1.8V
5V
5V
ADJ
5V
ADJ
NR
11641-043
FREQUENCY (Hz)
0.01
0.1
1
10
10 100 1k 10k 100k
NOISE (µV/√Hz)
3.3V
5V
5V
ADJ
5V
ADJ
NR
11641-044
CH2 50mVCH1 500mA M 20µs A CH1 270mA
1
2
T10%
Ω
LO AD CURRE NT
OUTPUT VOLTAGE
11641-045
BW
BW
CH2 50mV
CH1 500mAM 20µs A CH1 280mA
1
2
T10.2%
Ω
LO AD CURRE NT
OUTPUT VOLTAGE
11641-046
BW
BW
Data Sheet ADP7105
Rev. B | Page 15 of 26
Figure 53. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 5 V, VIN = 7 V
Figure 54. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 1.8 V
Figure 55. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 3.3 V
Figure 56. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 5 V
Figure 57. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 1.8 V
Figure 58. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 3.3 V
CH2 50mVCH1 500mA M 20µs A CH1 300mA
1
2
T10.2%
Ω
LOAD CURRENT
OUTPUT VOLTAGE
11641-047
BW
BW
CH2 10mVCH1 1V M 4µs A CH4 1.56V
1
2
T9.8%
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-048
BW
BW
CH2 10mVCH1 1V M 4µs A CH4 1.56V
1
2
T9.8%
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-049
BW
BW
CH2 10mVCH1 1V M 4µs A CH4 1.56V
1
2
T9.8%
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-050
BW
BW
1
2
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-051
CH2 10mVCH1 1V M 4µs A CH4 1.56V
T9.8%
BW
BW
1
2
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-052
CH2 10mVCH1 1V M 4µs A CH4 1.56V
T9.8%
BW
BW
ADP7105 Data Sheet
Rev. B | Page 16 of 26
Figure 59. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 5 V
CH2 10mV
CH1 1V M 4µs A CH4 1.56V
1
2
T9.8%
INPUT VOLTAGE
OUTPUT VOLTAGE
11641-053
BW
BW
Data Sheet ADP7105
Rev. B | Page 17 of 26
THEORY OF OPERATION
The ADP7105 is a low quiescent current, LDO linear regulator
that operates from 3.3 V to 20 V and provides up to 500 mA of
output current. The ADP7105 draws a low 900 µA of quiescent
current (typical) at full load, making it ideal for battery-operated
portable equipment. Typical shutdown current consumption is
40 μA at room temperature.
Optimized for use with small 1 µF ceramic capacitors, the
ADP7105 provides excellent transient performance.
Figure 60. Fixed Output Voltage Internal Block Diagram
Figure 61. Adjustable Output Voltage Internal Block Diagram
Internally, the ADP7105 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate
of the PMOS device is pulled higher, allowing less current to
pass and decreasing the output voltage.
The ADP7105 is available in three fixed output voltage options,
1 . 8 V, 3.3 V, and 5 V, and in an adjustable version with an output
voltage that can be set from 1.22 V to 19 V by an external
voltage divider. The output voltage can be set according to the
following equation:
VOUT = 1.22 V(1 + R1/R2)
Figure 62. Typical Adjustable Output Voltage Application Schematic
Ensure that the value of R2 is less than 200 kΩ to minimize
errors in the output voltage caused by the ADJ input current.
For example, when R1 and R2 each equal 200 kΩ, the output
voltage is 2.46 V. The output voltage error introduced by the
ADJ input current is 2 mV or 0.08%, assuming a typical ADJ
input current of 10 nA at 25°C.
The ADP7105 uses the EN/UVLO pin to enable and disable the
VOUT pin under normal operating conditions. When EN/UVLO
is high, VOUT turns on; when EN/UVLO is low, VOUT turns
off. For automatic startup, EN/UVLO can be tied to VIN.
The ADP7105 incorporates reverse current protection circuitry
that prevents current flow backwards through the pass element
when the output voltage is greater than the input voltage. A
comparator senses the difference between the input and output
voltages. When the difference between the input voltage and
output voltage exceeds 55 mV, the body of the PFET is switched
to VOUT and turned off or opened. In other words, the gate is
connected to VOUT.
SHUTDOWN
VIN
GND
EN/
UVLO
VOUT
REFERENCE
VREG PGOOD PG
SENSE
SS
SHORT-CIRCUIT,
THERMAL
PROTECT
10µA
11641-056
SHUTDOWN
VIN
GND
EN/
UVLO
VOUT
1.22V
REFERENCE
VREG PGOOD PG
ADJ
SHORT-CIRCUIT,
THERMAL
PROTECT
10µA
SS
11641-156
V
OUT
= 5V
V
IN
= 8V
PG
VOUTVIN
PG
GND
ADJ
EN/
UVLO RPG
100kΩ
R4
100kΩ
R3
100kΩ
COUT
1µF
CIN
1µF
ON
OFF R2
13kΩ
+
+R1
40.2kΩ
SS CSS
11641-075
ADP7105 Data Sheet
Rev. B | Page 18 of 26
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP7105 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective series
resistance (ESR) value. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 1 µF capacitance
with an ESR of 1 Ω or less is recommended to ensure the stability
of the ADP7105. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7105 to
large changes in load current. Figure 63 shows the transient
responses for an output capacitance value of 1 µF.
Figure 63. Output Transient Response, VOUT = 1.8 V, COUT = 1 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 µF of output capacitance is required, increase the input
capacitor to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP7105, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 25 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Figure 64 shows the capacitance vs. voltage bias characteristic of
an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
Figure 64. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V, as shown in Figure 64.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO regulator
overtemperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7105, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
CH2 50mV
CH1 500mA M 20µs A CH1 270mA
1
2
T10%
Ω
LO AD CURRE NT
OUTPUT VOLTAGE
11641-057
1.2
1.0
0.8
0.6
0.4
0.2
0
02 4 6 8 10
CAPACITANCE (µF )
VOLTAGE (V)
11641-058
Data Sheet ADP7105
Rev. B | Page 19 of 26
PROGRAMMABLE UNDERVOLTAGE LOCKOUT
(UVLO)
The ADP7105 uses the EN/UVLO pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 65, when a rising voltage on EN/UVLO crosses the upper
threshold, VOUT turns on. When a falling voltage on EN/UVLO
crosses the lower threshold, VOUT turns off. The hysteresis of
the EN/UVLO threshold is determined by the Thevenin
equivalent resistance in series with the EN/UVLO pin.
Figure 65. Typical VOUT Response to EN/UVLO Pin Operation
The upper and lower thresholds are user programmable and can
be set using two resistors. When the EN/UVLO pin voltage is
below 1.23 V, the LDO is disabled. When the EN/UVLO pin
voltage transitions above 1.23 V, the LDO is enabled and 10 µA
hysteresis current is sourced out of the pin, raising the voltage
and thus providing threshold hysteresis. Typically, two external
resistors program the minimum operational voltage for the
LDO. The resistance values, R1 and R2, can be determined from
the following:
R1 = VHYS/10 μA
R2 = 1.23 V × R1/(VIN − 1.23 V)
where:
VHYS is the desired EN/UVLO hysteresis level.
VIN is the desired turn-on voltage.
Hysteresis can also be achieved by connecting a resistor in series
with the EN/UVLO pin. For the example shown in Figure 66,
the enable threshold is 2.46 V with a hysteresis of 1 V.
Figure 66. Typical EN/UVLO Pin Voltage Divider
Figure 65 shows the typical hysteresis of the EN/UVLO pin.
This prevents on/off oscillations that can occur due to noise
on the EN/UVLO pin as it passes through the threshold points.
SOFT START FUNCTION
For applications that require a controlled startup, the ADP7105
provides a programmable soft start function. Programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. Upon startup, a
1 µA current source charges this capacitor. The ADP7105
start-up output voltage is limited by the voltage at SS, providing
a smooth ramp-up to the nominal output voltage. The soft start
time is calculated by
tSS = VREF × (CSS/ISS)
where:
tSS is the soft start delay.
VREF is the 1.22 V reference voltage.
CSS is the soft start capacitance between SS and GND.
ISS is the current sourced from SS (1 µA).
When the ADP7105 is disabled (by driving EN low), the soft
start capacitor is discharged to GND through an internal 5 kΩ
resistor.
Figure 67. Typical Start-Up Behavior
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.25 1.50 1.75 2.00
EN/UVLO (V)
2.25 2.50 2.75 3.001.00
0
V
OUT
, EN/UVLO RISE
V
OUT
, EN/UVLOFALL
11641-060
V
OUT
(V)
V
OUT
= 5V
V
IN
= 8V
PG
VOUTVIN
PG
GND
SENSE
EN/
UVLO
100kΩ
R2
100kΩ
R1
100kΩ
C
OUT
1µF
C
IN
1µF
ON
OFF
+
+
SS C
SS
11641-059
TIME (ms)
0
1
2
3
4
5
6
7
0510 15
OUTPUT VOLTAGE (V)
2.7nF
0nF 6.8nF 10nF
EN
11641-061
ADP7105 Data Sheet
Rev. B | Page 20 of 26
POWER-GOOD FEATURE
The ADP7105 provides a power-good pin (PG) to indicate
the status of the output. This open-drain output requires an
external pull-up resistor to VIN or VOUT. If the part is in
shutdown mode, current-limit mode, or thermal shutdown, or
if VOUT falls below 90% of the nominal output voltage, the
power-good pin (PG) immediately transitions low. During soft
start, the rising threshold of the power-good signal is 93.5% of
the nominal output voltage.
The open-drain output is held low when the ADP7105 has suffi-
cient input voltage to turn on the internal PG transistor. The PG
transistor is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90.8% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no good signals if VOUT falls below 90.8%
of the nominal output voltage.
A normal power-down causes the power-good signal to go low
when VOUT falls below 90.8%.
Figure 68 and Figure 69 show the typical power-good rising and
falling thresholds over temperature.
Figure 68. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Rising
Figure 69. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Falling
NOISE REDUCTION OF THE ADJUSTABLE
ADP7105
The ultralow output noise of the fixed output ADP7105 is
achieved by keeping the LDO error amplifier in unity gain
and setting the reference voltage equal to the output voltage.
This architecture does not apply to the adjustable output voltage
LDO regulator. The adjustable output ADP7105 uses the more
conventional architecture where the reference voltage is fixed
and the error amplifier gain is a function of the output voltage.
The disadvantage of the conventional LDO architecture is that
the output voltage noise is proportional to the output voltage.
The adjustable LDO circuit can be modified slightly to reduce
the output voltage noise to levels close to that of the fixed output
ADP7105. The circuit shown in Figure 70 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be equal to RFB2. This limits
the ac gain of the error amplifier to approximately 6 dB. The
actual gain is the parallel combination of RNR and RFB1 divided
by RFB2. This ensures that the error amplifier always operates at
greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR
at a frequency between 50 Hz and 100 Hz. This capacitor value sets
the frequency so that the ac gain of the error amplifier is 3 dB
less than its dc gain.
Figure 70. Noise Reduction Modification to Adjustable LDO Regulator
The noise of the adjustable LDO regulator can be found by
using the following formula, assuming the noise of a fixed
output LDO is approximately 15 μV:
+
+× kΩ13/
kΩ2.40/1kΩ
1/13 1
1μV15
Based on the component values shown in Figure 70, the
ADP7105 has the following characteristics:
• DC gain of 4.09 (12.2 dB)
• 3 dB roll-off frequency of 59 Hz
• High frequency ac gain of 1.76 (4.89 dB)
• Noise reduction factor of 1.33 (2.59 dB)
• RMS noise of the ADP7105 adjustable LDO without noise
reduction of 27.8 µV rms
• RMS noise of the ADP7105 adjustable LDO with noise
reduction (assuming 15 µV rms for fixed voltage option)
of 19.95 µV rms
0
1
2
3
4
5
6
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
PG (V)
V
OUT
(V)
–40°C
–5°C
+25°C
+85°C
+125°C
11641-062
0
1
2
3
4
5
6
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
PG (V)
V
OUT
(V)
–40°C
–5°C
+25°C
+85°C
+125°C
11641-063
VOUT = 5V
VIN = 8V
PG
VOUTVIN
PG
GND
ADJ
EN/
UVLO RPG
100kΩ
R4
100kΩ
R3
100kΩ
COUT
1µF
CIN
1µF
ON
OFF
RNR
13kΩ
RFB2
13kΩ
+
+RFB1
40.2kΩCNR
100nF
+
SS CSS
11641-064
Data Sheet ADP7105
Rev. B | Page 21 of 26
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP7105 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7105 is designed to limit the current when the
output load reaches 775 mA (typical). When the output load
exceeds 775 mA, the output voltage is reduced to maintain a
constant current limit. As the output voltage drops, the current
is folded back to approximately 50 mA to minimize heat
generation inside the LDO regulator.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and/or
high power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature falls below
135°C, the output is turned on again, and output current is
restored to its operating value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP7105 limits the current so that only
775 mA is conducted into the short. If self heating of the
junction is great enough to cause its temperature to rise above
150°C, thermal shutdown is activated, turning off the output and
reducing the output current to zero. As the junction temperature
cools and falls below 135°C, the output turns on and conducts
775 mA into the short, again causing the junction temperature
to rise above 150°C. This thermal oscillation between 135°C
and 150°C causes a current oscillation between 775 mA and
0 mA that continues as long as the short remains at the output.
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
THERMAL CONSIDERATIONS
In applications with a low input-to-output voltage differential,
the ADP7105 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become
significant enough that it causes the junction temperature of the
die to exceed the maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the regulator
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7105 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA value is dependent on
the package assembly compounds that are used and the amount of
copper used to solder the package GND pins to the PCB.
Table 6 shows typical θJA values for the 8-lead SOIC and 8-lead
LFCSP packages for various PCB copper sizes. Table 7 shows
the typical ΨJB values for the 8-lead SOIC and 8-lead LFCSP
with PCB area.
Table 6. Typical θJA Values
Copper Size (mm2)
θJA (°C/W)
LFCSP SOIC
251 165.1 167.8
100 125.8 111
500 68.1 65.9
1000
56.4
56.1
6400 42.1 45.8
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values with PCB Area
Model ΨJB (°C/W)
8-Lead LFCSP1 15.1
8-Lead SOIC 31.3
1 Note that the ΨJB value for the LFCSP package accounts for PCB area, which
is being used as a heat sink via the exposed pad, whereas the value in Table 4 is
per the JEDEC standard.
The junction temperature of the ADP7105 is calculated from
the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
θJA is the junction-to-ambient thermal resistance.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature, input-
to-output voltage differential, and continuous load current, a
minimum copper size requirement for the PCB exists to ensure
that the junction temperature does not rise above 125°C. Figure 71
to Figure 76 show junction temperature calculations for different
ambient temperatures, power dissipation, and areas of PCB copper.
ADP7105 Data Sheet
Rev. B | Page 22 of 26
Figure 71. LFCSP, TA = 25°C
Figure 72. LFCSP, TA = 50°C
Figure 73. LFCSP, TA = 85°C
Figure 74. SOIC, TA = 25°C
Figure 75. SOIC, TA = 50°C
Figure 76. SOIC, TA = 85°C
25
35
45
55
65
75
85
95
105
115
125
135
145
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
JUNCTION TEMP E R ATURE (° C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAX
11641-065
JUNCTION TEMP E R ATURE (° C)
50
60
70
80
90
100
110
120
130
140
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TOTAL POWER DISSIPATION (W)
6400mm2
500mm2
25mm2
TJMAX
11641-066
JUNCTION TEMP E R ATURE (° C)
65
75
85
95
105
115
125
135
145
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAX
11641-067
25
35
45
55
65
75
85
95
105
115
125
135
145
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
JUNCTION TEMP E R ATURE (° C)
6400mm2
500mm2
25mm2
TJMAX
11641-068
50
60
70
80
90
100
110
120
130
140
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TOTAL POWER DISSIPATION (W)
JUNCTION TEMP E R ATURE (° C)
6400mm
2
500mm
2
25mm
2
T
J
MAX
11641-069
65
75
85
95
105
115
125
135
145
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TOTAL POWER DISSIPATION (W)
JUNCTION TEMP E R ATURE (° C)
6400mm
2
500mm
2
25mm
2
T
J
MAX
11641-070
Data Sheet ADP7105
Rev. B | Page 23 of 26
In the case where the board temperature is known, use the ΨJB
thermal characterization parameter to estimate the junction
temperature rise (see Figure 77 and Figure 78). Maximum
junction temperature (TJ) is calculated from the board tempera-
ture (TB) and power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB) (5)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP package
and 31.3°C/W for the 8-lead SOIC package (see Table 7).
Figure 77. LFCSP
Figure 78. SOIC
TOTAL POWER DISSIPATION (W)
JUNCTION TEMP E R ATURE (T
J
)
0
20
40
60
80
100
120
140
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAX
11641-071
TOTAL POWER DISSIPATION (W)
JUNCTION TEMP E R ATURE (T
J
)
0
20
40
60
80
100
120
140
00.5 1.0 1.5 2.0 2.5 3.0 3.5
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAX
11641-072
ADP7105 Data Sheet
Rev. B | Page 24 of 26
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP7105.
However, as shown in Table 6, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0805 or 0603 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where space is limited.
Figure 79. Example LFCSP PCB Layout
Figure 80. Example SOIC PCB Layout
11641-073
11641-074
Data Sheet ADP7105
Rev. B | Page 25 of 26
OUTLINE DIMENSIONS
Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-5)
Dimensions shown in millimeters
Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-2)
Dimensions shown in millimeters
PIN 1
INDICATOR
(R 0. 2)
BOTTOM VIEW
TOP VIEW 1
4
8
5
INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
0.30
0.25
0.18
0.05 M AX
0.02 NO M
0.80 M AX
0.55 NO M
0.20 REF
0.50 BSC
COPLANARITY
0.08
2.48
2.38
2.23
1.74
1.64
1.49
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-229-WEE D- 4
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-B
0.20 M IN
EXPOSED
PAD
3.10
3.00 SQ
2.90
COMPLIANT TO JEDE C S TANDARDS MS-012-AA
06-03-2011-B
1.27
0.40
1.75
1.35
2.41
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
3.098
ADP7105 Data Sheet
Rev. B | Page 26 of 26
ORDERING GUIDE
Model1
Temperature
Range
Output
Voltage (V)
Package
Description
Package
Option Branding
ADP7105ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-5 LNS
ADP7105ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-5 LNT
ADP7105ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP_WD CP-8-5 LNU
ADP7105ACPZ-R2 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LNV
ADP7105ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LNV
ADP7105ARDZ-1.8 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ-3.3 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ-5.0
−40°C to +125°C
5
8-Lead SOIC_N_EP
RD-8-2
ADP7105ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2
ADP7105ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2
1 Z = RoHS Compliant Part.
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D11641-0-10/15(B)
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ADP7105ARDZ-3.3 ADP7105ARDZ-5.0 ADP7105ARDZ ADP7105ACPZ-R2 ADP7105ARDZ-5.0-R7
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ADP7105ARDZ-R7 ADP7105ACPZ-1.8-R7