Low Capacitance, 4-/8-Channel,
±15 V/+12 V iCMOS Multiplexers
ADG1208/ADG1209
Rev. B
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FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in 16-lead TSSOP, 4 mm × 4 mm LFCSP_VQ, and
16-lead SOIC
Typical power consumption < 0.03 μW
APPLICATIONS
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
ADG1208
S1
S8
D
ADG1209
S1A
S4B
DA
DB
S4A
S1B
1-OF-4
DECODER
1-OF-8
DECODER
A0 A1 ENA0 A1 A2 EN
05713-001
Figure 1.
GENERAL DESCRIPTION
The ADG1208 and ADG1209 are monolithic, iCMOS® analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight
inputs to a common output as determined by the 3-bit binary
address lines A0, A1, and A2. The ADG1209 switches one of
four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An
EN input on both devices is used to enable or disable the device.
When disabled, all channels are switched off. When on, each
channel conducts equally well in both directions and has an
input signal range that extends to the supplies.
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal-
oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
V
S
(V)
CHARGE INJECTION (pC)
1.0
0
–15 15
05713-051
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–10 –5 0 5 10
MUX (SOURCE TO DRAIN)
T
A
= 25°C
V
DD
=+15V
V
SS
= –15V
V
DD
=+5V
V
SS
=–5V
V
DD
=+12V
V
SS
=0V
Figure 2. Source to Drain Charge Injection vs. Source Voltage
ADG1208/ADG1209
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Test Circuits ..................................................................................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
1/09—Rev. A to Rev. B
Change to IDD Parameter, Table 1 ................................................... 4
Change to IDD Parameter, Table 2 ................................................... 6
4/07—Rev. 0 to Rev. A
Added 16-lead SOIC .......................................................... Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Figure 10 and Figure 11 ............................................. 10
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/06—Revision 0: Initial Version
ADG1208/ADG1209
Rev. B | Page 3 of 20
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 1.
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA, see Figure 29
200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between Channels, ∆RON 3.5 Ω typ VS = ±10 V, IS = −1 mA
6 10 12 Ω max
On Resistance Flatness, RFLAT (On) 20 Ω typ VS = −5 V/0 V/+5 V, IS = −1 mA
64 76 83 Ω max
LEAKAGE CURRENTS
Source Off Leakage, IS (Off) ±0.003 nA typ VD = ±10 V, VS = −10 V, see Figure 30
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V, see Figure 31
ADG1208 ±0.2 ±0.6 ±1 nA max
ADG1209 ±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±0.005 μA max VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION 80 ns typ RL = 300 Ω, CL = 35 pF
130 165 185 ns max VS = 10 V, see Figure 32
tON (EN) 75 ns typ RL = 300 Ω, CL = 35 pF
95 105 115 ns max VS = 10 V, see Figure 34
tOFF (EN) 83 ns typ RL = 300 Ω, CL = 35 pF
100 125 140 ns max VS = 10 V, see Figure 34
Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 10 V, see Figure 33
Charge Injection 0.4 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 35
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,
see Figure 39
−3 dB Bandwidth 550 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
CS (Off) 1 pF typ f = 1 MHz, VS = 0 V
1.5 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1208 6 pF typ f = 1 MHz, VS = 0 V
7 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1209 3.5 pF typ f = 1 MHz, VS = 0 V
4.5 pF max f = 1 MHz, VS = 0 V
ADG1208/ADG1209
Rev. B | Page 4 of 20
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
CD, CS (On) ADG1208 7 pF typ f = 1 MHz, VS = 0 V
8 pF max f = 1 MHz, VS = 0 V
CD, CS (On) ADG1209 5 pF typ f = 1 MHz, VS = 0 V
6 pF max f = 1 MHz, VS = 0 V
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.002 μA typ Digital inputs = 0 V or VDD
1.0 μA max
IDD 220 μA typ Digital inputs = 5 V
380 μA max
ISS 0.002 μA typ Digital inputs = 0 V or VDD
1.0 μA max
ISS 0.002 μA typ Digital inputs = 5 V
1.0 μA max
VDD/VSS ±5/±16.5 V min/max |VDD | = |VSS|
1 Temperature range is as follows: Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1208/ADG1209
Rev. B | Page 5 of 20
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 300 Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 29
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels, ∆RON 5 Ω typ VS = 0 V to 10 V, IS = −1 mA
16 26 27 Ω max
On Resistance Flatness, RFLAT (On) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V
Source Off Leakage, IS (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, see Figure 31
ADG1208 ±0.2 ±0.6 ±1 nA max
ADG1209 ±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±0.001
±0.1 μA max VIN = VINL or VINH
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION 100 ns typ RL = 300 Ω, CL = 35 pF
170 210 235 VS = 8 V, see Figure 32
tON (EN) 90 ns typ RL = 300 Ω, CL = 35 pF
110 140 160 VS = 8 V, see Figure 34
tOFF (EN) 105 ns typ RL = 300 Ω, CL = 35 pF
130 155 175 VS = 8 V, see Figure 34
Break-Before-Make Time Delay, tBBM 45 ns typ RL = 300 Ω, CL = 35 pF
20 ns min VS1 = VS2 = 8 V, see Figure 33
Charge Injection −0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 35
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
−3 dB Bandwidth 450 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
CS (Off) 1.2 pF typ f = 1 MHz, VS = 6 V
1.8 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1208 7.5 pF typ f = 1 MHz, VS = 6 V
9 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1209 4.5 pF typ f = 1 MHz, VS = 6 V
5.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1208 9 pF typ f = 1 MHz, VS = 6 V
10.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1209 6 pF typ f = 1 MHz, VS = 6 V
7.5 pF max f = 1 MHz, VS = 6 V
ADG1208/ADG1209
Rev. B | Page 6 of 20
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.002 μA typ Digital inputs = 0 V or VDD
1.0 μA max
IDD 220 μA typ Digital inputs = 5 V
380 μA max
VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V
1 Temperature range is as follows: Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
ADG1208/ADG1209
Rev. B | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog, Digital Inputs1
VSS − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)
Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Maximum)
100 mA
Operating Temperature Range
Industrial (Y Version) –40°C to +125°C
Storage Temperature –65°C to +150°C
Junction Temperature 150°C
θJA, Thermal Impedance, TSSOP 112°C/W
θJA, Thermal Impedance, LFCSP_VQ 30.4°C/W
θJA, Thermal Impedance, SOIC_N 77°C/W
Reflow Soldering Peak
Temperature (Pb-Free)
260(+0/−5)°C
1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG1208/ADG1209
Rev. B | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
EN
9
V
SS
S1
S4
S3
S2
A0
A2
GND
V
DD
S7
S6
S5
A1
ADG1208
TOP VIEW
(Not to Scale)
DS8
0
5713-002
PIN 1
INDICATOR
1
Figure 3. ADG1208 Pin Configuration (TSSOP/SOIC)
V
SS
2S1
3S2
4S3
11 VDD
12 GND
10 S5
9S6
5
S4
6
D
7
S8
8
S7
15 A0
16 EN
14 A1
13 A2
TOP VIEW
(Not to Scale)
ADG1208
05713-004
Figure 4. ADG1208 Pin Configuration (LFCSP_VQ),
Exposed Pad Tied to Substrate, VSS
Table 4. ADG1208 Pin Function Descriptions
Pin Number
TSSOP/SOIC LFCSP_VQ Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN
Active High Digital Input. When low, the device is disabled and all switches are off. When
high, Ax logic inputs determine on switches.
3 1 VSS Most Negative Power Supply Potential. In single-supply applications, it can be
connected to ground.
4 2 S1 Source Terminal 1. Can be an input or an output.
5 3 S2 Source Terminal 2. Can be an input or an output.
6 4 S3 Source Terminal 3. Can be an input or an output.
7 5 S4 Source Terminal 4. Can be an input or an output.
8 6 D Drain Terminal. Can be an input or an output.
9 7 S8 Source Terminal 8. Can be an input or an output.
10 8 S7 Source Terminal 7. Can be an input or an output.
11 9 S6 Source Terminal 6. Can be an input or an output.
12 10 S5 Source Terminal 5. Can be an input or an output.
13 11 VDD Most Positive Power Supply Potential.
14 12 GND Ground (0 V) Reference.
15 13 A2 Logic Control Input.
16 14 A1 Logic Control Input.
Table 5. ADG1208 Truth Table
A2 A1 A0 EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
ADG1208/ADG1209
Rev. B | Page 9 of 20
1
2
3
4
5
6
7
8
16
15
14
13
12
EN
V
SS
S1A
S2A
A0
GND
V
DD
S1B
S2B
A1
ADG1209
TOP VIEW
(Not to Scale)
11
10
9
S4A
S3A
S4B
DA DB
S3B
0
5713-003
PIN 1
INDICATOR
1V
SS
2S1A
3S2A
4S3A
11 S1B
12 V
DD
10 S2B
9S3B
15 A0
16 EN
14 A1
13 GND
TOP VIEW
(Not to Scale)
ADG1209
Figure 5. ADG1209 Pin Configuration (TSSOP/SOIC)
5
S4A
6
DA
7
DB
8
S4B
05713-005
Figure 6. ADG1209 Pin Configurations (LFCSP_VQ),
Exposed Pad Tied to Substrate, VSS
Table 6. ADG1209 Pin Function Descriptions
Pin Number
TSSOP/SOIC LFCSP_VQ Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3 1 VSS Most Negative Power Supply Potential. In single-supply applications, it can be
connected to ground.
4 2 S1A Source Terminal 1A. Can be an input or an output.
5 3 S2A Source Terminal 2A. Can be an input or an output.
6 4 S3A Source Terminal 3A. Can be an input or an output.
7 5 S4A Source Terminal 4A. Can be an input or an output.
8 6 DA Drain Terminal A. Can be an input or an output.
9 7 DB Drain Terminal B. Can be an input or an output.
10 8 S4B Source Terminal 4B. Can be an input or an output.
11 9 S3B Source Terminal 3B. Can be an input or an output.
12 10 S2B Source Terminal 2B. Can be an input or an output.
13 11 S1B Source Terminal 1B. Can be an input or an output.
14 12 VDD Most Positive Power Supply Potential.
15 13 GND Ground (0 V) Reference.
16 14 A1 Logic Control Input.
Table 7. ADG1209 Truth Table
A1 A0 EN On Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
ADG1208/ADG1209
Rev. B | Page 10 of 20
8
TYPICAL PERFORMANCE CHARACTERISTICS
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
200
100
0
–18 –15 –12 –9 –6 –3 12 1590631
180
160
140
120
80
60
40
20
T
A
= 25°C V
DD
= +15V
V
SS
=–15V
V
DD
= +16.5V
V
SS
= –16.5V
V
DD
= +13.5V
V
SS
= –13.5V
05713-030
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
600
300
0
–6 –4 –2 402 6
500
400
200
100
T
A
= 25°C
V
DD
=+5V
V
SS
=–5V
V
DD
=+5.5V
V
SS
= –5.5V
V
DD
= +4.5V
V
SS
=–4.5V
05713-031
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
450
250
300
0
02 46 12810 14
400
350
150
200
100
50
TA= 25°C
VDD =12V
VSS =0V
VDD =13.2V
VSS =0V
VDD =10.8V
VSS =0V
05713-032
Figure 9. On Resistance as a Function of VD (VS) for Single Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
250
0
–15 –10 –5 1005 15
150
200
100
50
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
V
DD
= +15V
V
SS
= –15V
05713-033
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
600
0
024 1068 12
300
400
200
500
100
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
V
DD
= 12V
V
SS
= 0V
05713-034
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
400
–400
0 102030405060708090100110120
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
300
200
100
0
–100
–200
–300
I
S
(OFF) + –
I
D
(OFF) + –
I
D
,
S
(ON) + +
I
S
(OFF) – +
I
D
,
S
(ON) – –
I
D
(OFF) – +
05713-057
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
Figure 12. ADG1208 Leakage Currents as a Function of Temperature, Dual Supply
ADG1208/ADG1209
Rev. B | Page 11 of 20
150
–150
0 102030405060708090100110120
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
100
50
0
–50
–100
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
,
S
(ON) – –
I
D
,
S
(ON) + +
05713-058
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
Figure 13. ADG1208 Leakage Currents as a Function of Temperature,
Single Supply
0
5713-035
LOGIC, IN
X
(V)
I
DD
(µA)
200
60
80
100
120
140
160
180
40
20
0
0 2 4 6 8 10121416
V
DD
= +12V
V
SS
=0V
V
DD
=+15V
V
SS
= –15V
I
DD
PER CHANNEL
T
A
=25°C
Figure 14. IDD vs. Logic Level
V
S
(V)
CHARGE INJECTION (pC)
1.0
0
–15 15
05713-040
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–10 –5 0 5 10
MUX (SOURCE TO DRAIN)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
V
DD
=+5V
V
SS
=–5V
V
DD
= +12V
V
SS
=0V
Figure 15. Source-to-Drain Charge Injection vs. Source Voltage
V
S
(V)
CHARGE INJECTION (pC)
6
–6
–15 15
05713-041
–10 –5 0 5 10
DEMUX (DRAIN TO SOURCE)
T
A
= 25°C
4
2
0
–2
–4
V
DD
= +15V
V
SS
=–15V
V
DD
=+5V
V
SS
= –5V
V
DD
=+12V
V
SS
=0V
Figure 16. Drain-to-Source Charge Injection vs. Source Voltage
350
0
–40
TEMPERATURE (°C)
TIME (ns)
300
250
200
150
100
50
–20 020 40 60 80 100 120
VDD =+5V
VSS =–5V
VDD =+12V
VSS =0V
VDD =+15V
VSS = –15V
05713-052
Figure 17. tON/tOFF Times vs. Temperature
0
5713-049
FREQUENCY (Hz)
OFF ISOLATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
10k 100k 1M 10M 100M 1G
V
DD
= +15V
V
SS
= –15V
T
A
=25°C
Figure 18. Off Isolation vs. Frequency
ADG1208/ADG1209
Rev. B | Page 12 of 20
FREQUENCY (Hz)
CROSSTALK (dB)
20
–120
10k 1G
05713-042
100k 1M 10M 100M
0
–20
–40
–60
–80
–100
V
DD
=+15V
V
SS
= –15V
T
A
=25°C
ADJACENT CHANNELS
NONADJACENT
CHANNELS
Figure 19. ADG1208 Crosstalk vs. Frequency
0
–120
10k 1G
FREQUENCY (Hz)
CROSSTALK (dB)
–20
–40
–60
–80
–100
100k 1M 10M 100M
ADJACENT CHANNELS
NONADJACENT
CHANNELS
05713-053
Figure 20. ADG1209 Crosstalk vs. Frequency
–
6.0
–10.0
10k 1G
FREQUENCY (Hz)
ON RESPONSE (dB)
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
100k 1M 10M 100M
05713-054
Figure 21. On Response vs. Frequency
FREQUENCY (Hz)
THD + N (%)
10
1
0.1
0.01
10 100 1k 10k 100k
LOAD = 10kΩ
T
A
= 25°C
V
DD
=+5V,V
SS
= –5V, V
S
= +3.5Vrms
V
DD
= +15V, V
SS
= –15V, V
S
=+5Vrms
05713-036
Figure 22. THD + N vs. Frequency
V
BIAS
(V)
CAPACITANCE (pF)
12
0
–15 15
05713-043
–10 –5 0 5 10
10
8
6
4
2
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
V
DD
= +15V
V
SS
= –15V
T
A
=25°C
Figure 23. ADG1208 Capacitance vs. Source Voltage,
±15 V Dual Supply
V
BIAS
(V)
CAPACITANCE (pF)
12
0
01
05713-045
2
246810
10
8
6
4
2
V
DD
=12V
V
SS
=0V
T
A
= 25°C
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
Figure 24. ADG1208 Capacitance vs. Source Voltage,
12 V Single Supply
ADG1208/ADG1209
Rev. B | Page 13 of 20
12
0
–5 5
V
BIAS
(V)
CAPACITANCE (pF)
10
8
6
4
2
–4 –3 –2 –1 0 1 2 3 4
V
DD
=+5V
V
SS
= –5V
T
A
= 25°C
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
05713-055
Figure 25. ADG1208 Capacitance vs. Source Voltage, ±5 V Dual Supply
V
BIAS
(V)
CAPACITANCE (pF)
8
0
–15 15
05713-046
–10 –5 0 5 10
V
DD
= +15V
V
SS
= –15V
T
A
=25°C
7
6
5
4
3
2
1
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
Figure 26. ADG1209 Capacitance vs. Source Voltage, ±15 V Dual Supply
V
BIAS
(V)
CAPACITANCE (pF)
8
0
01
05713-047
2
246810
V
DD
=12V
V
SS
=0V
T
A
=25°C
7
6
5
4
3
2
1
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply
8
0
–5 5
V
BIAS
(V)
CAPACITANCE (pF)
–4 –3 –2 –1 0 1 2 3 4
V
DD
=+5V
V
SS
= –5V
T
A
= 25°C
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
7
6
5
4
3
2
1
05713-056
Figure 28. ADG1209 Capacitance vs. Source Voltage, ±5 V Dual Supply
ADG1208/ADG1209
Rev. B | Page 14 of 20
TERMINOLOGY
RON
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog voltage on Terminal D, Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (On)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
IDD
Positive supply current.
ISS
Negative supply current.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ADG1208/ADG1209
Rev. B | Page 15 of 20
TEST CIRCUITS
I
DS
SD
V
S
V
05713-037
Figure 29. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
05713-038
Figure 30. Off Leakage
SD
A
VD
ID(ON)
NC
NC = NO CONNECT
05713-039
Figure 31. On Leakage
3V
0V
OUTPUT
t
r
< 20ns
t
f
<20ns
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
50% 50%
90%
90%
OUTPUT
ADG1208
1
A0
A1
A2
50Ω
300Ω
GND
S1
S2–S7
S8
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V
S1
V
S8
1
SIMILAR CONNECTION FOR ADG1209.
05713-022
Figure 32. Address to Output Switching Times, tTRANSITION
OUTPUT
ADG1208
1
A0
A1
A2
50Ω
300Ω
GND
S1
S2–S7
S8
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1209.
3V
0V
OUTPUT
80% 80%
ADDRESS
DRIVE (V
IN
)
t
BBM
05713-023
Figure 33. Break-Before-Make Delay, tBBM
OUTPUT
ADG1208
1
A0
A1
A2
50Ω300Ω
GND
S1
S2–S8
D
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1209.
3V
0V
O
UTPUT
50% 50%
tOFF
(EN)
tON
(EN)
0.9V
O
0.9V
O
ENABLE
D
R
IVE (V
IN
)
05713-024
Figure 34. Enable Delay, tON (EN), tOFF (EN)
ADG1208/ADG1209
Rev. B | Page 16 of 20
3V
V
IN
V
OUT
Q
INJ
=C
L
×ΔV
OUT
ΔV
OUT
DS
EN
GND C
L
1nF
V
OUT
V
IN
R
S
V
S
V
DD
V
SS
V
DD
V
SS
A0
A1
A2
ADG12081
1
SIMILAR CONNECTION FOR ADG1209.
05713-025
Figure 35. Charge Injection
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
S
D
50Ω
OFF ISOLATION = 20 log
V
OUT
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-026
Figure 36. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
S
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-027
Figure 37. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
05713-028
Figure 38. Channel-to-Channel Crosstalk
V
OUT
R
S
AUDIO PRECISION
R
L
10kΩ
IN
V
IN
S
D
V
S
Vp-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-029
Figure 39. THD + Noise
ADG1208/ADG1209
Rev. B | Page 17 of 20
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
2.25
2.10 SQ
1.95
16
5
13
8
9
12 1
4
1.95 BSC
PIN 1
INDICATOR TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
(BOTTOM VIEW)
12° MAX
1.00
0.85
0.80 SEATING
PLANE
0.35
0.30
0.25
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
0.65 BSC
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
0.25 MIN
021207-A
0.75
0.60
0.50
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-16-4)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 42. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
ADG1208/ADG1209
Rev. B | Page 18 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG1208YRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1208YRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1208YCPZ-REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
ADG1208YCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
ADG1208YRZ1 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1208YRZ-REEL71 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1209YRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1209YRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1209YCPZ-REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
ADG1209YCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
ADG1209YRZ1 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1209YRZ-REEL71 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
1 Z = RoHS compliant part.
ADG1208/ADG1209
Rev. B | Page 19 of 20
NOTES
ADG1208/ADG1209
Rev. B | Page 20 of 20
NOTES
©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05713-0-1/09(B)
