LT3487
1
3487f
Boost and Inverting
Switching Regulator
for CCD Bias
■ CCD Bias
■ TFT LCD Bias
■ OLED Bias
■ ±Rail Generation for Op Amps
■ Generates 15V at 45mA, –8V at 90mA from a
Li-Ion Cell
■ Output Disconnect
■ Sequencing: Positive Output Reaches Regulation
Before Negative Channel Begins Switching
■ Internal Schottky Diodes
■ 2MHz Constant Switching Frequency
■ Requires Only One Resistor per Channel to Set
Output Voltages
■ V
IN Range: 2.3V to 16V
■ Output Voltage Up to 28V
■ Short-Circuit Robust
■ Capacitor Programmable Soft-Start
■ Separate VBAT Pin Allows Separate Sources for
Power and Control Circuitry
■ Available in 10-Lead (3mm × 3mm) DFN Package
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
The LT®3487 dual channel switching regulator generates
positive and negative outputs for biasing CCD imagers.
The device delivers up to –8V at 90mA and 15V at 45mA
from a lithium-ion cell, providing bias for many popular
CCD imagers. The boost regulator incorporates output
disconnect technology to eliminate the DC current path
from VIN to the output load that is present in standard
boost confi gurations. The 2MHz switching frequency
allows CCD solutions using tiny, low profi le capacitors
and inductors and generates low noise outputs that are
easy to fi lter. Schottky diodes are internal and the output
voltages are set with one resistor per channel, reducing
the external component count.
Intelligent soft-start allows sequential soft-start of the two
channels with a single capacitor. The soft-start is sequenced
such that the output ramp of the negative channel begins
after the ramp of the positive channel. Internal sequencing
circuitry also disables the negative channel until the positive
channel has reached 87% of its fi nal value, ensuring that
the sum of the two outputs is always positive.
The LT3487 is available in a 10-pin 3mm × 3mm DFN
package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
SWN
15µH10µH
VIN CAP
549k
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
15µH
324k
47pF
FBN
RUN/SSRUN/SS
VNEG
–8V
90mA
100nF
4.7µF
3487 TA01a
100nF
VPOS
15V
45mA
1µF
2.2µF
22µF
VIN
3V TO 12V
Conversion Effi ciency
LOAD CURRENT (mA)
0
EFFICIENCY (%)
55
60
65
60 100
3487 TA01b
50
45
40 20 40 80
70
75
80 POS CHANNEL AT CAP
NEG CHANNEL
POS CHANNEL
AT VPOS
VIN = 3.6V
LT3487
2
3487f
VIN Voltage ............................................................... 16V
VBAT Voltage ............................................................. 16V
SWP, SWN Voltage ................................................... 32V
CAP, VPOS .................................................................30V
DN Voltage ............................................................. –32V
RUN/SS Voltage ..........................................................8V
FBP Voltage ................................................................ 6V
FBN Voltage ................................................ –0.2V to 6V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range ................. –40°C to 85°C
Storage Temperature Range ................... –65°C to 125°C ORDER PART NUMBER DD PART MARKING
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
LBXB
LT3487EDD
(Note 1)
The
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range 2.3 16 V
Quiescent Current RUN/SS = 3V, Not Switching
RUN/SS = 0V
3.7
5.3
5
8
mA
µA
RUN/SS Voltage Threshold (Full Current) (Note 3) 1.6 V
RUN/SS Voltage Threshold (Shutdown) ●100 160 mV
RUN/SS Pin Current RUN/SS = 0V (Note 4) 1 1.4 2 µA
FBP (Positive Channel) Pin Voltage ●1.19 1.23 1.27 V
FBN (Negative Channel) Pin Voltage ●–7 3 12 mV
FBP Pin Voltage Line Regulation 0.007 %/V
FBN Pin Voltage Line Regulation 0.001 mV/V
FBP Pin Bias Current ●24.4 25 25.6 µA
FBN Pin Bias Current ●24.4 25 25.6 µA
FBP Threshold (Percent of Final Value)
to Start Negative Channel
87 90 %
Switching Frequency 1.85 2 2.15 MHz
Maximum Duty Cycle ●87 93 %
Positive Channel Switch Current Limit (Note 5) ●750 920 mA
Negative Channel Switch Current Limit (Note 5) ●900 1090 mA
Positive Channel VCESAT ISWP = 400mA 280 mV
Negative Channel VCESAT ISWN = 600mA 340 mV
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1VPOS
FBP
RUN/SS
FBN
VIN
CAP
SWP
VBAT
SWN
DN
θJA = 43°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO PCB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LT3487
3
3487f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Schottky DP Forward Drop ISWP = 400mA 1045 mV
Schottky DN Forward Drop ISWN = 600mA 980 mV
Disconnect PNP VCE IVPOS = 50mA 205 mV
Disconnect Current Limit VCAP = 15V, VPOS = 0V 100 155 mA
VCAP – VBAT to Disconnect VBAT = 3.6V, VPOS = 0V, ICAP < 100µA 1.2 1.6 V
Disconnect Leakage VBAT = 3.6V, CAP = 3.6V, VPOS = 0V 0.1 1.0 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3487E is guaranteed to meet specifi ed performance from
0°C to 85°C. Specifi cations over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
Shutdown Quiescent Current Positive Output to Enable Inverter FBP Voltage
Note 3: Guaranteed by design, not directly tested.
Note 4: Current fl ows out of pin.
Note 5: Current limit guaranteed by design and/or correlation to static test.
Slope compensation reduces current limit at higher duty cycle.
TEMPERATURE (°C)
–50 –25
0
QUIESCENT CURRENT (µA)
4
10
050 75
3487 G01
2
8
6
25 100 125
TEMPERATURE (°C)
–50 –25
50
PERCENTAGE OF FINAL FBP VOLTAGE (%)
70
100
050 75
3487 G02
60
90
80
25 100 125
TEMPERATURE (°C)
–50
1.200
VFBP (V)
1.225
1.250
1.275
1.300
–25 0 25 50
3487 G03
75 100 125
LT3487
4
3487f
Positive Channel Switch VCE(SAT)
Positive Channel Schottky I-V
Characteristic
Negative Channel Schottky I-V
Characteristic
Output Disconnect Voltage Drop
(50mA Load)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Negative Channel Switch VCE(SAT)
FBN Voltage FBP Bias Current FBN Bias Current
TEMPERATURE (°C)
–50
VFBN (mV)
7.5
25
3487 G04
0
–5.0
–25 0 50
–7.5
–10.0
10.0
5.0
2.5
–2.5
75 100 125
TEMPERATURE (°C)
–50
24.0
IFBP (µA)
24.5
25.0
25.5
26.0
–25 0 25 50
3487 G05
75 100 125
TEMPERATURE (°C)
–50
24.0
IFBN (µA)
24.5
25.0
25.5
26.0
–25 0 25 50
3487 G06
75 100 125
SWITCH CURRENT (mA)
0
0
POSITIVE SWITCH SATURATION VOLTAGE (mV)
100
200
300
400
500
100 200 300 400
3487 G07
500 600
SWITCH CURRENT (mA)
0
0
NEGATIVE SWITCH SATURATION VOLTAGE (mV)
100
300
400
500
200 400 500 900
3487 G08
200
100 300 600 700 800
SCHOTTKY FORWARD DROP (mV)
600
0
POSITIVE SCHOTTKY FORWARD CURRENT (mA)
100
200
300
400
700 800 900 1000
3487 G09
500
600
650 750 850 950
SCHOTTKY FORWARD DROP (mV)
600
NEGATIVE SCHOTTKY FORWARD CURRENT (mA)
400
600
1000
3487 G10
200
0700 800 900
650 750 850 950
800
300
500
100
700
TEMPERATURE (°C)
–50
100
VCAP – VPOS (mV)
150
200
250
300
–25 0 25 50
3487 G11
75 100 125
VCAP – VBAT (V)
0
100
120
140
10
3487 G20
80
60
2.5 5 7.5 12.5
40
20
0
ICAP (mA)
VCAP – VPOS = 500mV
TA = 25°C
Maximum Disconnect Current
LT3487
5
3487f
TEMPERATURE (°C)
–50
IRUN/SS (µA)
2.0
2.5
3.0
25 75
3487 G16
1.5
1.0
–25 0 50 100 125
0.5
0
VIN (V)
2
0
RUN/SS PIN CURRENT (µA)
0.5
1.0
1.5
2.0
46810
3487 G17
12 14 16
Output Disconnect Current Limit Switch Current Limits
Switch Current Limits
vs Duty Cycle
Switch Current Limits vs RUN/SS
Voltage (at 55% Duty Cycle) RUN/SS Pin Current in Shutdown
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RUN/SS Pin Current
vs VIN in Shutdown
UVLO Voltage
TEMPERATURE (°C)
–50
100
CURRENT LIMIT (mA)
125
150
175
200
–25 0 25 50
3487 G12
75 100 125
VCAP = 15V
VBAT = 3.6V
VPOS = 0V
TEMPERATURE (°C)
–50
CURRENT LIMITS (mA)
1150
25
3487 G13
1000
900
–25 0 50
850
800
1200
1100
1050
950
75 100 125
NEG CHANNEL
POS CHANNEL
DUTY CYCLE (%)
0
0
CURRENT LIMITS (mA)
200
400
600
800
1000
1200
20 40 60 80
3487 G14
100
NEG CHANNEL
P0S CHANNEL
RUN/SS (mV)
0
0
CURRENT LIMITS (mA)
200
400
600
800
1000
250 500 750 1000
3487 G15
1250 1500
NEG CHANNEL
P0S CHANNEL
TEMPERATURE (°C)
–50 –25
2.0
UVLO (V)
2.2
2.5
050 75
3487 G18
2.1
2.4
2.3
25 100 125
TEMPERATURE (°C)
–50
VRUN/SS (mV)
200
250
300
25 75
3487 G19
150
100
–25 0 50 100 125
50
0
RUN/SS Shutdown Threshold
LT3487
6
3487f
PI FU CTIO S
UUU
CAP (Pin 1): Disconnect-PNP Emitter and Positive Schottky
Cathode. Acts as an intermediate positive (boost) output.
Connect boost output capacitor to this pin.
SWP (Pin 2): Switch Pin and Schottky Anode for Positive
Channel. Connect boost inductor to this pin.
VBAT (Pin 3): Battery Voltage. Connect this pin to the sup-
ply voltage for the boost inductor. The disconnect drive
current is returned to this pin. The disconnect operates
until CAP falls to 1.2V above VBAT.
SWN (Pin 4): Switch Pin for Negative (Inverter) Chan-
nel. Connect inverter input inductor and fl ying capacitor
here.
DN (Pin 5): Anode of Internal Schottky for Inverter. Connect
inverter output inductor and fl ying capacitor here.
VIN (Pin 6): Input Supply Pin. VIN is used to power the
control circuitry of the LT3487. This pin must be locally
bypassed with an X5R or X7R type ceramic capacitor.
FBN (Pin 7): Feedback Pin for Inverter. Connect feedback
resistor R2 from this pin to VNEG. Choose R2 according
to:
RV
µA
NEG
225
=–
Pin voltage = 0V when regulated.
RUN/SS (Pin 8): Run/Soft-Start Pin. Connect to an open-
drain transistor. The transistor must sink 1.4µA from
RUN/SS. Pull RUN/SS below 100mV to shut down the chip.
Connect a capacitor from RUN/SS to ground to program
soft-start functionality. The soft-start will slowly bring the
boost channel into regulation and then slowly bring up
the inverter. RUN/SS must be above 1.6V to allow both
channels to reach full current. If soft-start is not required,
this pin can be driven with a logic signal, but the RUN/SS
voltage must remain below VIN.
FBP (Pin 9): Feedback Pin for Boost. Connect boost
feedback resistor R1 from FBP to CAP. Choose R1 ac-
cording to:
RV
µA
POS
1123
25
=–.
Pin voltage = 1.23V when regulated.
VPOS (Pin 10): Output Pin for Boost Channel. VPOS is
the collector of the output disconnect PNP. Connect the
boost load to VPOS. Connect capacitor C5 between CAP
and VPOS for stability.
Exposed Pad (Pin 11): GND. Tie directly to ground plane
through multiple vias under the package for optimum
thermal performance.
LT3487
7
3487f
BLOCK DIAGRA
W
Figure 1. Block Diagram
–
+
A2
–
+
A3 VCN
–
+
A4
–
+
A1
49.2k VCP
R
X1
SQ
DP
Q1
Q3
DN
DISCONNECT
PNP ANTISAT
RAMP
GENERATOR
2MHz
OSCILLATOR
1.25V
CAP
C5
VPOS
VBAT
C4
SWP
VBAT
L1
R
Q2
X2
SQ
+
3
10
GND 11
SWN
VBAT
4
DN 5
1
2
R1
RAMP
GENERATOR
C2
VNEG
3487 BD
C3
L2
L3
+160mV
49.2k
1.4µA
VIN
VBAT
VREF
1.23V
6
FBP
CAP
9
RUN/SS
8
FBN
VNEG
7
C1
C6
M1
RUN
R2
C7
–+
Σ
Σ
LT3487
8
3487f
Operation
The LT3487 uses a constant frequency, current mode con-
trol scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the Block
Diagram in Figure 1. At the start of each oscillator cycle,
the SR latch X1 is set, which turns on the power switch
Q1. A voltage proportional to the switch current is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A2. When this
voltage exceeds the level at the negative input of A2, the
SR latch X1 is reset, turning off the power switch Q1. The
level at the negative input of A2 is set by the error amplifi er
A1, and is simply an amplifi ed version of the difference
between the feedback voltage and the reference voltage
of 1.23V. In this manner, the error amplifi er sets the cor-
rect peak current level to keep the output in regulation.
If the error amplifi er’s output increases, more current is
delivered to the output; if it decreases, less current is
delivered. The second channel is an inverting converter.
The basic operation is the same as the positive channel.
The SR latch X2 is also set at the start of each oscillator
cycle. The power switch Q2 is turned on at the same time
as Q1. Q2 turns off based on its own feedback loop, which
consists of error amplifi er A3 and PWM comparator A4.
The reference voltage of this negative channel is ground.
Voltage clamps on VCP and VCN (not shown) enforce current
limit. Switching waveforms with typical load conditions
are shown in Figure 2.
The PNP Q3 is used as an output disconnect pass transistor.
Q3 disconnects the load from the input during shutdown.
The anti-sat driver keeps Q3 at the edge of saturation as
long as CAP is typically 1.2V and worst-case 1.6V (cold)
above the VBAT voltage. The drive current for the output
disconnect PNP is returned to the VBAT pin. This allows
the pass transistor to turn off when the CAP voltage
falls to less than 1.2V above VBAT. The VBAT pin allows
applications in which the power (inductors L1 and L2)
and internal control circuitry (VIN pin) are powered from
different sources.
Inductor Selection
A 10μH inductor is recommended for the LT3487 boost
channel. The inverting channel can use uncoupled 15μH
inductors, or coupled 10μH inductors. Small size and
high effi ciency are the major concerns for most LT3487
applications. Inductors with low core losses and small
DCR (copper wire resistance) at 2MHz are good choices
for LT3487 applications. The inductor DCR should be on
the order of half of the switch on-resistance for its chan-
nel. Some inductors in this category with small size are
listed in Table 1.
Table 1. Recommended Inductors
PART NUMBER
INDUCTANCE
(μH)
DCR
(Ω)
CURRENT
RATING
(mA) MANUFACTURER
DB318C-A997AS-
100M
10 0.18 580 Toko
www. tokoam.com
CDRH3D18-100
CDRH2D18HP-100
CDRH3D23-100
CDRH2D18/HP-150
CDRH3D18-150
CDRH3D23-150
10
10
10
15
15
15
0.205
0.245
0.117
0.345
0.301
0.191
900
850
850
700
750
700
Sumida
www.sumida.com
Capacitor Selection
The small size of ceramic capacitors makes them suitable
for LT3487 applications. X5R and X7R types of ceramic
capacitors are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 1μF input capaci-
tor is suffi cient for most LT3487 applications. The output
capacitors required for stability depend on the application.
For the typical Li-Ion to +15V, –8V application, the positive
channel requires a 4.7μF output capacitor and the negative
channel requires at least 10μF of capacitance.
APPLICATIO S I FOR ATIO
WUUU
Figure 2. Switching Waveforms
VSWP
20V/DIV
VSWN
20V/DIV
ISWN
100mA/DIV
200ns/DIV 3487 F02
VIN = 3.6V
VPOS = 15V, 25mA
VNEG = –8V, 50mA
ILI
100mA/DIV
LT3487
9
3487f
Table 2. Recommended Ceramic Capacitor Manufacturers
MANUFACTURER PHONE URL
Taiyo Yuden (408) 573-4150 www.t-yuden.com
Murata (814) 237-1431 www.murata.com
Kemet (408) 986-0424 www.kemet.com
Inrush Current
The LT3487 uses internal Schottky diodes. When a sup-
ply voltage is abruptly applied to the VIN pin, the voltage
difference between VIN and VCAP generates inrush current
fl owing from the input through the inductor L1 and the
internal Schottky diode DP to charge the boost output
capacitor C4. For the inverting channel, there is a similar
inrush current fl owing from the input through the inductor
L2 path, charging the fl ying capacitor C2 and returning
through the internal Schottky diode DN. The maximum
current the Schottky diodes in the LT3487 can sustain is
2A. The selection of inductor and capacitor values should
ensure that the peak inrush current is below 2A. The peak
inrush current can be calculated as follows:
IV
LeSIN
PIN
=
⎛
⎝
⎜⎞
⎠
⎟
–.
•• • arctan
– •arctan
06
ω
α
ω
ω
αωω
α
α
ω
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
=+
=
r
L
LC
r
L
15
2
1
42
.
•
•–•
where L is the inductance, r is the resistance of the inductor
and C is the output capacitance. For low DCR inductors,
which is usually the case for this application, the peak
inrush current can be simplifi ed as follows:
IV
L
e
PIN
=
⎛
⎝
⎜⎞
⎠
⎟
–.
••
–•
06 2
ω
α
ω
π
Table 3 gives inrush peak currents for some component
selections. Note that inrush current is not a concern if the
input voltage rises slowly.
Table 3. Inrush Peak Current
VIN (V) R (Ω) L (μH) C (μF) I
P (A)
5 0.18 10 4.7 1.44
5 0.235 15 2.2 1.06
3.6 0.18 10 4.7 0.979
3.6 0.245 10 4.7 0.958
3.6 0.345 15 2.2 0.704
External Diode Selection
As stated previously, the LT3487 has internal Schottky
diodes. The Schottky diode, DP, is suffi cient for most
step-up applications. However, for high current inverter
applications, a properly selected external Schottky diode in
parallel with DN can improve effi ciency. For external diode
selection, both forward voltage drop and diode capacitance
need to be considered. Schottky diodes rated for higher
current usually have lower forward voltage drops and
larger capacitance, which can cause signifi cant switching
losses at a 2MHz switching frequency. Some recommended
Schottky diodes are listed in Table 4.
APPLICATIO S I FOR ATIO
WUUU
Table 4. Recommended Schottky Diodes
PART NUMBER FORWARD CURRENT (mA) FORWARD VOLTAGE DROP (V)
DIODE CAPACITANCE
(pF at 10V) MANUFACTURER
PMEG2010AEB 1000 0.51 7.5 Philips
www.semiconductors.
philips.com
CMDSH2-3 200 0.49 15 Central Semiconductor
www.centralsemi.com
RSX051VA-30 500 0.35 30 ROHM
www.rohm.com
ZHCS400 400 0.425 18 Zetex
www.zetex.com
LT3487
10
3487f
Setting the Output Voltages
The LT3487 has an accurate internal feedback resistor
that is trimmed to set the feedback currents to 25µA for
each channel. Only one resistor is needed to set the output
voltage for each channel. The output voltage can be set
according to the following formulas:
RV
µA
RV
µA
POS
NEG
1123
25
225
=⎛
⎝
⎜⎞
⎠
⎟
=
–.
–
In order to maintain accuracy, high precision resistors are
preferred (1% is recommended).
Soft-Start
The LT3487 has a single soft-start control for both chan-
nels. The RUN/SS pin is fed by a 1.4μA current source.
The soft-start ramp can be programmed by connecting a
capacitor from the RUN/SS pin to ground. An open-drain
transistor should be used to pull the pin low to shut down
the LT3487. Once the transistor stops sinking the 1.4μA,
the capacitor begins to charge. The chip starts up when
the RUN/SS pin charges to 160mV. The VCP node voltage
follows the RUN/SS voltage as it continues to ramp up
to ensure slow start-up on the positive channel. The VCN
node follows the ramp voltage, down a VBE. This ensures
that the negative channel starts up after the positive, but
still has a slow ramping output to avoid large start-up
currents.
Start Sequencing
The LT3487 also has internal sequencing circuitry that
inhibits the negative channel from operating until the
feedback voltage of the boost channel reaches about 1.1V
(87% of the fi nal voltage), ensuring that the sum of the
two outputs is always positive.
There are two ways in which the negative channel may
start up, depending on the size of the soft-start capacitor.
If there is no soft-start capacitor, or a very small capacitor,
then the negative channel will start up when the positive
output reaches 87% of its fi nal value. If a large enough
soft-start capacitor is used, then the RUN/SS voltage will
continue to clamp the negative channel past the point
where the positive channel is in regulation. Figure 3 shows
the start-up sequencing without soft-start, with a small
soft-start capacitor, and a large soft-start capacitor.
Output Disconnect
The output disconnect uses a PNP transistor with circuitry
that varies the base current such that the transistor is
consistently at the edge of saturation, thus yielding the
best compromise between VCE(SAT) and low quiescent
current. To remain stable, this circuit requires a bypass
capacitor connected between the VPOS pin and the CAP pin
or between the VPOS pin and ground. A ceramic capacitor
with a value of at least 0.1μF is a good choice. Figure 4
shows that the PNP can support load currents of 50mA
with a VCE less than 210mV. The disconnect transistor is
current limited to provide a maximum of 155mA in short
circuit.
APPLICATIO S I FOR ATIO
WUUU
Figure 3a. VRUN/SS, VPOS, VNEG,
IIN with No Soft-Start Capacitor
Figure 3b. VRUN/SS, VPOS, VNEG,
IIN with a 10nF Soft-Start Capacitor
Figure 3c. VRUN/SS, VPOS, VNEG, IIN
with a 100nF Soft-Start Capacitor
VRUN/SS
2V/DIV
IIN
1A/DIV
VPOS
10V/DIV
VNEG
10V/DIV
500µs/DIV 3487 F03a
VRUN/SS
2V/DIV
IIN
500mA/DIV
VPOS
10V/DIV
VNEG
10V/DIV
2ms/DIV 3487 F03b
VRUN/SS
2V/DIV
IIN
200mA/DIV
VPOS
10V/DIV
VNEG
10V/DIV
10ms/DIV 3487 F03c
LT3487
11
3487f
Figure 4. VCE vs I of Output Disconnect
Choosing a Feedback Node
The positive channel feedback resistor, R1, may be con-
nected to the VPOS pin or to the CAP pin (see Figure 5).
Regulating the VPOS pin eliminates the output offset result-
ing from the voltage drop across the output disconnect.
However, in the case of a short-circuit fault at the VPOS
pin, the LT3487 will switch continuously because the FBP
pin is low. While operating in this open-loop condition, the
rising voltage at the CAP pin is limited only by the current
limit of the output disconnect. Given worst-case parameters
this voltage may reach 18V in a Li-Ion application. Care
must be taken in high VIN applications when regulating
from the VPOS pin. When the short-circuit is removed, the
VPOS pin will bounce up to the voltage on the CAP pin,
potentially exceeding the programmed output voltage until
the capacitor voltages fall back into regulation. While this
is harmless to the LT3487, this should be considered in
the context of the external circuitry if short-circuit events
are expected. Regulating the CAP pin ensures that the
voltage on the VPOS pin never exceeds the set output volt-
age after a short-circuit event. However, this setup does
not compensate for the voltage drop across the output
disconnect, resulting in an output voltage that is slightly
lower than the voltage set by the feedback resistor. This
voltage drop (VDISC) can be accounted for when using
the CAP pin as the feedback node by setting the output
voltage according to the following formula (using VDISC
from Figure 4):
RV
µA
DISC
1123
25
=+VPOS –.
VBAT
The VBAT pin is a new innovation in the LT3487 that allows
output disconnect operation in a wide range of applica-
tions. The VBAT pin allows the part to stay on until CAP is
less than 1.2V above VBAT. This ensures that the positive
bias doesn’t fall before the negative bias discharges. In
some applications it may be useful to power the inductors
from a different source than VIN. In this case, connect
VBAT to the source powering the inductors to allow proper
operation of the disconnect. For example, in an automotive
system there may already be a buck regulator producing
3.3V from a 12V battery. The LT3487 enables the user
to power VIN from the 3.3V rail, but power the VBAT pin
APPLICATIO S I FOR ATIO
WUUU
Figure 5. Feedback Connection Using the VPOS and CAP Pins
DISCONNECT CURRENT (mA)
0
0
DISCONNECT SATURATION VOLTAGE (mV)
50
100
150
200
250
300
20 40 60 80
2400 G31
100
SWN
VIN CAP
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
FBN
RUN/SS
3487 F05
VPOS
SWN
VIN CAP
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
FBN
RUN/SS VPOS
LT3487
12
3487f
APPLICATIO S I FOR ATIO
WUUU
and the inductors directly from the battery for higher ef-
fi ciency. When the part goes into shutdown, the output
load is isolated from the 12V source as soon as the CAP
node falls to below VBAT plus 1.2V (13.2V in this case).
The VBAT pin is also useful in a system using a 2V supply
(such as a 2-cell alkaline battery), below the operating
range of the LT3487. A boost converter designed for low
voltage operation can provide 3.3V for the LT3487 VIN pin,
while the inductors and VBAT can still be powered from the
2V supply. In shutdown, the 3.3V supply will turn off, but
the output disconnect will still decouple the output load
as soon as CAP falls below 3.2V .
Figure 6. Recommended Component Placement
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize effi ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have rise and fall times of a few ns.
Minimize the length and area of all traces connected to
the SWP and SWN pins and always use a ground plane
under the switching regulator to minimize interplane
coupling. Recommended component placement is shown
in Figure 6.
VNEG
VIN
VBAT
VPOS
RUN
3487 F06
FBP
CAP
L1 L1
L3
U1
C5
C8
R1
C6
C4
M1
C2 C1
R2
C7
LT3487
13
3487f
TYPICAL APPLICATIO
U
VPOS Load Step Response VNEG Load Step Response
+15V and –8V Boost and Inverting CCD Bias
SWN
L2
15µH
L1
10µH
VIN CAP
R1
549k
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
L3
15µH
R2 324k
C7 47pF
FBN
RUN/SSRUN/SS
VNEG
–8V
90mA
C6
100nF
C4
4.7µF
3487 TA02a
C5
100nF
VPOS
15V
45mA
C1
1µF
C2
2.2µF
C3
22µF
VIN
3V TO 12V
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
VPOS
100mV/DIV
AC-COUPLED
45mA
IPOS 15mA
100µs/DIV 3487 TA02b
VIN = 3.6V
VNEG
20mV/DIV
AC-COUPLED
–50mA
INEG
–90mA
100µs/DIV 3487 TA02c
VIN = 3.6V
The positive channel’s response is stable, but slightly
underdamped. A phase lead capacitor (C8) can be added
to provide more ideal phase margin.
VPOS Load Step Response (with Phase Lead Capacitor)
VPOS
100mV/DIV
AC-COUPLED
45mA
IPOS 15mA
100µs/DIV 3487 TA02d
VIN = 3.6V
CAP
R2
549k
C8
10pF
FBP 3487 TA02e
LT3487
14
3487f
TYPICAL APPLICATIO S
U
+15V and –8V Low VIN CCD Bias
SWN
L2
15µH
L1
10µH
VIN CAP
R1
549k
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
L3
15µH
R2 324k
C7 33pF
FBN
RUN/SSRUN/SS
VNEG
–8V
80mA
C6
100nF
C4
4.7µF
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN EMK212BJ225MD-TR
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
3487 TA03
C5
100nF
C8
15pF
VPOS
15V
40mA
C1
1µF
C2
2.2µF
C3
22µF
VIN
2.7V TO 5V
+15V and –8V Boost and Charge Pump CCD Bias
SWN
L2
15µH
L1
10µH
VIN CAP
R1
549k
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
D1
R2 324k
C7 20pF
FBN
RUN/SSRUN/SS
VNEG
–8V
90mA
C6
100nF
C4
4.7µF
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN EMK316BJ106ML
C4: TAIYO YUDEN TMK316BJ475ML-TR
D1: PHILIPS PMEG2010AEB
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
3487 TA04
C5
100nF
VPOS
15V
45mA
C1
1µF
C2
2.2µF
C3
10µF
VIN
3V TO 12V
LT3487
15
3487f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PACKAGE DESCRIPTIO
U
LT3487
16
3487f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0406 • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LT1944/LT1944-1 Dual Output 350mA/100mA ISW, Constant Off-Time,
High Effi ciency DC/DC Converter
VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20µA, ISD < 1µA, 10-Lead
MS Package
LT1945 Dual Output, Boost/Inverter, 350mA ISW, Constant Off-Time,
High Effi ciency DC/DC Converter
VIN: 1.2V to 15V, VOUT(MAX) = ±34V, IQ = 40µA, ISD < 1µA, 10-Lead
MS Package
LT1947 Triple Output, 3MHz, High Effi ciency DC/DC Converter VIN: 2.6V to 8V, VOUT(MAX) = ±34V, IQ = 9.5mA, ISD < 1µA, 10-Lead
MS Package
LTC®3450 Triple Output, 550kHz, High Effi ciency DC/DC Converter VIN: 1.4V to 4.6V, VOUT(MAX) = ±15V, IQ = 75µA, ISD < 2µA,
DFN Package
LT3463/LT3463A Dual Output, Boost/Inverter, 250mA ISW, Constant Off-Time,
High Effi ciency DC/DC Converter with Integrated Schottkys
VIN: 2.2V to 16V, VOUT(MAX) = ±40V, IQ = 2.8mA, ISD < 1µA,
DFN Package
LT3471 Dual Output, Boost/Inverter, 1.3A ISW, 1.2MHz, High
Effi ciency DC/DC Converter
VIN: 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD < 1µA,
DFN Package
LT3472/LT3472A Dual Output, Boost/Inverter, 350mA/400mA ISW, 1.2MHz,
High Effi ciency DC/DC Converter with Integrated Schottkys
VIN: 2.3V to 15V, VOUT(MAX) = ±40V, IQ = 40µA, ISD < 1µA,
DFN Package
RELATED PARTS
TYPICAL APPLICATIO
U
+24V and –16V LCD Bias
SWN
L2
22µH
L1
15µH
VIN CAP
R1
931k
FBP
VPOS
VBAT
LT3487
GND
SWP
DN
L3
22µH
R2 640k
C7 33pF
FBN
RUN/SSRUN/SS
VNEG
–16V
26mA
C6
100nF
C4
10µF
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ106KL-T
L1: SUMIDA CDRH2D18/HP-150NC
L2, L3: TOKO D53LC-A915AY-220M
3487 TA05
C5
100nF
C8
15pF
VPOS
24V
24mA
C1
1µF
C2
2.2µF
C3
22µF
VIN
3V TO 6V
