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FDP2532 / FDB2532 N-Channel PowerTrench(R) MOSFET 150 V, 79 A, 16 m Features Applications * RDS(on) = 14 m ( Typ.) @ VGS = 10 V, ID = 33 A * Consumer Appliances * QG(tot) = 82 nC ( Typ.) @ VGS = 10 V * Synchronous Rectification * Low Miller Charge * Battery Protection Circuit * Low Qrr Body Diode * Motor drives and Uninterruptible Power Supplies * UIS Capability (Single Pulse and Repetitive Pulse) * Micro Solar Inverter Formerly developmental type 82884 D D GD S G TO-220 G D2-PAK S S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol FDP2532 / FDB2532 Unit VDSS Drain to Source Voltage 150 V VGS Gate to Source Voltage 20 V 79 A Parameterr Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, R JA = 43oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) 56 A 8 A Figure 4 A 400 mJ Power dissipation 310 W Derate above 25oC 2.07 W/oC -55 to 175 oC Operating and Storage Temperature Thermal Characteristics RJC Thermal Resistance Junction to Case, Max. TO-220, D2-PAK RJA Thermal Resistance Junction to Ambient, Max. TO-220, D2-PAK (Note 2) RJA Thermal Resistance Junction to Ambient (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 D2-PAK, 1 Max. 1in2 0.61 copper pad area oC/W 62 o C/W 43 o C/W www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET October 2013 Device Marking FDB2532 Device FDB2532 Package D2-PAK Reel Size 330 mm Tape Width 24 mm Quantity 800 units FDP2532 FDP2532 TO-220 Tube N/A 50 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit V Off Characteristics B VDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 150 - - - - 1 - - 250 VGS = 20V - - 100 nA VGS = VDS, ID = 250A 2 - 4 V - 0.014 0.016 ID = 16A, VGS = 6V, - 0.016 0.024 - 0.040 0.048 - 5870 - pF - 615 - pF - 135 - pF - 82 107 nC VDS = 120V VGS = 0V TC = 150oC A On Characteristics VGS(TH) Gate to Source Threshold Voltage rDS(ON) Drain to Source On Resistance ID = 33A, VGS = 10V ID = 33A, VGS = 10V, TC = 175oC Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V VGS = 0V to 2V Qg(TH) Threshold Gate Charge Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VDD = 75V ID = 33A Ig = 1.0mA - 11 14 nC - 23 - nC - 13 - nC - 19 - nC ns Resistive Switching Characteristics (VGS = 10V) tON Turn-On Time - - 69 Turn-On Delay Time - 16 - ns tr Rise Time - 30 - ns tf td(ON) VDD = 75V, ID = 33A V GS = 10V, RGS = 3.6 td(OFF) Turn-Off Delay Time - 39 - ns Fall Time - 17 - ns tOFF Turn-Off Time - - 84 ns ISD = 33A - - 1.25 V ISD = 16A - - 1.0 V Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage trr Reverse Recovery Time ISD = 33A, dISD/dt= 100A/s - - 105 ns QRR Reverse Recovery Charge ISD = 33A, dISD/dt= 100A/s - - 327 nC Notes: 1: Starting TJ = 25C, L = 0.5 mH, IAS = 40A. 2: Pulse Width = 100s (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 2 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Package Marking and Ordering Information 1.2 125 100 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER VGS = 10V 1.0 0.8 0.6 0.4 75 50 25 0.2 0 0 25 50 75 100 150 125 0 175 25 TC , CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature 2.0 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZJC, NORMALIZED THERMAL IMPEDANCE 1.0 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JC x RJC + TC SINGLE PULSE 0.01 10 -5 10-4 10 -3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1000 IDM, PEAK CURRENT (A) TC = 25 oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 10V 100 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 3 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 200 1000 10s STARTING TJ = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100s 100 OPERATION N IN HIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.001 300 0.01 0.1 tAV, TIME IN AVALANCHE (ms) 1 NOTE: Refer to Fairchild Application Notes AN7515 and AN7517 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 180 180 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 120 TJ = 175oC 90 60 VGS = 7V VGS = 10V 150 ID, DRAIN CURRENT (A) 150 ID , DRAIN CURRENT (A) STARTING TJ = 150oC TJ = 25oC TJ = -55oC VGS = 6V 120 90 TC = 25oC 60 VGS = 5V 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 30 0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VGS , GATE TO SOURCE VOLTAGE (V) 0.0 6.5 Figure 7. Transfer Characteristics 6.0 Figure 8. Saturation Characteristics 18 3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (m ) 1.0 2.0 3.0 4.0 5.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 17 VGS = 6V 16 15 VGS = 10V 14 13 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.5 2.0 1.5 1.0 VGS = 10V, ID =33A 0.5 0 20 40 60 ID, DRAIN CURRENT (A) 80 -80 Figure 9. Drain to Source On Resistance vs Drain Current (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature 4 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 1.4 1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 1.1 1.0 0.9 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 -80 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 10000 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 75V C, CAPACITANCE (pF) CISS = CGS + CGD COSS CDS + CGD 1000 CRSS = CGD 100 VGS = 0V, f = 1MHz 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 33A ID = 16A 2 0 50 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 150 40 60 80 100 Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Voltage (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 20 Figure 14. Gate Charge Waveforms for Constant Gate Currents 5 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted VDS BVDSS tP L VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS + - VGS VGS = 10V Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS 90% - VDD 10% 0 10% DUT 90% VGS VGS 0 Figure 19. Switching Time Test Circuit (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 90% + VGS RGS tf 50% 10% PULSE WIDTH 50% Figure 20. Switching Time Waveforms 6 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Test Circuits and Waveforms The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) (T -T ) JM A P D M = ----------------------------R JA 80 40 (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm2 ) (64.5) Figure 21. Thermal Resistance vs Mounting Pad Area 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA 19.84 ( 0.262 + Area ) (EQ. 2) = 26.51 + ------------------------------------- Area in Inches Squared R JA 128 ( 1.69 + Area ) (EQ. 3) = 26.51 + ---------------------------------- Area in Centimeters Squared (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 7 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Thermal Resistance vs. Mounting Pad Area rev April 2002 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 RSLC2 5 51 Ebreak 11 7 17 18 159 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 EVTHRES + 19 8 + LGATE GATE 1 Lgate 1 9 9.56e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 7.71e-9 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK ESLC - It 8 17 1 DRAIN 2 5 + .SUBCKT FDB2532 2 1 3 ; CA 12 8 1.4e-9 CB 15 14 1.6e-9 CIN 6 8 5.61e-9 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 7 RSOURCE RLgate 1 9 95.6 RLdrain 2 5 10 RLsource 3 7 77.1 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 14 13 S1B CA 17 18 RVTEMP CB 6 8 EGS 5 8 EDS - 19 VBAT + IT 14 + + Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 9.6e-3 Rgate 9 20 1.01 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 3.0e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD RLSOURCE RBREAK 15 S2B 13 SOURCE 3 - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*190),3))} .MODEL DbodyMOD D (IS=6.0E-11 N=1.09 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6 + CJO=3.9e-9 M=0.65 TT=4.8e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.0e-9 IS=1.0e-30 N=10 M=0.6) .MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.01) .MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-9.0e-7) .MODEL RdrainMOD RES (TC1=9.0e-3 TC2=3.5e-5) .MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6) .MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-4.0e-3 TC2=3.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-4.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-6.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.4 VOFF=1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.0 VOFF=-1.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 8 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET PSPICE Electrical Model REV April 2002 ttemplate FDB2532 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=6.0e-11,nl=1.09,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=3.9e-9,m=0.65,tt=4.8e-8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.0e-9,isl=10.0e-30,nl=10,m=0.6) m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-4.0) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-4.0,voff=-6.0) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.4,voff=1.0) 10 RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.4) RSLC1 51 c.ca n12 n8 = 1.4e-9 RSLC2 c.cb n15 n14 = 1.6e-9 ISCL c.cin n6 n8 = 5.61e-9 spe.ebreak n11 n7 n17 n18 = 159 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN DRAIN 2 8 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE i.it n8 n17 = 1 S1A 12 l.lgate n1 n9 = 9.56e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 7.71e-9 S2A 13 8 14 13 S1B CA res.rlgate n1 n9 = 95.6 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 77.1 RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS - 19 IT 14 + + VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-9.0e-7 res.rdrain n50 n16 = 9.6e-3, tc1=9.0e-3,tc2=3.5e-5 res.rgate n9 n20 = 1.01 res.rslc1 n5 n51 = 1.0e-6, tc1=3.4e-3,tc2=1.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 3.0e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=3.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/190))** 3)) } } (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 9 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET SABER Electrical Model th JUNCTION REV 26 February 2002 FDB2532 CTHERM1 TH 6 7.5e-3 CTHERM2 6 5 8.0e-3 CTHERM3 5 4 9.0e-3 CTHERM4 4 3 2.4e-2 CTHERM5 3 2 3.4e-2 CTHERM6 2 TL 6.5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.1e-4 RTHERM2 6 5 2.5e-3 RTHERM3 5 4 2.0e-2 RTHERM4 4 3 8.0e-2 RTHERM5 3 2 1.2e-1 RTHERM6 2 TL 1.3e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB2532 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =2.4e-2 ctherm.ctherm5 3 2 =3.4e-2 ctherm.ctherm6 2 tl =6.5e-2 RTHERM3 CTHERM3 4 RTHERM4 rrtherm.rtherm1 th 6 =3.1e-4 rtherm.rtherm2 6 5 =2.5e-3 rtherm.rtherm3 5 4 =2.0e-2 rtherm.rtherm4 4 3 =8.0e-2 rtherm.rtherm5 3 2 =1.2e-1 rtherm.rtherm6 2 tl =1.3e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 10 CASE www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET SPICE Thermal Model FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Mechanical Dimensions TO-220 3L Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT220-003 Dimension in Millimeters (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 11 www.fairchildsemi.com FDP2532 / FDB2532 -- N-Channel PowerTrench(R) MOSFET Mechanical Dimensions TO-263 2L (D2PAK) Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002 Dimension in Millimeters (c)2002 Fairchild Semiconductor Corporation FDP2532 / FDB2532 Rev. C2 12 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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