DRBPACKAGE
3mmx3mmSON
(TOPVIEW)
8
7
6
5
OUT
N/C
NR/FB
GND
IN
N/C
N/C
EN
1
2
3
4
GND
DRVPACKAGE
2mmx2mmSON
IN
N/C
EN
6
5
4
OUT
NR/FB
GND
1
2
3
GND
(TOPVIEW)
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
500mA, Low Quiescent Current, Ultra-Low Noise, High PSRR
Low-Dropout Linear Regulator
Check for Samples: TPS735xx
1FEATURES APPLICATIONS
2• 500mA Low Dropout Regulator with EN • WiFi, WiMax
• Low IQ: 46μA • Printers
• Multiple Output Voltage Versions Available: • Cellular Phones, SmartPhones
– Fixed Outputs of 1.0V to 4.3V Using • Handheld Organizers, PDAs
Innovative Factory EEPROM Programming DESCRIPTION
– Adjustable Outputs from 1.25V to 6.0V The TPS735xx family of low-dropout (LDO), low-
• High PSRR: 60dB at 1kHz power linear regulators offers excellent ac
• Ultra-low Noise: 28μVRMS performance with very low ground current. High
• Fast Start-Up Time: 45μspower-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
• Stable with a Low-ESR, 2.0μF Typical Output response are provided while consuming a very low
Capacitance 46μA (typical) ground current. The TPS735xx is
• Excellent Load/Line Transient Response stable with ceramic capacitors and uses an advanced
• 2% Overall Accuracy (Load/Line/Temp, BiCMOS fabrication process to yield a typical dropout
voltage of 250mV at 500mA output. The TPS735xx
VOUT > 2.2V) uses a precision voltage reference and feedback loop
• Very Low Dropout: 280mV at 500mA to achieve overall accuracy of 2% (VOUT > 2.2V) over
• 2mm × 2mm SON-6 and 3mm × 3mm SON-8 all load, line, process, and temperature variations. It
Packages is fully specified from TJ= –40°C to +125°C and is
offered in low-profile, 2mm x 2mm SON and 3mm ×
3mm SON packages that are ideal for wireless
handsets, printers, and WLAN cards.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS735xx yyy z XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range (unless otherwise noted).(1)
PARAMETER TPS735xx UNIT
VIN range –0.3 to +7.0 V
VEN range –0.3 to VIN +0.3 V
VOUT range –0.3 to VIN +0.3 V
VFB range –0.3 to VFB (TYP) +0.3 V
Peak output current Internally limited
Continuous total power dissipation See Thermal Information table
Junction temperature range, TJ–55 to +150 °C
Storage temperature range , TSTG –55 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
THERMAL INFORMATION TPS735xx(2)
THERMAL METRIC(1) DRB DRV(3) UNITS
8 PINS 6 PINS
θJA Junction-to-ambient thermal resistance(4) 47.8 50.2
θJCtop Junction-to-case (top) thermal resistance(5) 83 59
θJB Junction-to-board thermal resistance(6) N/A N/A °C/W
ψJT Junction-to-top characterization parameter(7) 2.1 0.1
ψJB Junction-to-board characterization parameter(8) 17.8 30.1
θJCbot Junction-to-case (bottom) thermal resistance(9) 12.1 8.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.ii. DRV: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. Due to size limitation of thermal
pad, 0.8-mm pitch array is used which is off the JEDEC standard.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.ii DRV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(3) Power dissipation may limit operating range.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN, COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73501, VOUT = 3.0V.
Typical values are at TJ= +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) 2.7 6.5 V
VFB Internal reference (TPS73501) 1.184 1.208 1.232 V
VOUT Output voltage range (TPS73501) VFB 6.0 V
VOUT Output accuracy Nominal TJ= +25°C –1.0 +1.0 %
VOUT + 0.3V ≤VIN ≤VOUT > 6.5V
DRB –2.0 ±1.0 +2.0 %
1mA ≤IOUT ≤500mA, VOUT > 2.2V
package
over VIN,VOUT + 0.3V ≤VIN ≤6.5V –3.0 ±1.0 +3.0 %
IOUT, Temp 1mA ≤IOUT ≤500mA, VOUT ≤2.2V
VOUT + 0.3V ≤VIN ≤VOUT + 3.0V,
VOUT Output accuracy(1) VIN ≤6.5V –2.0 ±1.0 +2.0 %
DRV 1mA ≤IOUT ≤500mA, VOUT > 2.2V
package
over VIN,VOUT + 0.3V ≤VIN ≤VOUT + 3.0V,
IOUT, Temp VIN ≤6.5V –3.0 ±1.0 +3.0 %
1mA ≤IOUT ≤500mA, VOUT ≤2.2V
ΔVOUT%/ ΔVIN Line regulation(1) VOUT(NOM) + 0.3V ≤VIN ≤6.5V 0.02 %/V
ΔVOUT%/ ΔIOUT Load regulation 500μA≤IOUT ≤500mA 0.005 %/mA
Dropout voltage(2)
VDO IOUT = 500mA 280 500 mV
(VIN = VOUT(NOM) – 0.1V) VOUT = 0.9 × VOUT(NOM)
ICL Output current limit VIN = VOUT(NOM) + 0.9V, 800 1170 1720 mA
VIN ≥2.7V
IGND Ground pin current 500μA≤IOUT ≤500mA 45 65 μA
ISHDN Shutdown current (IGND) VEN ≤0.4V 0.15 1.0 μA
IFB Feedback pin current (TPS73501) –0.5 0.5 μA
f = 100Hz 60 dB
Power-supply rejection ratio f = 1kHz 56 dB
PSRR VIN = 3.85V, VOUT = 2.85V, f = 10kHz 41 dB
CNR = 0.01μF, IOUT = 100mA f = 100kHz 28 dB
CNR = 0.01μF 11 x VOUT μVRMS
Output noise voltage
VNBW = 10Hz to 100kHz, VOUT = 2.8V CNR = none 95 x VOUT μVRMS
CNR = none 45 μs
Startup time, VOUT= 0% to CNR = 0.001μF 45 μs
90%
TSTR VOUT = 2.85V, CNR = 0.01μF 50 μs
RL= 14Ω, COUT = 2.2μFCNR = 0.047μF 50 μs
VEN(HI) Enable high (enabled) 1.2 VIN V
VEN(LO) Enable low (shutdown) 0 0.4 V
IEN(HI) Enable pin current, enabled VEN = VIN = 6.5V 0.03 1.0 μA
Shutdown, temperature increasing 165 °C
TSD Thermal shutdown temperature Reset, temperature decreasing 145 °C
TJOperating junction temperature –40 +125 °C
Under-voltage lock-out VIN rising 1.90 2.20 2.65 V
UVLO Hysteresis VIN falling 70 mV
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
(2) VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V.
4Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
IN
N/C
EN
6
5
4
OUT
NR/FB
GND
1
2
3
GND
8
7
6
5
OUT
N/C
NR/FB
GND
IN
N/C
N/C
EN
1
2
3
4
GND
8
7
6
5
OUT
N/C
NR/FB
GND
IN
N/C
N/C
EN
1
2
3
4
GND
Thermal
Shutdown
UVLO
Current
Limit
2 Am
Overshoot
Detect
500kW
Quickstart
1.208V
Bandgap(1)
IN
EN
NR
OUT
GND
400W
NOTE(1): Fixedvoltageversionsbetween1.0Vto1.2Vhavea1.0Vbandgapcircuit
insteadofa1.208Vbandgapcircuit.
Thermal
Shutdown
UVLO
Current
Limit
3.3MW
Overshoot
Detect
500kW
1.208V
Bandgap
IN
EN
FB
OUT
GND
400W
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Fixed Voltage Versions Figure 2. Adjustable Voltage Versions
PIN CONFIGURATIONS
DRB PACKAGE
3mm × 3mm SON-6
(TOP VIEW)
DRB PACKAGE DRV PACKAGE
3mm × 3mm SON-6 2mm × 2mm SON-6
(TOP VIEW) (TOP VIEW)
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
PIN DESCRIPTIONS
TPS735xx
NAME DRV DRB DESCRIPTION
IN 6 8 Input supply.
GND 3, Pad 4 Ground. The pad must be tied to GND.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
EN 4 5 shutdown mode. EN can be connected to IN if not used.
Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise
NR 2 3 generated by the internal bandgap. This allows output noise to be reduced to very low levels.
Adjustable version only; this is the input to the control loop error amplifier, and is used to set the
FB 2 3 output voltage of the device.
Output of the regulator. A small capacitor (total typical capacitance ≥2.0μF ceramic) is needed
OUT 1 1 from this pin to ground to assure stability.
N/C 5 2, 6, 7 Not internally connected. This pin must either be left open, or tied to GND.
6Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
60
50
40
30
20
10
0
I ( A)m
GND
0 50 100 150 200 250 300 350 400 450 500
I (mA)
OUT
TJ= 40 C-°
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
500
450
400
350
300
250
200
150
100
50
0
I (na)
GND
-40 -25 -10 5 20 35 50 65 80 95 110 125
T ( )
JC
°
VIN =6.5V
VEN =0.4V
VIN =5.0V
VIN =3.3V
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
V (V)
OUT
0 50 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C-°
TJ=+125 C°
TJ=+85 C°
Y-axisrangeis 2%of2.8V±
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
V (V)
OUT
0 50 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C-°
TJ=+125 C°TJ=+85 C°
TJ=0 C°
TJ=+25 C°
Y-axisrangeis 2%of2.5V±
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV (%)
OUT
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V (V)
IN
TJ= 40 C-°
TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I =100mA
OUT
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV (%)
OUT
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V (V)
IN
TJ= 40 C-°TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I =100mA
OUT
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73501, VOUT = 2.8V. The TPS73525 is used as the
evaluation target of the fixed-voltage option in this datasheet. However, this voltage option may not be released. Check the
Package Option Addendum at the end of this document for the availability of the 2.5V version.Typical values are at TJ=
+25°C.
TPS73501 LINE REGULATION TPS73525 LINE REGULATION
Figure 3. Figure 4.
TPS73501 LOAD REGULATION TPS73525 LOAD REGULATION
Figure 5. Figure 6.
TPS73525 GROUND PIN CURRENT vs TPS73525 GROUND PIN CURRENT (DISABLE) vs
OUTPUT CURRENT TEMPERATURE
Figure 7. Figure 8.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
30
25
20
15
10
5
0
TotalNoise( V )mRMS
0510 15 20 25
C ( F)m
OUT
I =1mA
C =0.01 F
OUT
NR m
10 100 1k 10k 100k 1M 10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =2.2 F
OUT m
C =0.01 F
NR m
I =200mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =250mA
OUT
I =1mA
OUT
10 100 1k 10k 100k 1M 10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =10 F
OUT m
C =0.01 F
NR m
I =200mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =
200mA
OUT
I =1mA
OUT
400
350
300
250
200
150
100
50
0
V (mV)
DO
0 50 100 150 200 250 300 350 400 450 500
I (mA)
OUT
TJ= 40 C-°
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
10 100 1k 10k 100k 1M 10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =2.2 F
OUT m
C =0.01 F
NR m
I =250mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =200mA
OUT
I =1mA
OUT
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73501, VOUT = 2.8V. The TPS73525 is used as the
evaluation target of the fixed-voltage option in this datasheet. However, this voltage option may not be released. Check the
Package Option Addendum at the end of this document for the availability of the 2.5V version.Typical values are at TJ=
+25°C. TPS73501 DROPOUT VOLTAGE vs POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
OUTPUT CURRENT (VIN – VOUT = 1.0V)
Figure 9. Figure 10.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 0.5V) (VIN – VOUT = 0.3V)
Figure 11. Figure 12.
TPS73525 TPS73525
TOTAL NOISE vs CNR TOTAL NOISE vs COUT
Figure 13. Figure 14.
8Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
10 s/divm
50mV/div
50mV/div
50mV/div
0.5V/div
VOUT
VOUT
VOUT
VOUT
VIN
C =470 FOSCON
OUT m
C =10 F
OUT m
C =2.2 F
OUT m
4V
3V
10 s/divm
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
1.0-
Volts(V)
VIN =EN
VOUT
R =5W
L
10 s/divm
200mV/div
200mV/div
200mV/div
500mA/div
VOUT
VOUT
IOUT
C =470 FOSCON
OUT m
C =10 F
OUT m
C =2.2 F
OUT m
V =3.0V
IN
500mA
1mA
10 s/divm
VOUT
VEN
C =10 F
OUT m
C =2.2 F
OUT m
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5-
Voltage(V)
10 s/divm
VEN
VOUT
C =2.2 F
OUT m
C =10 F
OUT m
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5-
Voltage(V)
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. For TPS73501, VOUT = 2.8V. The TPS73525 is used as the
evaluation target of the fixed-voltage option in this datasheet. However, this voltage option may not be released. Check the
Package Option Addendum at the end of this document for the availability of the 2.5V version.Typical values are at TJ=
+25°C. TPS73525
TURN-ON RESPONSE TPS73525
(VIN = VEN) EN RESPONSE OVER STABLE VIN
Figure 15. Figure 16.
TPS73525
POWER-UP/POWER-DOWN
(VIN = VEN) TPS73525 LOAD TRANSIENT RESPONSE
Figure 17. Figure 18.
TPS73525 LINE TRANSIENT RESPONSE
Figure 19.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
GNDEN FB
IN OUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
TPS73501
2.2 F
Ceramic
m
VIN
VEN
R1
R2
CFB
VOUT
(R +R )
1 2
R2
VOUT =´1.208
GNDEN NR
IN OUT
TPS735xx
Optionalbypasscapacitor
toreduceoutputnoise
andincreasePSRR.
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
VIN
VEN
2.2 F
Ceramic
m
VOUT
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
APPLICATION INFORMATION
Input and Output Capacitor Requirements
The TPS735xx family of LDO regulators combines
the high performance required of many RF and Although an input capacitor is not required for
precision analog applications with ultra-low current stability, it is good analog design practice to connect
consumption. High PSRR is provided by a high gain, a 0.1μF to 1μF low equivalent series resistance
high bandwidth error loop with good supply rejection (ESR) capacitor across the input supply near the
at very low headroom (VIN – VOUT). Fixed voltage regulator. The ground of this capacitor should be
versions provide a noise reduction pin to bypass connected as close as the ground of output capacitor;
noise generated by the bandgap reference and to a capacitor value of 0.1μF is enough in this condition.
improve PSRR while a quick-start circuit fast-charges When it is difficult to place these two ground points
this capacitor at startup. The combination of high close together, a 1μF capacitor is recommended.
performance and low ground current also make the This capacitor counteracts reactive input sources and
TPS735xx an excellent choice for portable improves transient response, noise rejection, and
applications. All versions have thermal and over- ripple rejection. A higher-value capacitor may be
current protection and are fully specified from –40°C necessary if large, fast rise-time load transients are
to +125°C. anticipated, or if the device is located several inches
from the power source. If source impedance is not
Figure 20 shows the basic circuit connections for sufficiently low, a 0.1μF input capacitor may be
fixed voltage models. Figure 21 gives the connections necessary to ensure stability.
for the adjustable output version (TPS73501). R1and
R2can be calculated for any output voltage using the The TPS735xx is designed to be stable with standard
formula in Figure 21. ceramic output capacitors of values 2.2μF or larger.
X5R and X7R type capacitors are best because they
have minimal variation in value and ESR over
temperature. Maximum ESR of the output capacitor
should be < 1.0Ω, so output capacitor type should be
either ceramic or conductive polymer electrolytic.
Feedback Capacitor Requirements
(TPS73501 only)
The feedback capacitor, CFB, shown in Figure 21 is
required for stability. For a parallel combination of R1
and R2equal to 250kΩ, any value from 3pF to 1nF
can be used. Fixed voltage versions have an internal
30pF feedback capacitor that is quick-charged at
Figure 20. Typical Application Circuit for start-up. The adjustable version does not have this
Fixed Voltage Versions quick-charge circuit, so values below 5pF should be
used to ensure fast startup; values above 47pF can
be used to implement an output voltage soft-start.
Larger value capacitors also improve noise slightly.
The TPS73501 is stable in unity-gain configuration
(OUT tied to FB) without CFB.
Output Noise
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS735xx, the bandgap does not contribute
significantly to noise. Instead, noise is dominated by
the output resistor divider and the error amplifier
Figure 21. Typical Application Circuit for input. To minimize noise in a given application, use a
Adjustable Voltage Versions 0.01μF noise reduction capacitor; for the adjustable
version, smaller value resistors in the output resistor
divider reduce noise. A parallel combination that
space gives 2μA of divider current has the same noise
space performance as a fixed voltage version. To further
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
V =xV
N OUT
11
V
mVRMS
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transient
output capacitor can be set to approximately 0.2Ω. response are degraded as (VIN – VOUT) approaches
This configuration maximizes phase margin in the dropout. This effect is shown in the Typical
control loop, reducing total output noise by up to Characteristics section.
10%. Startup and Noise Reduction Capacitor
Noise can be referred to the feedback point (FB pin)
such that with CNR = 0.01μF, total noise is given Fixed voltage versions of the TPS735xx use a quick-
approximately by Equation 1:start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see the Functional Block
Diagrams). This architecture allows the combination
(1) of very low output noise and fast start-up times. The
The TPS73501 adjustable version does not have the NR pin is high impedance so a low leakage CNR
noise-reduction pin available, so ultra-low noise capacitor must be used; most ceramic capacitors are
operation is not possible. Noise can be minimized appropriate in this configuration. A high-quality, COG-
according to the above recommendations. type (NPO) dielectric ceramic capacitor is
recommended for CNR when used in environments
Board Layout Recommendations to Improve where abrupt changes in temperature can occur.
PSRR and Noise Performance Note that for fastest startup, VIN should be applied
To improve ac performance such as PSRR, output first, then the enable pin (EN) driven high. If EN is
noise, and transient response, it is recommended that tied to IN, startup is somewhat slower. Refer to the
the board be designed with separate ground planes Typical Characteristics section. The quick-start switch
for VIN and VOUT, with each ground plane connected is closed for approximately 135μs. To ensure that
only at the GND pin of the device. In addition, the CNR is fully charged during the quick-start time, a
ground connection for the bypass capacitor should 0.01μF or smaller capacitor should be used.
connect directly to the GND pin of the device. Transient Response
Internal Current Limit As with any regulator, increasing the size of the
The TPS735xx internal current limit helps protect the output capacitor reduces over/undershoot magnitude
regulator during fault conditions. During current limit, but increases duration of the transient response. In
the output sources a fixed amount of current that is the adjustable version, adding CFB between OUT and
largely independent of output voltage. For reliable FB improves stability and transient response. The
operation, the device should not be operated in transient response of the TPS735xx is enhanced by
current limit for extended periods of time. an active pull-down that engages when the output
overshoots by approximately 5% or more when the
The PMOS pass element in the TPS735xx has a device is enabled. When enabled, the pull-down
built-in body diode that conducts current when the device behaves like a 400Ωresistor to ground.
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage Undervoltage Lock-Out (UVLO)
operation is anticipated, external limiting may be
appropriate. The TPS735xx utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
Shutdown circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
The enable pin (EN) is active high and is compatible undershoot transients on the input if they are less
with standard and low voltage TTL-CMOS levels. than 50μs duration.
When shutdown capability is not required, EN can be
connected to IN. Minimum Load
Dropout Voltage The TPS735xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
The TPS735xx uses a PMOS pass transistor to minimum load of 500μA is required. Below 500μA at
achieve low dropout. When (VIN – VOUT) is less than junction temperatures near +125°C, the output can
the dropout voltage (VDO), the PMOS pass device is drift up enough to cause the output pull-down to turn
in its linear region of operation and the input-to-output on. The output pull-down limits voltage drift to 5%
resistance is the RDS, ON of the PMOS pass element. typically but ground current could increase by
Because the PMOS device behaves like a resistor in
dropout, VDO approximately scales with output
current.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
160
140
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
Board Copper Area ( )in2
DRV
DRB
RqJA +()125OC*TA)
PD
PD+ǒVIN*VOUTǓ@IOUT
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
approximately 50μA. In typical applications, the Power dissipation depends on input voltage and load
junction cannot reach high temperatures at light loads conditions. Power dissipation is equal to the product
because there is no appreciable dissipated power. of the output current time the voltage drop across the
The specified ground current would then be valid at output pass element, as shown in Equation 2:
no load in most applications. (2)
Thermal Information Note: When the device is used in a condition of
higher input and lower output voltages with the DRV
and DRB packages, PDexceeds the package rating
Thermal Protection at room temperature. This equation shows an
example of the DRB package:
Thermal protection disables the output when the
junction temperature rises to approximately +165°C, PD= (6.5V – 1.0V) × 500mA = 2.75W, which is
allowing the device to cool. When the junction greater than 2.5W at +25°C.
temperature cools to approximately +145°C the Power dissipation can be minimized and greater
output circuitry is again enabled. Depending on power efficiency can be achieved by using the lowest
dissipation, thermal resistance, and ambient possible input voltage necessary to achieve the
temperature, the thermal protection circuit may cycle required output voltage regulation.
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of On both SON (DRB) and SON (DRV) packages, the
overheating. primary conduction path for heat is through the
exposed pad to the printed circuit board (PCB). The
Any tendency to activate the thermal protection circuit pad can be connected to ground or be left floating;
indicates excessive power dissipation or an however, it should be attached to an appropriate
inadequate heatsink. For reliable operation, junction amount of copper PCB area to ensure the device
temperature should be limited to +125°C maximum. does not overheat. The maximum junction-to-ambient
To estimate the margin of safety in a complete design thermal resistance depends on the maximum ambient
(including heatsink), increase the ambient temperature, maximum device junction temperature,
temperature until the thermal protection is triggered; and power dissipation of the device and can be
use worst-case loads and signal conditions. For good calculated using Equation 3:
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This (3)
configuration produces a worst-case junction Knowing the maximum RθJA, the minimum amount of
temperature of +125°C at the highest expected PCB copper area needed for appropriate heatsinking
ambient temperature and worst-case load. can be estimated using Figure 22.
The internal protection circuitry of the TPS735xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS735xx into thermal
shutdown degrades device reliability.
Package Mounting
Solder pad footprint recommendations for the
TPS735xx are available from the Texas Instruments
web site at www.ti.com.
Power Dissipation
The ability to remove heat from the die is different for
each package type, presenting different
considerations in the PCB layout. The PCB area
around the device that is free of other components Note: θJA value at board size of 9in2(that is, 3in ×
moves the heat from the device to the ambient air. 3in) is a JEDEC standard.
Performance data for JEDEC low- and high-K boards Figure 22. θJA vs Board Size
are given in the Thermal Information table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
(a) Example DRB (SON) Package Measurement (b) Example DRV (SON) Package Measurement
1mm
T on top
of IC
T
T on PCB
surface
B
T on top
of IC
T
T on PCB
surface
B
1mm
See note (1)
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
35
30
25
20
15
10
5
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
Board Copper Area (in )
2
51 3 7 9
DRV
DRB
YJT
DRV
DRB
YJB
TPS735xx
www.ti.com
SBVS087K –JUNE 2008–REVISED AUGUST 2013
Figure 22 illustrates the variation of θJA as a function By looking at Figure 23, the new thermal metrics (ΨJT
of ground plane copper area in the board. It is and ΨJB) have very little dependency on board size.
intended only as a guideline to demonstrate the That is, using ΨJT or ΨJB with Equation 4 is a good
effects of heat spreading in the ground plane and way to estimate TJby simply measuring TTor TB,
should not be used to estimate actual thermal regardless of the application board size.
performance in real application environments.
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
ESTIMATING JUNCTION TEMPERATURE
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 4). For backwards
compatibility, an older θJC,Top parameter is listed as
well.
(4) Figure 23. ΨJT and ΨJB vs Board Size
Where PDis the power dissipation shown by
Equation 2, TTis the temperature at the center-top of For a more detailed discussion of why TI does not
the IC package, and TBis the PCB temperature recommend using θJC(top) to determine thermal
measured 1mm away from the IC package on the characteristics, refer to application report SBVA025,
PCB surface (as Figure 24 shows). Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
NOTE: Both TTand TBcan be measured on actual application report SPRA953,IC Package Thermal
application boards using a thermo-gun (an infrared Metrics, also available on the TI website.
thermometer).
For more information about measuring TTand TB, see
the application note SBVA025,Using New Thermal
Metrics, available for download at www.ti.com.
(1) Power dissipation may limit operating range. Check Thermal Information table.
Figure 24. Measuring Points for TTand TB
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
TPS735xx
SBVS087K –JUNE 2008–REVISED AUGUST 2013
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (May 2011) to Revision K Page
• Added last sentence to first paragraph of Startup and Noise Reduction Capacitor section ............................................... 11
Changes from Revision I (April, 2011) to Revision J Page
• Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3
• Revised conditions for Typical Characteristics to include statement about TPS73525 device availability .......................... 7
• Updated Power Dissipation section .................................................................................................................................... 12
• Added Estimating Junction Temperature section ............................................................................................................... 13
Changes from Revision H (November, 2009) to Revision I Page
• Corrected typo in Electrical Characteristics table for VOUT specification, DRV package test conditions, VOUT ≤2.2V ......... 4
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS73501DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CBK
TPS73501DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CBK
TPS73501DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR
TPS73501DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDR
TPS73512DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT
TPS73512DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTT
TPS73515DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 QWH
TPS73515DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 QWH
TPS73525DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CBM
TPS73525DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM
TPS73525DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CBM
TPS73525DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CBM
TPS73525DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW
TPS73525DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NSW
TPS73527DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) NIPDAU | CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK
TPS73527DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) NIPDAU | CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAK
TPS735285DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS735285DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RAW
TPS73533DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CVY
TPS73533DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU | Call TI Level-2-260C-1 YEAR -40 to 125 CVY
TPS73533DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVY
TPS73533DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 CVY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Nov-2013
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73501DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73501DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73501DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73501DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73512DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73512DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73515DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73515DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73525DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73527DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73527DRVR SON DRV 6 3000 180.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
TPS73527DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS735285DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS735285DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73533DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2013
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73533DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73533DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73533DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73501DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73501DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73501DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS73501DRVT SON DRV 6 250 203.0 203.0 35.0
TPS73512DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73512DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73515DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73515DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73525DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73525DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73525DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS73525DRVT SON DRV 6 250 203.0 203.0 35.0
TPS73527DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS73527DRVR SON DRV 6 3000 205.0 200.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2013
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73527DRVT SON DRV 6 250 203.0 203.0 35.0
TPS735285DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS735285DRVT SON DRV 6 250 203.0 203.0 35.0
TPS73533DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73533DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73533DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS73533DRVT SON DRV 6 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Nov-2013
Pack Materials-Page 3
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