TC6320 N- and P-Channel Enhancement-Mode MOSFET Pair Features General Description The Supertex TC6320 consists of high voltage, low threshold N-channel and P-channel MOSFETs in 8-Lead SOIC and DFN packages. Both MOSFETs have integrated gate-tosource resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. It is a complimentary, high-speed, high voltage, gate-clamped Nand P-channel MOSFET pair, which utilizes an advanced vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Integrated gate-to-source resistor Integrated gate-to-source Zener diode Low threshold Low on-resistance Low input capacitance Fast switching speeds Free from secondary breakdown Low input and output leakage Independent, electrically isolated N- and P-channels Applications High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interfaces Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Typical Application Circuit VDD +100V VH OE 10nF INA INB 10nF VSS -100V VL Supertex MD12xx, MD17xx, or MD18xx Supertex TC6320 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com TC6320 Ordering Information BVDSS/BVDGS Package Options Device 8-Lead DFN RDS(ON) (V) (max) () 8-Lead SOIC 4.0x4.0mm body 1.0mm height (max) 1.0mm pitch (dual pad) 4.9x3.9mm body 1.75mm height (max) 1.27mm pitch N-Channel P-Channel N-Channel P-Channel TC6320K6-G TC6320TG-G 200 -200 7.0 8.0 TC6320 -G indicates package is RoHS compliant (`Green') Pin Configurations SN 1 GN 2 Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Operating and storage temperature Soldering temperature* +300C Distance of 1.6mm from case for 10 seconds. Thermal Characteristics Package ja = 44 C/W 8-Lead SOIC (TG) ja = 130OC/W DP SP 4 8 DN 7 DN 6 DP 5 DP 8-Lead DFN (K6) (top view) SN 1 8 DN GN 2 7 DN SP 3 6 DP GP 4 5 DP Value 8-Lead DFN (K6) Note: 1.0oz, 4-layer, 3"x4" PCB GP 3 -55C to +150C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * DN 8-Lead SOIC (TG) (top view) O Package Marking Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = "Green" Packaging 6320 YWLL Package may or may not include the following marks: Si or 8-Lead DFN (K6) YYWW C6320 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging Package may or may not include the following marks: Si or 8-Lead SOIC (TG) 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 TC6320 N-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID = 1.0mA - - -4.5 mV/OC VGS = VDS, ID = 1.0mA VGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 10 - 50 K IGS = 100A VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA - - 10.0 A VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC 1.0 - - 2.0 - - - - 8.0 - - 7.0 - - 1.0 %/OC VGS = 4.5V, ID =150mA 400 - - mmho VDS = 25V, ID = 500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance RDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - - 110 COSS Common source output capacitance - - 60 CRSS Reverse transfer capacitance - - 23 td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD =25V, ID = 1.0A, RGEN = 25 1.8 V VGS = 0V, ISD = 500mA - ns VGS = 0V, ISD = 500mA Notes: 1. All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V RL 90% Input 0V Pulse Generator 10% t(ON) td(ON) VDD VDD t(OFF) tr 10% td(OFF) RGEN tf 10% OUTPUT D.U.T Input Output 0V 90% 90% 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 TC6320 P-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA - - 4.5 mV/OC VGS = VDS, ID = -1.0mA VGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 10 - 50 K IGS = 100A VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2mA - - -10 A VDS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC -1.0 - - -2.0 - - - - 10 - - 8.0 - - 1.0 %/OC VGS = -10V, ID =-200mA 400 - - mmho VDS = -25V, ID = -500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance RDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - - 200 COSS Common source output capacitance - - 55 CRSS Reverse transfer capacitance - - 30 td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -150mA VGS = -10V, ID = -1.0A pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -1.0A, RGEN = 25 -1.8 V VGS = 0V, ISD = -500mA - ns VGS = 0V, ISD = -500mA Notes: 1. All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit 0V Pulse Generator 10% Input -10V t(ON) td(ON) 0V Output VDD RGEN 90% D.U.T t(OFF) tr td(OFF) 90% 10% tf Input OUTPUT 90% 10% RL VDD 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 TC6320 8-Lead DFN Package Outline (K6) 4.00x4.00mm body, 0.90mm height (max), 1.00mm pitch (dual pad) K1 D 8 D2 K1/2 D2 8 E2 E E2 Note 1 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) 1 1 Top View Bottom View View B Note 3 A A3 e b A1 L Seating Plane L1 Note 2 View B Side View Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 A3 MIN 0.80 0.00 NOM 0.85 - MAX 0.90 0.05 0.20 REF b D D2 E E2 0.25 3.90 1.35 3.90 1.35 0.30 4.00 1.45 4.00 1.45 0.35 4.10 1.55 4.10 1.55 e 1.00 BSC K1 0.50 REF L L1 0.40 0.00 0O 0.50 - - 0.60 0.15 14O Drawings not to scale Supertex Doc. #: DSPD-8DFNK64x4P100, Version B101008 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 TC6320 8-Lead SOIC (Narrow Body) Package Outline (TG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch D 1 8 E E1 L2 Note 1 (Index Area D/2 x E1/2) L 1 L1 Top View Gauge Plane Seating Plane View B A View B Note 1 h h A A2 Seating Plane b e A1 A Side View View A-A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 L2 1.04 REF 0.25 BSC 1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version H101708. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com. (c)2008 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC6320 C122208 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6