● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
TC6320
Features
Integrated gate-to-source resistor
Integrated gate-to-source Zener diode
Low threshold
Low on-resistance
Low input capacitance
Fast switching speeds
Free from secondary breakdown
Low input and output leakage
Independent, electrically isolated N- and P-channels
Applications
High voltage pulsers
Amplifiers
Buffers
Piezoelectric transducer drivers
General purpose line drivers
Logic level interfaces
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N- and P-Channel
Enhancement-Mode MOSFET Pair
General Description
The Supertex TC6320 consists of high voltage, low threshold
N-channel and P-channel MOSFETs in 8-Lead SOIC and
DFN packages. Both MOSFETs have integrated gate-to-
source resistors and gate-to-source Zener diode clamps
which are desired for high voltage pulser applications. It is a
complimentary, high-speed, high voltage, gate-clamped N-
and P-channel MOSFET pair, which utilizes an advanced
vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of
bipolar transistors and with the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Typical Application Circuit
INA
INB
OE
-100V
+100V
Supertex
TC6320
10nF
10nF
VDD
VSS
VH
VL
Supertex
MD12xx, MD17xx, or MD18xx
2
TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
Device
Package Options BVDSS/BVDGS
(V)
RDS(ON)
(max) (Ω)
8-Lead DFN
4.0x4.0mm body
1.0mm height (max)
1.0mm pitch (dual pad)
8-Lead SOIC
4.9x3.9mm body
1.75mm height (max)
1.27mm pitch
N-Channel P-Channel N-Channel P-Channel
TC6320 TC6320K6-G TC6320TG-G 200 -200 7.0 8.0
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Pin Configurations
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
C6320
LLLL
8-Lead SOIC (TG)
(top view)
8-Lead SOIC (TG)
Package Marking
8-Lead DFN (K6)
(top view)
6320
YWLL
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead DFN (K6)
Thermal Characteristics
Package Value
8-Lead DFN (K6) θja = 44OC/W
8-Lead SOIC (TG) θja = 130OC/W
Note:
1.0oz, 4-layer, 3”x4” PCB
8
1
2
3
4
7
6
5
SN
GN
DN
GP
SP
DN
DP
DP
DN
DP
DP
DP
GN
SN
SP
DN
DN
GP
1
2
3
45
6
7
8
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
3
TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA
VGS(th) Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID = 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
RGS Gate-to-source shunt resistor 10 - 50 KΩ IGS = 100µA
VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA
IDSS Zero gate voltage drain current
- - 10.0 µA VDS = Max rating, VGS = 0V
- - 1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current 1.0 - - AVGS = 4.5V, VDS = 25V
2.0 - - VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance - - 8.0 ΩVGS = 4.5V, ID = 150mA
- - 7.0 VGS = 10V, ID = 1.0A
ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 4.5V, ID =150mA
GFS Forward transconductance 400 - - mmho VDS = 25V, ID = 500mA
CISS Input capacitance - - 110
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - - 60
CRSS Reverse transfer capacitance - - 23
td(ON) Turn-on delay time - - 10
ns
VDD =25V,
ID = 1.0A,
RGEN = 25Ω
trRise time - - 15
td(OFF) Turn-off delay time - - 20
tfFall time - - 15
VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA
Notes:
All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
1.
2.
N-Channel Switching Waveforms and Test Circuit
R
GEN
Input
Pulse
Generator
V
DD
R
L
D.U.T
OUTPUT
10V
0V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
10%
90%
90%
10%
90%
10%
4
TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA
VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
RGS Gate-to-source shunt resistor 10 - 50 KΩ IGS = 100µA
VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2mA
IDSS Zero gate voltage drain current
- - -10 µA VDS = Max rating, VGS = 0V
- - -1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current -1.0 - - AVGS = -4.5V, VDS = -25V
-2.0 - - VGS = -10V, VDS = -25V
RDS(ON) Static drain-to-source on-state resistance - - 10 ΩVGS = -4.5V, ID = -150mA
- - 8.0 VGS = -10V, ID = -1.0A
ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -10V, ID =-200mA
GFS Forward transconductance 400 - - mmho VDS = -25V, ID = -500mA
CISS Input capacitance - - 200
pF
VGS = 0V,
VDS = -25V,
f = 1.0MHz
COSS Common source output capacitance - - 55
CRSS Reverse transfer capacitance - - 30
td(ON) Turn-on delay time - - 10
ns
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
trRise time - - 15
td(OFF) Turn-off delay time - - 20
tfFall time - - 15
VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA
Notes:
All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
1.
2.
P-Channel Switching Waveforms and Test Circuit
R
GEN
Input
Pulse
Generator
V
DD
R
L
D.U.T
OUTPUT
0V
-10V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
90%
10%
90%
10%
10%
90%
5
TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
8-Lead DFN Package Outline (K6)
4.00x4.00mm body, 0.90mm height (max), 1.00mm pitch (dual pad)
Symbol A A1 A3 b D D2 E E2 e K1 L L1 θ
Dimension
(mm)
MIN 0.80 0.00
0.20
REF
0.25 3.90 1.35 3.90 1.35
1.00
BSC
0.50
REF
0.40 0.00 0O
NOM 0.85 - 0.30 4.00 1.45 4.00 1.45 0.50 - -
MAX 0.90 0.05 0.35 4.10 1.55 4.10 1.55 0.60 0.15 14O
Drawings not to scale
Supertex Doc. #: DSPD-8DFNK64x4P100, Version B101008
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
D2
e
b
E2
A3
L
L1
View B
View B
Note 1
(Index Area
D/2 x E/2)
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
1
1
88
Note 1
E2
D2
K1
θ
K1/2
Notes:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
The inner tip of the lead may be either rounded or square.
1.
2.
3.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
6
TC6320
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TC6320
C122208
8-Lead SOIC (Narrow Body) Package Outline (TG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
1.
