Data Sheet, V1.0, Apr. 2008
Microcontrollers
TC1762
32-Bit Single-Chip Microcontroller
TriCore
Edition 2008-04
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2008.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
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be endangered.
Data Sheet, V1.0, Apr. 2008
Microcontrollers
TC1762
32-Bit Single-Chip Microcontroller
TriCore
TC1762
Preliminary
Data Sheet V1.0, 2008-04
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
TC1762 Data Sheet
Revision History: V1.0, 2008-04
Previous Version: V0.5 2007-03
Page Subjects (major changes since last revision)
7VSSOSC3 is deleted from the TC1762 Logic Symbol.
8, 10 TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin
77 are updated in the Pinning Diagram and Pin Definition and Functions
Table.
33 Transmit DMA request in Block Diagram of ASC Interfaces is updated.
35 Alternate output functions in block diagram of SSC interfaces are updated.
41 Programmable baud rate of the MLI is updated.
42 TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated.
54 The description for WDT double reset detection is updated.
91 The power sequencing details is updated.
102 MLI timing, maximum operating frequency limit is extended, t31 is added.
106 Thermal resistance junction leads is updated.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
TC1762
Table of ContentsPreliminary
Data Sheet 1 V1.0, 2008-04
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4 Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1 System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . .24
3.2 On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.3 Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.4 Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5 DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.6 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.7 Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . . .33
3.8 High-Speed Synchronous Serial Interface (SSC0) . . . . . . . . . . . . . . . . . . .35
3.9 Micro Second Bus Interface (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.10 MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.11 Micro Link Serial Bus Interface (MLI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.12 General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.12.1 Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.13 Analog-to-Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.14 Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . . .49
3.15 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.16 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.17 System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.18 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.19 Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.20 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.21 Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.22 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.23 Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.1.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table of Contents
TC1762
Table of ContentsPreliminary
Data Sheet 2 V1.0, 2008-04
4.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.2.2 Analog to Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
4.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . .82
4.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
4.2.5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
4.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
4.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
4.3.2 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4.3.4 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
4.3.5 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
4.3.6 Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4.3.7 Timing for JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
4.3.8 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
4.3.8.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .102
4.3.8.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . .104
4.3.8.3 Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . .105
5 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
5.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
5.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
5.4 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
TC1762
Summary of FeaturesPreliminary
Data Sheet 3 V1.0, 2008-04
1 Summary of Features
The TC1762 has the following features:
• High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 66 or 80 MHz operation at full temperature range
• Multiple on-chip memories
– 32 Kbyte Local Data Memory (SRAM)
– 4 Kbyte Overlay Memory
– 8 Kbyte Scratch-Pad RAM (SPRAM)
– 8 Kbyte Instruction Cache (ICACHE)
– 1024 Kbyte Flash Memory
– 16 Kbyte Data Flash (2 Kbyte EEPROM emulation)
– 16 Kbyte Boot ROM
• 8-channel DMA Controller
• Fast-response interrupt system with 255 hardware priority arbitration levels serviced
by CPU
• High-performance on-chip bus structure
– 64-bit Local Memory Bus (LMB) to Flash memory
– System Peripheral Bus (SPB) for interconnections of functional units
• Versatile on-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate
generator, parity, framing and overrun error detection
– One High Speed Synchronous Serial Channel (SSC) with programmable data
length and shift direction
– One Micro Second Bus (MSC) interface for serial port expansion to external power
devices
– One high-speed Micro Link Interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with two CAN nodes and 64 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer
– One General Purpose Timer Array Module (GPTA) with a powerful set of digital
signal filtering and timer functionality to realize autonomous and complex
Input/Output management
– One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10-
bit, or 12-bit, supporting 32 input channels
– One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated
comb filters for hardware data reduction: supporting 10-bit resolution, with
minimum conversion time of 262.5ns (@ 80 MHz) or 318.2ns (@ 66 MHz)
TC1762
Summary of FeaturesPreliminary
Data Sheet 4 V1.0, 2008-04
• 32 analog input lines for ADC and FADC
• 81 digital general purpose I/O lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 and 2 (CPU, DMA)
• Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration
via USB V1.1 interface available (TC1766ED)
• Power Management System
• Clock Generation Unit with PLL
• Core supply voltage of 1.5 V
• I/O voltage of 3.3 V
• Full automotive temperature range: -40° to +125°C
• PG-LQFP-176-2 package
TC1762
Summary of FeaturesPreliminary
Data Sheet 5 V1.0, 2008-04
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
• The package and the type of delivery
For the available ordering codes for the TC1762, please refer to the “Product Catalog
Microcontrollers” that summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1-1 enumerates these
derivatives and summarizes the differences.
Table 1-1 TC1762 Derivative Synopsis
Derivative Ambient Temperature Range
SAK-TC1762-128F66HL TA = -40oC to +125oC; 66 MHz operation frequency
SAK-TC1762-128F80HL TA = -40oC to +125oC; 80 MHz operation frequency
TC1762
General Device InformationPreliminary
Data Sheet 6 V1.0, 2008-04
2 General Device Information
Chapter 2 provides the general information for the TC1762.
2.1 Block Diagram
Figure 2-1 shows the TC1762 block diagram.
Figure 2-1 TC1762 Block Diagram
DMA
8 c h.
BI0
f
FPI
f
CPU
Syst em Peripheral Bus (SPB)
Ports
SBCU
MCB06056
M ulti CA N
( 2 Nodes ,
64 Buffer)
STM
Ext.
Request
Unit
LBCU
LFI B r idge
OCDS Debug
Interface/JTAG
Abbreviations:
ICA CHE : Ins tr uc tion Cac he
SPRAM: Scrat ch-Pad RAM
LDRA M : Loc al Data RA M
OV RA M : O v er lay RA M
BRO M: Boot RO M
P Flas h: P r ogr am Flas h
DFlas h: Dat a Flas h
LM B: Local Memory Bus
SPB: Syst em Peripheral Bus
MLI0
TriCore
(TC1.3M)
PMI
8 KB SPRAM
8 KB ICACHE
DMI
32 K B LDRA M
CPS
16 KB BRO M
1024 K B P flas h
16 KB DF lash
PMU
GPTA
FPU
ASC1
ASC0
Mem
Check
4 K B OV RA M
Overlay
Mechanism
FADC
2 c h.
ADC0
32 c h.
A nalog In put
Assignment
SSC0
DM A B us
PLL SCU PLL
Loc al M em or y B us (LM B )
BI1
SMIF
MSC0
TC1762
General Device InformationPreliminary
Data Sheet 7 V1.0, 2008-04
2.2 Logic Symbol
Figure 2-2 shows the TC1762 logic symbol.
Figure 2-2 TC1762 Logic Symbol
8
7
9
FCLN0
FCLP0A
TESTMODE
BYPASS
NMI
HDRST
PORST
V
SS
MS C0 Co n tr o l
Digital Circuitry
Pow er Supply
General C ont rol
SOP0A
SON0
V
DD
V
DDP
AN[35:0]
AD C Analog I nput s V
DDM
V
SSM
V
DDMF
V
SSMF
V
DDAF
V
SSAF
V
AREF0
V
AGND0
V
FAREF
V
FAGND
V
DDFL3
AD C /F ADC Analog
Pow er Supply
MCB06066
Port 0 16-bit
V
DDOSC3
Alt ernat e F unc t ions
BRKOUT
XTAL1
XTAL2
Oscillator
TDI
TCK
TRST
Port 1 15-bit
Port 2 14-bit
Port 3 16-bit
Port 4 4-bit
GPTA, SCU
GPTA, ADC
S S C0 , ML I0 , G P TA, MS C0
ASC0/ 1, SSC0, SCU , CAN
TDO O CDS / JTA G Co n tr o l
GPTA, SCU
TMS
BRKIN
TRCLK
V
DDOSC
V
SSOSC
Port 5 16-bit G P TA , O CDS L 2 , MLI0
TC1762
TC1762
General Device InformationPreliminary
Data Sheet 8 V1.0, 2008-04
2.3 Pin Configuration
Figure 2-3 shows the TC1762 pin configuration.
Figure 2-3 TC1762 Pinning for PG-LQFP-176-2 Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
39
40
41
42
43
44
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
30
31
32
33
34
35
36
37
38
45
46
47
48
49
50
51
52
53
97
96
95
94
93
92
91
90
89
100
99
98
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
P0.0/IN0/SWCFG0/OUT0/OUT56
P0.1/IN1/SWCFG1/OUT1/OUT57
P0.2/IN2/SWCFG2/OUT2/OUT58
P0.3/IN3/SWCFG3/OUT3/OUT59
P0.4/IN4/SWCFG4/OUT4/OUT60
P0.5/IN5/SWCFG5/OUT5/OUT61
P0.6/IN6/SWCFG6/REQ2/OUT6/OUT62
P0.7/IN7/SWCFG7/REQ3/OUT7/OUT63
P0.8/IN8/SWCFG8/OUT8/OUT64
P0.9/IN9/SWCFG9/OUT9/OUT65
P0.10/IN10/SWCFG10/OUT10/OUT66
P0.11/IN11/SWCFG11/OUT11/OUT67
P0.12/IN12/SWCFG12/OUT12/OUT68
P0.13/IN13/SWCFG13/OUT13/OUT69
P0.14/IN14/SWCFG14/REQ4/OUT14/OUT70
P0.15/IN15/SWCFG15/REQ5/OUT15/OUT71
P1.0/IN16/OUT16/OUT72
P1.1/IN17/OUT17/OUT73
P1.2/IN18/OUT18/OUT74
P1.3/IN19/OUT19/OUT75
P1.4/IN20/EMG_IN/OUT20/OUT76
P1.5/IN21/OUT21/OUT77
P1.6/IN22/OUT22/OUT78
P1.7/IN23/OUT23/OUT79
P1.8/IN24/IN48/OUT24/OUT48
P1.9/IN25/IN49/OUT25/OUT49
P1.10/IN26/IN50/OUT26/OUT50
P1.11/IN27/IN51/OUT27/OUT51
AD0EMUX0/P1.12
AD0EMUX1/P1.13
AD0EMUX2/P1.14
TCLK0/OUT32/IN32/P2.0
SLSO03/OUT33/TREADY0A/IN33/P2.1
TVALID0A/OUT34/IN34/P2.2
TDATA0/OUT35/IN35/P2.3
OUT36/RCLK0A/IN36/P2.4
RREADY0A/OUT37/IN37/P2.5
OUT38/RVALID0A/IN38/P2.6
OUT39/RDATA0A/IN39/P2.7
P2.8/SLSO04/EN00
P2.9/SLSO05/EN01
P2.10/GPIO
P2.11/FCLP0B
P2.12/SOP0B
P2.13/SDI0
P3.0/RXD0A
P3.1/TXD0A
P3.2/SCLK0
P3.3/MRST0
P3.4/MTSR0
P3.5/SLSO00/SLSO00
P3.6/SLSO01/SLSO01
P3.7/SLSI0/SLSO02
P3.8/SLSO06/TXD1A
P3.9/RXD1A
P3.10/REQ0
P3.11/REQ1
P3.12/RXDCAN0/RXD0B
P3.13/TXDCAN0/TXD0B
P3.14/RXDCAN1/RXD1B
P3.15/TXDCAN1/TXD1B
OUT52/OUT28/HWCFG0/IN52/IN28/P4.0
OUT53/OUT29/HWCFG1/IN53/IN29/P4.1
OUT54/OUT30/HWCFG2/IN54/IN30/P4.2
P4.3/IN31/IN55/OUT31/OUT55/SYSCLK
OCDSDBG0/OUT40/IN40/P5.0
OCDSDBG1/OUT41/IN41/P5.1
OCDSDBG2/OUT42/IN42/P5.2
OCDSDBG4/OUT44/IN44/P5.4
OCDSDBG3/OUT43/IN43/P5.3
OCDSDBG5/OUT45/IN45/P5.5
OCDSDBG6/OUT46/IN46/P5.6
OCDSDBG7/OUT47/IN47/P5.7
OCDSDBG8/RDATA0B/P5.8
OCDSDBG9/RVALID0B/P5.9
OCDSDBG10/RREADY0B/P5.10
OCDSDBG11/RCLK0B/P5.11
OCDSDBG12/TDATA0/P5.12
OCDSDBG13/TVALID0B/P5.13
OCDSDBG14/TREADY0B/P5.14
OCDSDBG15/TCLK0/P5.15
FCLP0A
FCLN0
SOP0A
SON0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN8
AN7
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
TRST
TCK
TDI
TDO
TMS
BRKIN
BRKOUT
NMI
HDRST
PORST
BYPASS
TESTMODE
XTAL1
XTAL2
VDD
VDDP
VSS
N.C.
N.C.
TRCLK
TC1762
VDD
VDDP
VSS
VDDMF
VSSMF
VDDAF
VSSAF
VFAREF
VFAGND
VDDM
VSSM
VAREF0
VAGND0
VDD
VDDP
VSS
VDD
VDDP
VSS
VSS
VDD
VDDP
VSS
VDDOSC
VDDOSC3
VSSOSC
VDDFL3
VDDP
VSS
VDD
VDDP
VSS
VDD
VDDP
VSS
MCP06067
TC1762
General Device InformationPreliminary
Data Sheet 9 V1.0, 2008-04
2.4 Pad Driver and Input Classes Overview
The TC1762 provides different types and classes of input and output lines. For
understanding of the abbreviations in Table 2-1 starting at the next page, Table 4-1
gives an overview on the pad type and class types.
TC1762
General Device InformationPreliminary
Data Sheet 10 V1.0, 2008-04
2.5 Pin Definitions and Functions
Table 2-1 shows the TC1762 pin definitions and functions.
Table 2-1 Pin Definitions and Functions
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
Parallel Ports
P0 I/O A1 VDDP Port 0
Port 0 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O lines or external trigger
inputs.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
145
146
147
148
166
167
173
174
149
150
151
152
168
169
175
176
IN0 / OUT0 /
IN1 / OUT1 /
IN2 / OUT2 /
IN3 / OUT3 /
IN4 / OUT4 /
IN5 / OUT5 /
IN6 / OUT6 /
REQ2
IN7 / OUT7 /
REQ3
IN8 / OUT8 /
IN9 / OUT9 /
IN10 / OUT10 /
IN11 / OUT11 /
IN12 / OUT12 /
IN13 / OUT13 /
IN14 / OUT14 /
REQ4
IN15 / OUT15 /
REQ5
OUT56 line of GPTA
OUT57 line of GPTA
OUT58 line of GPTA
OUT59 line of GPTA
OUT60 line of GPTA
OUT61 line of GPTA
OUT62 line of GPTA
External trigger input 2
OUT63 line of GPTA
External trigger input 3
OUT64 line of GPTA
OUT65 line of GPTA
OUT66 line of GPTA
OUT67 line of GPTA
OUT68 line of GPTA
OUT69 line of GPTA
OUT70 line of GPTA
External trigger input 4
OUT71 line of GPTA
External trigger input 5
In addition, the state of the port pins are
latched into the software configuration input
register SCU_SCLIR at the rising edge of
HDRST. Therefore, Port 0 pins can be used
for operating mode selections by software.
TC1762
General Device InformationPreliminary
Data Sheet 11 V1.0, 2008-04
P1 I/O VDDP Port 1
Port 1 is a 15-bit bi-directional general
purpose I/O port which can be alternatively
used for GPTA I/O lines and ADC0 interface.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
91
92
93
98
107
108
109
110
94
95
96
97
73
72
71
A1
A1
A1
A1
A1
A1
A1
A1
A2
A2
A2
A2
A1
A1
A1
IN16 / OUT16 /
IN17 / OUT17 /
IN18 / OUT18 /
IN19 / OUT19 /
IN20 / OUT20 /
IN21 / OUT21 /
IN22 / OUT22 /
IN23 / OUT23 /
IN24 / OUT24 /
IN25 / OUT25 /
IN26 / OUT26 /
IN27 / OUT27 /
AD0EMUX0
AD0EMUX1
AD0EMUX2
OUT72 line of GPTA
OUT73 line of GPTA
OUT74 line of GPTA
OUT75 line of GPTA
OUT76 line of GPTA
OUT77 line of GPTA
OUT78 line of GPTA
OUT79 line of GPTA
IN48 / OUT48 line of GPTA
IN49 / OUT49 line of GPTA
IN50 / OUT50 line of GPTA
IN51 / OUT51 line of GPTA
ADC0 external multiplexer
control output 0
ADC0 external multiplexer
control output 1
ADC0 external multiplexer
control output 2
In addition, P1.4 also serves as emergency
shut-off input for certain I/O lines (e.g. GPTA
related outputs).
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 12 V1.0, 2008-04
P2 I/O VDDP Port 2
Port 2 is a 14-bit bi-directional general-
purpose I/O port which can be alternatively
used for GPTA I/O, and interface for MLI0,
MSC0 or SSC0.
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
74
75
76
77
78
79
80
81
A2
A2
A2
A2
A1
A2
A1
A1
TCLK0
IN32 / OUT32
TREADY0A
IN33 / OUT33
SLSO03
TVALID0A
IN34 / OUT34
TDATA0
IN35 / OUT35
RCLK0A
IN36 / OUT36
RREADY0A
IN37 / OUT37
RVALID0A
IN38 / OUT38
RDATA0A
IN39 / OUT39
MLI0 transmit channel clock
output A
line of GPTA
MLI0 transmit channel ready
input A
line of GPTA
SSC0 slave select output 3
MLI0 transmit channel valid
output A
line of GPTA
MLI0 transmit channel data
output A
line of GPTA
MLI0 receive channel clock
input A
line of GPTA
MLI0 receive channel ready
output A
line of GPTA
MLI0 receive channel valid
input A
line of GPTA
MLI0 receive channel data
input A
line of GPTA
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 13 V1.0, 2008-04
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
164
160
161
162
163
165
A2
A2
A2
A2
A2
A1
SLSO04
EN00
SLSO05
EN01
FCLP0B
SOP0B
SDI0
SSC0 Slave Select output 4
MSC0 enable output 0
SSC0 Slave Select output 5
MSC0 enable output 1
MSC0 clock output B
MSC0 serial data output B
MSC0 serial data input
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 14 V1.0, 2008-04
P3 I/O VDDP Port 3
Port 3 is a 16-bit bi-directional general-
purpose I/O port which can be alternatively
used for ASC0/1, SSC0 and CAN lines.
P3.0
P3.1 136
135 A2
A2 RXD0A
TXD0A ASC0 receiver inp./outp. A
ASC0 transmitter output A
This pin is sampled at the rising edge of
PORST. If this pin and the BYPASS input pin
are both active, then oscillator bypass mode
is entered.
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
129
130
132
126
127
131
128
138
137
144
143
142
134
133
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A2
A2
A2
A2
SCLK0
MRST0
MTSR0
SLSO00
SLSO01
SLSI0
SLSO02
SLSO06
TXD1A
RXD1A
REQ0
REQ1
RXDCAN0
RXD0B
TXDCAN0
TXD0B
RXDCAN1
RXD1B
TXDCAN1
TXD1B
SSC0 clock input/output
SSC0 master receive input/
slave transmit output
SSC0 master transmit
output/slave receive input
SSC0 slave select output 0
SSC0 slave select output 1
SSC0 slave select input
SSC0 slave select output 2
SSC0 slave select output 6
ASC1 transmitter output A
ASC1 receiver inp./outp. A
External trigger input 0
External trigger input 1
CAN node 0 receiver input
ASC0 receiver inp./outp. B
CAN node 0 transm. output
ASC0 transmitter output B
CAN node 1 receiver input
ASC1 receiver inp./outp. B
CAN node 1 transm. output
ASC1 transmitter output B
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 15 V1.0, 2008-04
P4 I/O VDDP Port 4 / Hardware Configuration Inputs
P4.[3:0] HWCFG[3:0] Boot mode and boot location
inputs; inputs are latched
with the rising edge of
HDRST.
During normal operation, Port 4 pins may be
used as alternate functions for GPTA or
system clock output.
P4.0
P4.1
P4.2
P4.3
86
87
88
90
A1
A1
A2
A2
IN28 / OUT28 /
IN29 / OUT29 /
IN30 / OUT30 /
IN31 / OUT31 /
SYSCLK
IN52 / OUT52 line of GPTA
IN53 / OUT53 line of GPTA
IN54 / OUT54 line of GPTA
IN55 / OUT55 line of GPTA
System Clock Output
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 16 V1.0, 2008-04
P5 I/O A2 VDDP Port 5
Port 5 is a 16-bit bi-directional general-
purpose I/O port. In emulation, it is us ed as a
trace port for OCDS Level 2 debug lines. In
normal operation, it is used for GPTA I/O or
the MLI0 interface.
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
1
2
3
4
5
6
7
8
OCDSDBG0
IN40 / OUT40
OCDSDBG1
IN41 / OUT41
OCDSDBG2
IN42 / OUT42
OCDSDBG3
IN43 / OUT43
OCDSDBG4
IN44 / OUT44
OCDSDBG5
IN45 / OUT45
OCDSDBG6
IN46 / OUT46
OCDSDBG7
IN47 / OUT47
OCDS L2 Debug Line 0
(Pipeline Status Sig. PS0)
line of GPTA
OCDS L2 Debug Line 1
(Pipeline Status Sig. PS1)
line of GPTA
OCDS L2 Debug Line 2
(Pipeline Status Sig. PS2)
line of GPTA
OCDS L2 Debug Line 3
(Pipeline Status Sig. PS3)
line of GPTA
OCDS L2 Debug Line 4
(Pipeline Status Sig. PS4)
line of GPTA
OCDS L2 Debug Line 5
(Break Qualification Line
BRK0)
line of GPTA
OCDS L2 Debug Line 6
(Break Qualification Line
BRK1)
line of GPTA
OCDS L2 Debug Line 7
(Break Qualification Line
BRK2)
line of GPTA
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 17 V1.0, 2008-04
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
13
14
15
16
17
18
19
20
OCDSDBG8
RDATA0B
OCDSDBG9
RVALID0B
OCDSDBG10
RREADY0B
OCDSDBG11
RCLK0B
OCDSDBG12
TDATA0
OCDSDBG13
TVALID0B
OCDSDBG14
TREADY0B
OCDSDBG15
TCLK0
OCDS L2 Debug Line 8
(Indirect PC Addr. PC0)
MLI0 receive channel data
input B
OCDS L2 Debug Line 9
(Indirect PC Addr. PC1)
MLI0 receive channel valid
input B
OCDS L2 Debug Line 10
(Indirect PC Addr. PC2)
MLI0 receive channel ready
output B
OCDS L2 Debug Line 11
(Indirect PC Addr. PC3)
MLI0 receive channel clock
input B
OCDS L2 Debug Line 12
(Indirect PC Addr. PC04)
MLI0 transmit channel data
output B
OCDS L2 Debug Line 13
(Indirect PC Addr. PC05)
MLI0 transmit channel valid
output B
OCDS L2 Debug Line 14
(Indirect PC Address PC6)
MLI0 transmit channel ready
input B
OCDS L2 Debug Line 15
(Indirect PC Address PC7)
MLI0 transmit channel clock
output B
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 18 V1.0, 2008-04
MSC0 Outputs
FCLP0A
FCLN0
SOP0A
SON0
157
156
159
158
O
O
O
O
CVDDP LVDS MSC Clock and Data Outputs2)
MSC0 Differential Driver Clock Output
Positive A
MSC0 Differential Driver Clock Output
Negative
MSC0 Differential Driver Serial Data Output
Positive A
MSC0 Differential Driver Serial Data Output
Negative
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 19 V1.0, 2008-04
Analog Inputs
AN[35:0]
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
67
66
65
64
63
62
61
36
60
59
58
57
56
55
50
49
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
ID – Analog Input Port
The Analog Input Port provides altogether 36
analog input lines to ADC0 and FAD C.
AN[31:0]: ADC0 analog inputs [31:0]
AN[35:32]: FADC analog differential inputs
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7
Analog input 8
Analog input 9
Analog input 10
Analog input 11
Analog input 12
Analog input 13
Analog input 14
Analog input 15
Analog input 16
Analog input 17
Analog input 18
Analog input 19
Analog input 20
Analog input 21
Analog input 22
Analog input 23
Analog input 24
Analog input 25
Analog input 26
Analog input 27
Analog input 28
Analog input 29
Analog input 30
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 20 V1.0, 2008-04
AN31
AN32
AN33
AN34
AN35
32
31
30
29
28
I D – Analog input 31
Analog input 32
Analog input 33
Analog input 34
Analog input 35
System I/O
TRST 114 I A21) VDDP JTAG Module Reset/Enable Input
TCK 115 I A21) VDDP JTAG Module Clock Input
TDI 111 I A11) VDDP JTAG Module Serial Data Input
TDO 113 O A2 VDDP JTAG Module Serial Data Output
TMS 112 I A21) VDDP JTAG Module State Machine Control I nput
BRKIN 117 I/O A3 VDDP OCDS Break Input (Alternate Output)2)3)
BRK
OUT 116 I/O A3 VDDP OCDS Break Output (Alternate Input)2)3)
TRCLK 9OA4 VDDP Trace Clock for OCDS_L2 Lines2)
NMI 120 I A24)5) VDDP Non-Maskable Interrupt Input
HDRST 122 I/O A26) VDDP Hardware Reset Input /
Reset Indication Output
PORST
7) 121 I A24) VDDP Power-on Reset Input
BYPASS 119 I A11) VDDP PLL Clock Bypass Select Input
This input has to be held stable during power-
on resets. With BYPASS = 1, the spike filters
in the HDRST, PORST and NMI inputs are
switched off.
TEST
MODE 118 I A24)8) VDDP Test Mode Select Input
For normal operation of the TC1762, this pin
should be connected to high level.
XTAL1
XTAL2 102
103 I
On.a. VDDOSC Oscillator/PLL/Clock Generator
Input/Output Pins
N.C. 21,
89 –– – Not Connected
These pins are reserved for future extension
and must not be connected externally.
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 21 V1.0, 2008-04
Power Supplies
VDDM 54 – – – ADC Analog Part Power Supply (3.3 V)
VSSM 53 – – – ADC Analog Part Ground for VDDM
VDDMF 24 – – – FADC Analog Part Power Supply (3.3 V)
VSSMF 25 – – – FADC Analog Part Ground for VDDMF
VDDAF 23 – – – FADC Analog Part Logic Power Supply
(1.5 V)
VSSAF 22 – – – FADC Analog Part Logic Ground for VDDAF
VAREF0 52 – – – ADC Reference Voltage
VAGND0 51 – – – ADC Reference Ground
VFAREF 26 – – – FADC Reference Voltage
VFAGND 27 – – – FADC Reference Ground
VDDOSC 105 – – – Main Oscillator and PLL Power Supply
(1.5 V)
VDDOSC3 106 – – – Main Oscillator Power Supply (3.3 V)
VSSOSC 104 – – – Main Oscillator and PLL Ground
VDDFL3 141 – – – Power Supply for Flash (3.3 V)
VDD 10,
68,
84,
99,
123,
153,
170
–– – Core Power Supply (1.5 V)
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 22 V1.0, 2008-04
VDDP 11,
69,
83,
100,
124,
154,
171,
139
–– – Port Power Supply (3.3 V)
VSS 12,
70,
85,
101,
125,
155,
172,
140,
82
–– – Ground
1) These pads are I/O pads with input only function. Its input characteristics are identical with the input
characteristics as defined for class A pads.
2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range),
an undefined output driving level may occur at these pins.
3) Programmed by software as either break input or break output.
4) These pads are input only pads with input characteristics.
5) Input only pads with input spike filter.
6) Open drain pad with input spike filter.
7) The dual input reset system of TC1762/TC1766ED, assumes that the PORST reset pin is used for power-on
reset only. It has to be taken into account that if a system uses the PORST reset input for other system resets,
the emulation part of the TC1766ED Emulation Device is reset as well. Thus, it will always force a comple te
re-initialization of the emulator and will prevent the user debugging across these types of resets.
8) Input only pads without input spike filter.
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pins I/O Pad
Driver
Class
Power
Supply Functions
TC1762
General Device InformationPreliminary
Data Sheet 23 V1.0, 2008-04
Table 2-2 List of Pull-up/Pull-down Reset Behavior of the Pins
Pins PORST =0 PORST=1
All GPIOs, TDI, TMS, TDO Pull-up
HDRST Drive-low Pull-up
BYPASS Pull-up High-impedance
TRST, TCK High-impedance Pull-down
TRCLK High-impedance
BRKIN, BRKOUT, TESTMODE Pull-up
NMI, PORST Pull-down
TC1762
Functional DescriptionPreliminary
Data Sheet 24 V1.0, 2008-04
3 Functional Description
Chapter 3 provides an overview of the TC1762 functional description.
3.1 System Architecture and On-Chip Bus Systems
The TC1762 has two independent on-chip buses (see also TC1762 block diagram on
Page 2-6):
• Local Memory Bus (LMB)
• System Peripheral Bus (SPB)
The LMB Bus connects the CPU local resources for data and instruction fetch. The Local
Memory Bus interconnects the memory units and functional units, such as CPU and
PMU. The main target of the LMB bus is to support devices with fast response times,
optimized for speed. This allows the DMI and PMI fast access to local memory and
reduces load on the FPI bus. The Tricore system itself is located on LMB bus.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable
length 64-bit block transfers.
The SPB Bus is accessible to the CPU via the LMB Bus bridge. The System Peripheral
Bus (SPB Bus) in TC1762 is an on-chip FPI Bus. The FPI Bus interconnects the
functional units of the TC1762, such as the DMA and on-chip peripheral components.
The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick
to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast
FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is
designed to sustain high transfer rates. For example, a peak transfer rate of up to 320
Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. With a 66 MHz
bus clock, the peak transfer rate is up to 264 Mbytes/s. Multiple data transfers per bus
arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth.
Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed
is 66 or 80 MHz depending on the derivative.
Additionally, two simplified bus interfaces ar e connected to and controlled by the DMA
Controller:
•DMA Bus
• SMIF Interface
TC1762
Functional DescriptionPreliminary
Data Sheet 25 V1.0, 2008-04
3.2 On-Chip Memories
As shown in the TC1762 block diagram on Page 2-6, some of the TC1762 units provide
on-chip memories that are used as program or data memory.
• Program memory in PMU
– 16 Kbyte Boot ROM (BROM)
– 1024 Kbyte Program Flash (PFlash)
• Program memory in PMI
– 8 Kbyte Scratch-Pad RAM (SPRAM)
– 8 Kbyte Instruction Cache (ICACHE)
• Data memory in PMU
– 16 Kbyte Data Flash (DFlash)
– 4 Kbyte Overlay RAM (OVRAM)
• Data memory in DMI
– 32 Kbyte Local Data RAM (LDRAM)
• On-chip SRAM with parity error protection
Features of Program Flash
• 1024 Kbyte on-chip program Flash memory
• Usable for instruction code or constant data storage
• 256-byte program interface
– 256 bytes are programmed into PFLASH page in one step/command
• 256-bit read interface
– Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers
• Dynamic correction of single-bit errors during read access
• Detection of double-bit errors
• Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte and one 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
• Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
• Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
• Password mechanism for temporary disabling of write and read protection
• On-chip generation of programming voltage
• JEDEC-standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
• Margin check for detection of problematic PFLASH bits