KSZ9021RL/RN Gigabit Ethernet Transceiver with RGMII Support Highlights Applications * Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet Transceiver * RGMII interface compliant to RGMII Version 1.3 * RGMII I/Os with 3.3V/2.5V tolerant and programmable timings to adjust and correct delays on both Tx and Rx paths * Auto-negotiation to automatically select the highest link up speed (10/100/100Mbps) and duplex (half/full) * On-chip termination resistors for the differential pairs * On-chip LDO controller to support single 3.3V supply operation - requires only external FET to generate 1.2V for the core * Jumbo frame support up to 16KB * 125MHz Reference Clock Output * Programmable LED outputs for link, activity and speed * Baseline Wander Correction * LinkMD(R) TDR-based cable diagnostics for identification of faulty copper cabling * Parametric NAND Tree support for fault detection between chip I/Os and board. * Loopback modes for diagnostics * Automatic MDI/MDI-X crossover for detection and correction of pair swap at all speeds of operation * Automatic detection and correction of pair swap, pair skew and pair polarity * MDC/MDIO Management Interface for PHY register configuration * Interrupt pin option * Power down and power saving modes * Operating Voltages - Core: 1.2V (external FET or regulator) - I/O: 3.3V or 2.5V - Transceiver: 3.3V * Available packages * * * * * * * * * * * Laser/Network printer Network attached storage (NAS) Network server Gigabit LAN on motherboard (GLOM) Broadband gateway Gigabit SOHO/SMB router IPTV IP Set-top box Game console Triple-play (data, voice, video) media center Media converter 64-pin E-LQFP (10mm x 10mm): KSZ9021RL 48-pin QFN (7mm x 7mm): KSZ9021RN 2009-2019 Microchip Technology Inc. DS00003050A-page 1 KSZ9021RL/RN TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00003050A-page 2 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Overview ..................................................................................................................................................................... 23 4.0 Register Description ...................................................................................................................................................................... 37 5.0 Operational Characteristics ........................................................................................................................................................... 50 6.0 Timing Diagrams ........................................................................................................................................................................... 53 7.0 Package Information ..................................................................................................................................................................... 60 Appendix A: Data Sheet Revision History ........................................................................................................................................... 63 The Microchip Web Site ...................................................................................................................................................................... 64 Customer Change Notification Service ............................................................................................................................................... 64 Customer Support ............................................................................................................................................................................... 64 Product Identification System ............................................................................................................................................................. 65 2009-2019 Microchip Technology Inc. DS00003050A-page 3 KSZ9021RL/RN 1.0 INTRODUCTION 1.1 General Description The KSZ9021RL is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer Transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9021RL provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at 10/100/1000Mbps speed. The KSZ9021RL reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core. The KSZ9021RL provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9021 I/Os and board. Micrel LinkMD(R) TDR-based cable diagnostics permit identification of faulty copper cabling. Remote and local loopback functions provide verification of analog and digital data paths. The KSZ9021RL is available in a 64-pin, RoHS compliant E-LQFP package, and is offered as the KSZ9021RN in the smaller 48-pin QFN package (See Ordering Information). 1.2 Functional Diagram FIGURE 1-1: KSZ9021RL/RN FUNCTIONAL DIAGRAM KSZ9021RL/RN MDC / MDIO Management Magnetics 10/100/1000 Mbps RGMII Ethernet MAC On-chip Termination Resistors RGMII RJ-45 Connector Media Types: 10Base-T 100Base-TX 1000Base-T LDO Controller VIN 3.3VA DS00003050A-page 4 VOUT 1.2V (for core voltages) 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 2.0 PIN DESCRIPTION AND CONFIGURATION 2.1 Pin Configuration - KSZ9021RL 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGNDH_BG ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO / LED_MODE DVDDL VSS DVDDL INT_N COL MDIO 64-PIN E-LQFP (TOP VIEW) AVDDH FIGURE 2-1: MDC 48 CRS 47 RX_CLK / PHYAD 2 46 AVDDL RX_ER 45 5 AVDDL DVDDH 44 6 AVDDH RX_DV / CLK125_EN 43 7 TXRXP_B RXD0 / MODE0 42 8 TXRXM_B RXD1 / MODE1 41 9 AGNDH DVDDL 40 10 TXRXP_C VSS 39 11 TXRXM_C RXD2 / MODE2 38 12 AVDDL DVDDH 37 13 AVDDL RXD3 / MODE3 36 14 TXRXP_D DVDDL 35 15 TXRXM_D VSS 34 16 AVDDH TX_EN 33 TXD0 TXD1 TXD2 TXD3 VSS DVDDL DVDDH TX_ER GTX_CLK Exposed Pad on bottom of chip VSS 4 DVDDL AGNDH LED1 / PHYAD0 3 DVDDH TXRXM_A LED2 / PHYAD1 2 VSS TXRXP_A VSS 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2009-2019 Microchip Technology Inc. DS00003050A-page 5 KSZ9021RL/RN 2.1.1 PIN DESCRIPTION - KSZ9021RL Pin Number Pin Name Type (Note 1) 1 TXRXP_A I/O Pin Function Media Dependent Interface[0], positive signal of differential pair 1000Base-T Mode: TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_A is the positive transmit signal (TX+) for MDI configuration and the positive receive signal (RX+) for MDI-X configuration, respectively. 2 TXRXM_A I/O Media Dependent Interface[0], negative signal of differential pair 1000Base-T Mode: TXRXM_A corresponds to BI_DA- for MDI configuration and BI_DB- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_A is the negative transmit signal (TX-) for MDI configuration and the negative receive signal (RX-) for MDI-X configuration, respectively. 3 AGNDH Gnd 4 AVDDL P 1.2V analog VDD 5 AVDDL P 1.2V analog VDD 3.3V analog VDD 6 AVDDH P 7 TXRXP_B I/O Analog ground Media Dependent Interface[1], positive signal of differential pair 1000Base-T Mode: TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_B is the positive receive signal (RX+) for MDI configuration and the positive transmit signal (TX+) for MDI-X configuration, respectively. 8 TXRXM_B I/O Media Dependent Interface[1], negative signal of differential pair 1000Base-T Mode: TXRXM_B corresponds to BI_DB- for MDI configuration and BI_DA- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_B is the negative receive signal (RX-) for MDI configuration and the negative transmit signal (TX-) for MDI-X configuration, respectively. 9 AGNDH DS00003050A-page 6 Gnd Analog ground 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 10 TXRXP_C I/O Pin Function Media Dependent Interface[2], positive signal of differential pair 1000Base-T Mode: TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_C is not used. 11 TXRXM_C I/O Media Dependent Interface[2], negative signal of differential pair 1000Base-T Mode: TXRXM_C corresponds to BI_DC- for MDI configuration and BI_DD- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_C is not used. 12 AVDDL P 13 AVDDL P 14 TXRXP_D I/O 1.2V analog VDD 1.2V analog VDD Media Dependent Interface[3], positive signal of differential pair 1000Base-T Mode: TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_D is not used. 15 TXRXM_D I/O Media Dependent Interface[3], negative signal of differential pair 1000Base-T Mode: TXRXM_D corresponds to BI_DD- for MDI configuration and BI_DC- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_D is not used. 16 AVDDH P 17 VSS Gnd Digital ground 18 VSS Gnd Digital ground 2009-2019 Microchip Technology Inc. 3.3V analog VDD DS00003050A-page 7 KSZ9021RL/RN Pin Number 19 Pin Name LED2 / PHYAD1 Type (Note 1) I/O Pin Function LED Output: Programmable LED2 Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[1] during powerup/reset. See "Strapping Options" section for details. The LED2 pin is programmed by the LED_MODE strapping option (pin 55), and is defined as follows. Single LED Mode Link Pin State LED Definition Link off H OFF Link on (any speed) L ON Tri-color Dual LED Mode Pin State Link / Activity Link off 1000 Link / No Activity 1000 Link / Activity (RX, TX) LED Definition LED2 LED1 LED2 LED1 H H OFF OFF L H ON Off Toggle H Blinking OFF 100 Link / No Activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No Activity 10 Link / Activity (RX, TX) L L ON ON Toggle Toggle Blinking Blinking For Tri-color Dual LED Mode, LED2 works in conjunction with LED1 (pin 21) to indicate 10 Mbps Link and Activity. 20 DVDDH DS00003050A-page 8 P 3.3V/2.5V digital VDD 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Pin Number 21 Pin Name Type (Note 1) LED1 / PHYAD0 I/O Pin Function LED Output: Programmable LED1 Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[0] during powerup/reset. See "Strapping Options" section for details. The LED1 pin is programmed by the LED_MODE strapping option (pin 55), and is defined as follows. Single LED Mode Activity Pin State LED Definition H OFF Toggle Blinking No Activity Activity (RX, TX) Tri-color Dual LED Mode Pin State Link / Activity Link off 1000 Link / No Activity 1000 Link / Activity (RX, TX) LED Definition LED2 LED1 LED2 LED1 H H OFF OFF L H ON Off Toggle H Blinking OFF 100 Link / No Activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No Activity 10 Link / Activity (RX, TX) L L ON ON Toggle Toggle Blinking Blinking For Tri-color Dual LED Mode, LED2 works in conjunction with LED1 (pin 21) to indicate 10 Mbps Link and Activity. 22 DVDDL P 23 VSS Gnd 1.2V digital VDD Digital ground 24 TXD0 I RGMII Mode: 25 TXD1 I RGMII Mode: 26 TXD2 I RGMII Mode: RGMII TD0 (Transmit Data 0) Input RGMII TD1 (Transmit Data 1) Input RGMII TD2 (Transmit Data 2) Input 27 TXD3 I RGMII Mode: RGMII TD3 (Transmit Data 3) Input 28 VSS Gnd 29 DVDDL P Digital ground 30 DVDDH P 3.3V/2.5V digital VDD 31 TX_ER I RGMII Mode: 1.2V digital VDD This pin is not used and should be left as a no connect. 2009-2019 Microchip Technology Inc. DS00003050A-page 9 KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 32 GTX_CLK I RGMII Mode: 33 TX_EN I RGMII Mode: Pin Function RGMII TXC (Transmit Reference Clock) Input RGMII TX_CTL (Transmit Control) Input 34 VSS Gnd 35 DVDDL P 36 RXD3 / MODE3 I/O Digital ground 1.2V digital VDD RGMII Mode: RGMII RD3 (Receive Data 3) Output / Config Mode: The pull-up/pull-down value is latched as MODE3 during power-up/ reset. See "Strapping Options" section for details. 37 DVDDH P 38 RXD2 / MODE2 I/O 3.3V/2.5V digital VDD RGMII Mode: RGMII RD2 (Receive Data 2) Output / Config Mode: The pull-up/pull-down value is latched as MODE2 during powerup/reset. See "Strapping Options" section for details. 39 VSS Gnd 40 DVDDL P 41 RXD1 / MODE1 I/O Digital ground 1.2V digital VDD RGMII Mode: RGMII RD1 (Receive Data 1) Output / Config Mode: The pull-up/pull-down value is latched as MODE1 during power-up/ reset. See "Strapping Options" section for details. 42 RXD0 / MODE0 I/O RGMII Mode: RGMII RD0 (Receive Data 0) Output / Config Mode: The pull-up/pull-down value is latched as MODE0 during power-up/ reset. See "Strapping Options" section for details. 43 RX_DV / CLK125_EN I/O RGMII Mode: RGMII RX_CTL (Receive Control) Output / Config Mode: Latched as CLK125_NDO Output Enable during power-up/reset. See "Strapping Options" section for details. 44 DVDDH P 3.3V/2.5V digital VDD 45 RX_ER O RGMII Mode: 46 RX_CLK / PHYAD2 I/O RGMII Mode: This pin is not used and should be left as a no connect. RGMII RXC (Receive Reference Clock) Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[2] during powerup/reset. See "Strapping Options" section for details. 47 CRS O RGMII Mode: This pin is not used and should be left as a no connect. DS00003050A-page 10 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 48 MDC Ipu Management Data Clock Input 49 MDIO Ipu/O Management Data Input/Output Pin Function This pin is the input reference clock for MDIO (pin 49). This pin is synchronous to MDC (pin 48) and requires an external pull-up resistor to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k. 50 COL O RGMII Mode: 51 INT_N O Interrupt Output This pin is not used and should be left as a no connect. This pin provides a programmable interrupt output and requires an external pull-up resistor to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k when active low. Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt output to active low (default) or active high. 52 DVDDL P 53 VSS Gnd 54 DVDDL P 55 CLK125_NDO / I/O LED_MODE 1.2V digital VDD Digital ground 1.2V digital VDD 125MHz Clock Output This pin provides a 125MHz reference clock output option for use by the MAC. / Config Mode: The pull-up/pull-down value is latched as LED_MODE during power-up/reset. See "Strapping Options" section for details. 56 RESET_N Ipu Chip Reset (active low) Hardware pin configurations are strapped-in at the de-assertion (rising edge) of RESET_N. See "Strapping Options" section for more details. 57 LDO_O O On-chip 1.2V LDO Controller Output This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the chip's core voltages. If 1.2V is provided by the system and this pin is not used, it can be left floating. 58 AVDDL_PLL P 1.2V analog VDD for PLL 59 XO O 25MHz Crystal feedback This pin is a no connect if oscillator or external clock source is used. 60 XI I Crystal / Oscillator / External Clock Input 25MHz 50ppm tolerance 61 AVDDH P 62 ISET I/O 3.3V analog VDD Set transmit output level 63 AGNDH_BG Gnd Analog ground Connect a 4.99K 1% resistor to ground on this pin. 2009-2019 Microchip Technology Inc. DS00003050A-page 11 KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 64 AVDDH P E-PAD E-PAD Gnd Pin Function 3.3V analog VDD Exposed Pad on bottom of chip Connect E-PAD to ground. Note 1: P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up. Ipu/O = Input with internal pull-up / Output. DS00003050A-page 12 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 2.1.2 STRAPPING OPTIONS - KSZ9021RL Pin Number Pin Name 46 19 21 PHYAD2 PHYAD1 PHYAD0 Type Pin Function (Note 1) I/O I/O I/O The PHY Address, PHYAD[2:0], is latched at power-up/reset and is configurable to any value from 1 to 7. Each PHY address bit is configured as follows: Pull-up = 1 Pull-down = 0 PHY Address bits [4:3] are always set to `00'. 36 38 41 42 43 MODE3 MODE2 MODE1 MODE0 CLK125_E N I/O I/O I/O I/O I/O The MODE[3:0] strap-in pins are latched at power-up/reset and are defined as follows: MODE[3:0] Mode 0000 Reserved - not used 0001 Reserved - not used 0010 Reserved - not used 0011 Reserved - not used 0100 NAND Tree Mode 0101 Reserved - not used 0110 Reserved - not used 0111 Chip Power Down Mode 1000 Reserved - not used 1001 Reserved - not used 1010 Reserved - not used 1011 Reserved - not used 1100 RGMII Mode - advertise 1000Base-T full-duplex only 1101 RGMII Mode - advertise 1000Base-T full and half-duplex only 1110 RGMII Mode - advertise all capabilities (10/100/1000 speed half/full duplex), except 1000Base-T half-duplex 1111 RGMII Mode - advertise all capabilities (10/100/1000 speed half/full duplex) CLK125_EN is latched at power-up/reset and is defined as follows: Pull-up = Enable 125MHz Clock Output Pull-down = Disable 125MHz Clock Output Pin 55 (CLK125_NDO) provides the 125MHz reference clock output option for use by the MAC. 55 LED_MODE I/O LED_MODE is latched at power-up/reset and is defined as follows: Pull-up = Single LED Mode Pull-down = Tri-color Dual LED Mode 2009-2019 Microchip Technology Inc. DS00003050A-page 13 KSZ9021RL/RN Note 1: I/O = Bi-directional. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to the incorrect configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode. Pin Configuration - KSZ9021RN AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO / LED_MODE DVDDH DVDDL INT_N MDIO 48-PIN QFN (TOP VIEW) ISET FIGURE 2-2: 48 47 46 45 44 43 42 41 40 39 38 37 AVDDH 1 36 MDC TXRXP_A 2 35 RX_CLK / PHYAD2 TXRXM_A 3 34 DVDDH AVDDL 4 33 RX_DV / CLK125_EN TXRXP_B 5 32 RXD0 / MODE0 TXRXM_B 6 31 RXD1 / MODE1 30 DVDDL Paddle Ground (on bottom of chip) 10 27 RXD3 / MODE3 TXRXM_D 11 26 DVDDL AVDDH 12 25 TX_EN DS00003050A-page 14 13 14 15 16 17 18 19 20 21 22 23 24 GTX_CLK TXRXP_D DVDDL RXD2 / MODE2 TXD3 28 TXD2 9 TXD1 AVDDL TXD0 VSS DVDDL 29 LED1 / PHYAD0 8 DVDDH TXRXM_C LED2 / PHYAD1 7 DVDDL TXRXP_C VSS_PS 2.2 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 2.2.1 PIN DESCRIPTION - KSZ9021RN Pin Number Pin Name Type (Note 1) 1 AVDDH P 2 TXRXP_A I/O Pin Function 3.3V analog VDD Media Dependent Interface[0], positive signal of differential pair 1000Base-T Mode: TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_A is the positive transmit signal (TX+) for MDI configuration and the positive receive signal (RX+) for MDI-X configuration, respectively. 3 TXRXM_A I/O Media Dependent Interface[0], negative signal of differential pair 1000Base-T Mode: TXRXM_A corresponds to BI_DA- for MDI configuration and BI_DB- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_A is the negative transmit signal (TX-) for MDI configuration and the negative receive signal (RX-) for MDI-X configuration, respectively. 4 AVDDL P 5 TXRXP_B I/O 1.2V analog VDD Media Dependent Interface[1], positive signal of differential pair 1000Base-T Mode: TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_B is the positive receive signal (RX+) for MDI configuration and the positive transmit signal (TX+) for MDI-X configuration, respectively. 6 TXRXM_B I/O Media Dependent Interface[1], negative signal of differential pair 1000Base-T Mode: TXRXM_B corresponds to BI_DB- for MDI configuration and BI_DA- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_B is the negative receive signal (RX-) for MDI configuration and the negative transmit signal (TX-) for MDI-X configuration, respectively. 7 TXRXP_C I/O Media Dependent Interface[2], positive signal of differential pair 1000Base-T Mode: TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_C is not used. 2009-2019 Microchip Technology Inc. DS00003050A-page 15 KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 8 TXRXM_C I/O Pin Function Media Dependent Interface[2], negative signal of differential pair 1000Base-T Mode: TXRXM_C corresponds to BI_DC- for MDI configuration and BI_DD- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_C is not used. 9 AVDDL P 10 TXRXP_D I/O 1.2V analog VDD Media Dependent Interface[3], positive signal of differential pair 1000Base-T Mode: TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXP_D is not used. 11 TXRXM_D I/O Media Dependent Interface[3], negative signal of differential pair 1000Base-T Mode: TXRXM_D corresponds to BI_DD- for MDI configuration and BI_DC- for MDI-X configuration, respectively. 10Base-T/100Base-TX Mode: TXRXM_D is not used. 12 AVDDH P 13 VSS_PS Gnd 14 DVDDL P DS00003050A-page 16 3.3V analog VDD Digital ground 1.2V digital VDD 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Pin Number 15 Pin Name Type (Note 1) LED2 / PHYAD1 I/O Pin Function LED Output: Programmable LED2 Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[1] during power-up/reset. See "Strapping Options" section for details. The LED2 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows. Single LED Mode Link Link off Link on (any speed) Pin State LED Definition H OFF LO ON Tri-color Dual LED Mode Pin State LED Definition Link/Activity LED2 LED1 LED2 LED1 Link off H H OFF OFF 1000 Link / No Activity L H ON ON 1000 Link / Activity (RX, TX) Toggle H Blinking OFF 100 Link / No Activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No Activity L L ON ON Toggle Toggle Blinking Blinking 10 Link / Activity (RX, TX) For Tri-color Dual LED Mode, LED2 works in conjunction with LED1 (pin 17) to indicate 10 Mbps Link and Activity. 16 DVDDH 2009-2019 Microchip Technology Inc. P 3.3V/2.5V digital VDD DS00003050A-page 17 KSZ9021RL/RN Pin Number 17 Pin Name LED1 / PHYAD0 Type (Note 1) I/O Pin Function LED Output: Programmable LED1 Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[0] during powerup/reset. See "Strapping Options" section for details. The LED1 pin is programmed by the LED_MODE strapping option (pin 41), and is defined as follows. Single LED Mode Link No Activity Activity (RX, TX) Pin State LED Definition H OFF Toggle Blinking Tri-color Dual LED Mode Pin State LED Definition Link/Activity Link off 1000 Link / No Activity 1000 Link / Activity (RX, TX) LED2 LED1 LED2 LED1 H H OFF OFF L H ON ON Toggle H Blinking OFF 100 Link / No Activity H L OFF ON 100 Link / Activity (RX, TX) H Toggle OFF Blinking 10 Link / No Activity 10 Link / Activity (RX, TX) L L ON ON Toggle Toggle Blinking Blinking For Tri-color Dual LED Mode, LED1 works in conjunction with LED2 (pin 15) to indicate 10 Mbps Link and Activity. 18 DVDDL P 1.2V digital VDD 19 TXD0 I RGMII Mode: RGMII TD0 (Transmit Data 0) Input 20 TXD1 I RGMII Mode: RGMII TD1 (Transmit Data 1) Input 21 TXD2 I RGMII Mode: 22 TXD3 I RGMII Mode: 23 DVDDL P 1.2V digital VDD 24 GTX_CLK I RGMII Mode: 25 TX_EN I RGMII Mode: 26 DVDDL P 1.2V digital VDD RGMII TD2 (Transmit Data 2) Input RGMII TD3 (Transmit Data 3) Input RGMII TXC (Transmit Reference Clock) Input RGMII TX_CTL (Transmit Control) Input DS00003050A-page 18 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Pin Number 27 Pin Name Type (Note 1) RXD3 / MODE3 I/O Pin Function RGMII Mode: RGMII RD3 (Receive Data 3) Output / Config Mode: The pull-up/pull-down value is latched as MODE3 during powerup/reset. See "Strapping Options" section for details. 28 RXD2 / MODE2 I/O RGMII Mode: RGMII RD2 (Receive Data 2) Output / Config Mode: The pull-up/pull-down value is latched as MODE2 during powerup/reset. See "Strapping Options" section for details. 29 VSS Gnd 30 DVDDL P 31 RXD1 / MODE1 I/O Digital ground 1.2V digital VDD RGMII Mode: RGMII RD1 (Receive Data 1) Output / Config Mode: The pull-up/pull-down value is latched as MODE1 during power-up/ reset. See "Strapping Options" section for details. 32 RXD0 / MODE0 I/O RGMII Mode: RGMII RD0 (Receive Data 0) Output / Config Mode: The pull-up/pull-down value is latched as MODE0 during power-up/ reset. See "Strapping Options" section for details. 33 RX_DV / CLK125_EN I/O RGMII Mode: RGMII RX_CTL (Receive Control) Output / Config Mode: Latched as CLK125_NDO Output Enable during power-up/reset. See "Strapping Options" section for details. 34 DVDDH P 35 RX_CLK / PHYAD2 I/O 3.3V/2.5V digital VDD RGMII Mode: RGMII RXC (Receive Reference Clock) Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[2] during powerup/reset. See "Strapping Options" section for details. 36 MDC Ipu Management Data Clock Input This pin is the input reference clock for MDIO (pin 37). 37 MDIO Ipu/O Management Data Input/Output This pin is synchronous to MDC (pin 36) and requires an external pull-up resistor to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k. 2009-2019 Microchip Technology Inc. DS00003050A-page 19 KSZ9021RL/RN Pin Number Pin Name Type (Note 1) 38 INT_N O Pin Function Interrupt Output This pin provides a programmable interrupt output and requires an external pull-up resistor to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k when active low. Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt output to active low (default) or active high. 39 DVDDL P 1.2V digital VDD 40 DVDDH P 3.3V/2.5V digital VDD 41 CLK125_NDO / I/O 125MHz Clock Output LED_MODE This pin provides a 125MHz reference clock output option for use by the MAC. / Config Mode: The pull-up/pull-down value is latched as LED_MODE during power-up/reset. See "Strapping Options" section for details. 42 RESET_N Ipu Chip Reset (active low) Hardware pin configurations are strapped-in at the de-assertion (rising edge) of RESET_N. See "Strapping Options" section for more details. 43 LDO_O O On-chip 1.2V LDO Controller Output This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the chip's core voltages. If 1.2V is provided by the system and this pin is not used, it can be left floating. 44 AVDDL_PLL P 1.2V analog VDD for PLL 45 XO O 25MHz Crystal feedback 46 XI I 47 AVDDH P 48 ISET I/O This pin is a no connect if oscillator or external clock source is used. Crystal / Oscillator / External Clock Input 25MHz 50ppm tolerance 3.3V analog VDD Set transmit output level Connect a 4.99k 1% resistor to ground on this pin. PADDLE P_GND Gnd Exposed Paddle on bottom of chip Connect P_GND to ground. Note 1: P = Power supply. Gnd = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up. Ipu/O = Input with internal pull-up / Output. DS00003050A-page 20 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 2.2.2 STRAPPING OPTIONS - KSZ9021RN Pin Number Pin Name 35 15 17 PHYAD2 PHYAD1 PHYAD0 Type Pin Function (Note 1) I/O I/O I/O The PHY Address, PHYAD[2:0], is latched at power-up/reset and is configurable to any value from 1 to 7. Each PHY address bit is configured as follows: Pull-up = 1 Pull-down = 0 PHY Address bits [4:3] are always set to `00'. 27 28 31 32 MODE3 MODE2 MODE1 MODE0 I/O I/O I/O I/O The MODE[3:0] strap-in pins are latched at power-up/reset and are defined as follows: MODE[3] Mode 0000 Reserved - not used 0001 Reserved - not used 0010 Reserved - not used 0011 Reserved - not used 0100 NAND Tree Mode 0101 Reserved - not used 0110 Reserved - not used 0111 Chip Power Down Mode 1000 Reserved - not used 1001 Reserved - not used 1010 Reserved - not used 1011 Reserved - not used 1100 RGMII Mode - advertise 1000Base-T full-duplex only 1101 RGMII Mode - advertise 1000Base-T full and Halfduplex only 1110 RGMII Mode - advertise all capabilities (10/100/1000 speed half/full duplex), except 1000Base-T halfduplex 1111 RGMII Mode - advertise all capabilities (10/100/1000 speed half/full duplex) RGMII Mode - advertise all capabilities (10/100/1000 speed half/full duplex) 33 CLK125_E N I/O CLK125_EN is latched at power-up/reset and is defined as follows: Pull-up = Enable 125MHz Clock Output Pull-down = Disable 125MHz Clock Output Pin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use by the MAC. 41 LED_MODE I/O LED_MODE is latched at power-up/reset and is defined as follows: Pull-up = Single LED Mode Pull-down = Tri-color Dual LED Mode Note 1: I/O = Bi-directional. 2009-2019 Microchip Technology Inc. DS00003050A-page 21 KSZ9021RL/RN Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to the incorrect configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode. DS00003050A-page 22 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 3.0 FUNCTIONAL OVERVIEW The KSZ9021RL/RN is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer Transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable. Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 signaling-based 10Base-T/100Base-TX transceivers are all IEEE 802.3 compliant. The KSZ9021RL/RN reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core. On the copper media interface, the KSZ9021RL/RN can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the IEEE 802.3 standard for 1000Base-T operation. The KSZ9021RL/RN provides the RGMII interface for a direct and seamless connection to RGMII MACs in Gigabit Ethernet Processors and Switches for data transfer at 10/100/1000Mbps speed. The following figure shows a high-level block diagram of the KSZ9021RL/RN. FIGURE 3-1: KSZ9021RL/RN BLOCK DIAGRAM PMA TX10/100/1000 Clock Reset Configurations PMA RX1000 PCS1000 MEDIA INTERFACE PMA RX100 RGMII Interface PCS100 PMA RX10 PCS10 AUTO NEGOTIATION 2009-2019 Microchip Technology Inc. LED DRIVERS DS00003050A-page 23 KSZ9021RL/RN 3.1 3.1.1 Functional Description: 10Base-T/100Base-TX Transceiver 100BASE-TX TRANSMIT The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the RGMII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is set by an external 4.99k 1% resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter. 3.1.2 100BASE-TX RECEIVE The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/ 5B decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC. 3.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY) The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming data stream using the same sequence as at the transmitter. 3.1.4 10BASE-T TRANSMIT The output 10Base-T driver is incorporated into the 100Base-TX driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into typical outputs of 2.5V amplitude. The harmonic contents are at least 31 dB below the fundamental when driven by an all-ones Manchester-encoded signal. 3.1.5 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ9021RL/RN decodes a data frame. The receiver clock is maintained active during idle periods in between receiving data frames. 3.2 Functional Description: 1000Base-T Transceiver The 1000Base-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power efficient line drivers. The following figure shows a high-level block diagram of a single channel of the 1000Base-T transceiver for one of the four differential pairs. DS00003050A-page 24 2009-2019 Microchip Technology Inc. KSZ9021RL/RN FIGURE 3-2: KSZ9021RL/RN 1000BASE-T BLOCK DIAGRAM - SINGLE CHANNEL XTAL OTHER CHANNELS Clk Generation SideStreamScrambler & SymbolEncoder TX Signal Transmit Block PCSStateMachines LEDDriver Analog Hybrid EchoCanceller PairSwap & AlignUnit NEXTCanceller NEXTCanceller NEXTCanceller Baseline Wander Compensation AGC RX ADC + FFE Descrambler + Decoder SLICER RX Signal Clock&Phase Recovery DFE MII Registers AutoNegotiation MII Management Control PMAState Machines 3.2.1 ANALOG ECHO CANCELLATION CIRCUIT In 1000Base-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10Base-T/100Base-TX mode. 3.2.2 AUTOMATIC GAIN CONTROL (AGC) In 1000Base-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. 3.2.3 ANALOG-TO-DIGITAL CONVERTER (ADC) In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to the overall performance of the transceiver. This circuit is disabled in 10Base-T/100Base-TX mode. 2009-2019 Microchip Technology Inc. DS00003050A-page 25 KSZ9021RL/RN 3.2.4 TIMING RECOVERY CIRCUIT In 1000Base-T mode, the mixed-signal clock recovery circuit, together with the digital phase locked loop, is used to recover and track the incoming timing information from the received data. The digital phase locked loop has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. The 1000Base-T slave PHY is required to transmit the exact receive clock frequency recovered from the received data back to the 1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. Additionally, this helps to facilitate echo cancellation and NEXT removal. 3.2.5 ADAPTIVE EQUALIZER In 1000Base-T mode, the adaptive equalizer provides the following functions: * Detection for partial response signaling * Removal of NEXT and ECHO noise * Channel equalization Signal quality is degraded by residual echo that is not removed by the analog hybrid and echo due to impedance mismatch. The KSZ9021RL/RN employs a digital echo canceller to further reduce echo components on the receive signal. In 1000Base-T mode, the data transmission and reception occurs simultaneously on all four pairs of wires (four channels). This results in high frequency cross-talk coming from adjacent wires. The KSZ9021RL/RN employs three NEXT cancellers on each receive channel to minimize the cross-talk induced by the other three channels. In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. 3.2.6 TRELLIS ENCODER AND DECODER In 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one KSZ9021RL/RN is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order and polarity have to be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and then de-scrambled into 8-bit data. 3.3 3.3.1 Functional Description: 10/100/1000 Transceiver Features AUTO MDI/MDI-X The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable between the KSZ9021RL/RN and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the link partner, and then assigns the MDI/MDI-X pair mapping of the KSZ9021RL/RN accordingly. The following table shows the KSZ9021RL/RN 10/100/1000 pin-out assignments for MDI/MDI-X pin mapping. TABLE 3-1: MDI/MDI-X PIN MAPPING MDI MDI-X Pin (RJ-45 pair) 1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T TXRXP/M_A (1,2) A+/- TX+/- TX+/- B+/- RX+/- RX+/- TXRXP/M_B (3,6) B+/- RX+/- RX+/- A+/- TX+/- TX+/- TXRXP/M_C (4,5) C+/- Not used Not used D+/- Not used Not used TXRXP/M_D (7,8) D+/- Not used Not used C+/- Not used Not used Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 28 (1Ch) bit 6. MDI and MDI-X mode is set by register 28 (1Ch) bit 7 if auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X. DS00003050A-page 26 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 3.3.2 PAIR- SWAP, ALIGNMENT, AND POLARITY CHECK In 1000Base-T mode, the KSZ9021RL/RN: * Detects incorrect channel order and automatically restore the pair order for the A, B, C, D pairs (four channels) * Supports 50 * 10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3 standard, and automatically corrects the data skew so the corrected 4-pairs of data symbols are synchronized Incorrect pair polarities of the differential signals are automatically corrected for all speeds. 3.3.3 WAVE SHAPING, SLEW RATE CONTROL AND PARTIAL RESPONSE In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. * For 1000Base-T, a special partial response signaling method is used to provide the band-limiting feature for the transmission path. * For 100Base-TX, a simple slew rate control method is used to minimize EMI. * For 10Base-T, pre-emphasis is used to extend the signal quality through the cable. 3.3.4 PLL CLOCK SYNTHESIZER The KSZ9021RL/RN generates 125MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from the external 25MHz crystal or reference clock. 3.4 Auto-Negotiation The KSZ9021RL/RN conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest. * * * * * * Priority 1: Priority 2: Priority 3: Priority 4: Priority 5: Priority 6: 1000Base-T, full-duplex 1000Base-T, half-duplex 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ9021RL/RN link partner is forced to bypass auto-negotiation for 10BaseT and 100Base-TX modes, then the KSZ9021RL/RN sets its operating mode by observing the input signal at its receiver. This is known as parallel detection, and allows the KSZ9021RL/RN to establish a link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart. 2009-2019 Microchip Technology Inc. DS00003050A-page 27 KSZ9021RL/RN FIGURE 3-3: AUTO NEGOTIATION FLOW CHART For 1000Base-T mode, auto-negotiation is required and always used to establish link. During 1000Base-T auto-negotiation, Master and Slave configuration is first resolved between link partners, and then link is established with the highest common capabilities between link partners. Auto-negotiation is enabled by default at power-up or after hardware reset. Afterwards, auto-negotiation can be enabled or disabled through register 0 bit 12. If auto-negotiation is disabled, then the speed is set by register 0 bits 6 and 13, and the duplex is set by register 0 bit 8. If the speed is changed on the fly, then the link goes down and either auto-negotiation or parallel detection will initiate until a common speed between KSZ9021RL/RN and its link partner is re-established for link. If link is already established, and there is no change of speed on the fly, then the changes will not take effect unless either auto-negotiation is restarted through register 0 bit 9, or a link down to link up transition occurs (i.e., disconnecting and reconnecting the cable). After auto-negotiation is completed, the link status is updated in register 1 and the link partner capabilities are updated in registers 5, 6, and 10. The auto-negotiation finite state machines employ interval timers to manage the auto-negotiation process. The duration of these timers under normal operating conditions are summarized in the following table. DS00003050A-page 28 2009-2019 Microchip Technology Inc. KSZ9021RL/RN TABLE 3-2: AUTO-NEGOTIATION TIMERS Auto-Negotiation Interval Timers Time Duration Transmit Burst interval 16ms Transmit Pulse interval 68s FLP detect minimum time 17.2s FLP detect maximum time 185s Receive minimum Burst interval 6.8ms Receive maximum Burst interval 112ms Data detect minimum interval 35.4s Data detect maximum interval 95s NLP test minimum interval 4.5ms NLP test maximum interval 30ms Link Loss time 52ms Break Link time 1480ms Parallel Detection wait time 830ms Link Enable wait time 1000ms 3.5 RGMII Interface The Reduced Gigabit Media Independent Interface (RGMII) is compliant with the RGMII Version 1.3 Specification. It provides a common interface between RGMII PHYs and MACs, and has the following key characteristics: * * * * Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII. All speeds (10Mbps, 100Mbps, and 1000Mbps) are supported at both half and full duplex. Data transmission and reception are independent and belong to separate signal groups. Transmit data and receive data are each 4-bit wide, a nibble. In RGMII operation, the RGMII pins function as follow: * The MAC sources the transmit reference clock, TXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps and 2.5MHz for 10Mbps. * The PHY recovers and sources the receive reference clock, RXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps and 2.5MHz for 10Mbps. * For 1000Base-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data, RXD[3:0], is clocked out on both edges of the recovered 125 MHz clock, RXC. * For 10Base-T/100Base-TX, the MAC will hold TX_CTL low until both PHY and MAC operate at the same speed. During the speed transition, the receive clock will be stretched on either positive or negative pulse to ensure that no clock glitch is presented to the MAC at any time. * TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These two RGMII control signals are valid at the falling clock edge. After power-up or reset, the KSZ9021RL/RN is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of the RGMII mode capability options. See Strapping Options section for available options. The KSZ9021RL/RN has the option to output a low jitter 125MHz reference clock on the CLK125_NDO pin. This clock provides a lower cost reference clock alternative for RGMII MACs that require a 125MHz crystal or oscillator. The 125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high. 2009-2019 Microchip Technology Inc. DS00003050A-page 29 KSZ9021RL/RN 3.5.1 RGMII SIGNAL DEFINITION The following table describes the RGMII signals. Refer to the RGMII Version 1.3 Specification for more detailed information. TABLE 3-3: RGMII Signal Name (per spec) RGMII SIGNAL DEFINITION RGMII Signal Name (per KSZ9021RL/RN) Pin Type (with respect to PHY) Pin Type (with respect to MAC) Description TXC GTX_CLK Input Output Transmit Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) TX_CTL TX_EN Input Output Transmit Control TXD[3:0] TXD[3:0] Input Output Transmit Data [3:0] RXC RX_CLK Output Input Receive Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) RX_CTL RX_DV Output Input Receive Control RXD[3:0] RXD[3:0] Output Input Receive Data [3:0] 3.5.2 RGMII SIGNAL DIAGRAM The KSZ9021RL/RN RGMII pin connections to the MAC are shown in the following figure. FIGURE 3-4: KSZ9021RL/RN RGMII INTERFACE KSZ9021RL/RN GTX_CLK DS00003050A-page 30 RGMII Ethernet MAC TXC TX_EN TX_CTL TXD[3:0] TXD[3:0] RX_CLK RXC RX_DV RX_CTL RXD[3:0] RXD[3:0] 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 3.5.3 RGMII PAD SKEW REGISTERS Pad skew registers are available for all RGMII pins (clocks, control signals, and data bits) to provide programming options to adjust or correct the timing relationship for each RGMII pin. Because RGMII is a source-synchronous bus interface, the timing relationship needs to be maintained only within the RGMII pin's respective timing group. * RGMII transmit timing group pins: * RGMII receive timing group pins: GTX_CLK, TX_EN, TXD[3:0] RX_CLK, RX_DV, RXD[3:0] The following three registers located at Extended Registers 260 (104h), 261 (105h), and 262 (106h) are provided for pad skew programming. TABLE 3-4: Address RGMII PAD SKEW REGISTERS Name Description Mode Default Register 260 (104h) - RGMII Clock and Control Pad Skew 260.15:12 rxc_pad_skew RGMII RXC PAD Skew Control (0.12ns/step) RW 0111 260.11:8 rxdv_pad_skew RGMII RX_CTL PAD Skew Control (0.12ns/step) RW 0111 260.7:4 txc_pad_skew RGMII TXC PAD Skew Control (0.12ns/step) RW 0111 260.3:0 txen_pad_skew RGMII TX_CTL PAD Skew Control (0.12ns/step) RW 0111 Register 261 (105h) - RGMII RX Data Pad Skew 261.15:12 rxd3_pad_skew RGMII RXD3 PAD Skew Control (0.12ns/step) RW 0111 261.11:8 rxd2_pad_skew RGMII RXD2 PAD Skew Control (0.12ns/step) RW 0111 261.7:4 rxd1_pad_skew RGMII RXD1 PAD Skew Control (0.12ns/step) RW 0111 261.3:0 rxd0_pad_skew RGMII RXD0 PAD Skew Control (0.12ns/step) RW 0111 Register 262 (106h) - RGMII TX Data Pad Skew 262.15:12 txd3_pad_skew RGMII TXD3 PAD Skew Control (0.12ns/step) RW 0111 262.11:8 txd2_pad_skew RGMII TXD2 PAD Skew Control (0.12ns/step) RW 0111 262.7:4 txd1_pad_skew RGMII TXD1 PAD Skew Control (0.12ns/step) RW 0111 262.3:0 txd0_pad_skew RGMII TXD0 PAD Skew Control (0.12ns/step) RW 0111 The RGMII clocks, control signals, and data bits have 4-bit skew settings. Each register bit is approximately a 0.12ns step change. A single-bit decrement decreases the delay by approximately 0.12ns, while a single-bit increment increases the delay by approximately 0.12ns. The following table lists the approximate absolute delay for each pad skew (value) setting. 2009-2019 Microchip Technology Inc. DS00003050A-page 31 KSZ9021RL/RN TABLE 3-5: ABSOLUTE DELAY FOR 4-BIT PAD SKEW SETTING Pad Skew (value) Delay (ns) 0000 -0.84 0001 -0.72 0010 -0.60 0011 -0.48 0100 -0.36 0101 -0.24 0110 -0.12 0111 No delay adjustment (default value) 1000 +0.12 1001 +0.24 1010 +0.36 1011 +0.48 1100 +0.60 1101 +0.72 1110 +0.84 1111 +0.96 When computing the RGMII timing relationships, delays along the entire data path must be aggregated to determine the total delay to be used for comparison between RGMII pins within their respective timing group. For the transmit data path, total delay includes MAC output delay, MAC-to-PHY PCB routing delay, and PHY (KSZ9021RL/RN) input delay and skew setting (if any). For the receive data path, the total delay includes PHY (KSZ9021RL/RN) output delay, PHYto-MAC PCB routing delay, and MAC input delay and skew setting (if any). After power-up or reset, the KSZ9021RL/RN defaults to the following timings at its RGMII I/O pins to support off-chip data-to-clock skew timing, as extended PCB trace run, according to the RGMII Version 1.3 Specification: * Transmit Inputs: * Receive outputs: GTX_CLK clock is in sync within 500ps of TX_EN and TXD[3:0] RX_CLK clock is in sync within 500ps of RX_DV and RXD[3:0] Alternatively, the KSZ9021RL/RN can be programmed to support RGMII v2.0 with the required data-to-clock skew implemented on-chip. If the delay is not implemented on the PCB and not programmed inside the MAC, the clock skew delay can be implemented via KSZ9021RL/RN registers 260 (104h), 261 (105h) and 262 (106h). These registers are accessed indirectly via the following registers: * Register 11 (Bh) * Register 12 (Ch) * Register 13 (Dh) // Extended Register - Control // Extended Register - Data Write // Extended Register - Data Read For the required data-to-clock delays: * For the RGMII transmit path, if there is no skew adjustment in the GMAC and also no skew on the PCB, set register 260 (104h) bits [7:0] to `F0' to delay the GTX_CLK and speed up TXEN. * For the RGMII receive path, if there is no skew adjustment in the GMAC and also no skew on the PCB, set register 260 (104h) bits [15:8] to `F0' to delay the RX_CLK and speed up RXDV. Additionally, RXD[3:0] and TXD[3:0] can be sped up by 0.84ns by setting the 4 register bits for each data bit to 0x0h in register 261 (105h) and register 262 (106h), respectively. Effectively, the 0.96ns clock delays and -0.84ns data delays (negative means speed up) will produce a combined datato-clock skew of 1.8ns. DS00003050A-page 32 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 3.5.4 RGMII IN-BAND STATUS The KSZ9021RL/RN can provide in-band status to the MAC during the inter-frame gap when RX_DV is de-asserted. RGMII in-band status is disabled by default. It is enabled by writing a one to extended register 256 (100h) bit 8. The in-band status is sent to the MAC using the RXD[3:0] data pins, and is described in the following table. TABLE 3-6: RGMII IN-BAND STATUS RX_DV 0 (valid only when RX_DV is low and register 256 bit 8 is set to 1) 3.6 RXD3 RXD[2:1] RXD0 Duplex Status 0 = half-duplex 1 = full-duplex RX_CLK clock speed 00 = 2.5MHz 01 = 25MHz 10 = 125MHz 11 = reserved Link Status 0 = Link down 1 = Link up MII Management (MIIM) Interface The KSZ9021RL/RN supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/ Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021RL/ RN. An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Further detail on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3 Specification. The MIIM interface consists of the following: * A physical connection that incorporates the clock line (MDC) and the data line (MDIO). * A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more KSZ9021RL/RN device. Each KSZ9021RL/RN device is assigned a PHY address between 1 and 7 by the PHYAD[2:0] strapping pins. * A 32 register address space to access the KSZ9021RL/RN IEEE Defined Registers, Vendor Specific Registers and Extended Registers. See Register Map section. The following table shows the MII Management frame format for the KSZ9021RL/RN. TABLE 3-7: MII MANAGEMENT FRAME FORMAT - FOR KSZ9021RL/RN Preamble Start of Frame Read/Write OP Code PHY Address Bits [4:0] REG Address Bits [4:0] TA Data Bits [15:0] Idle Read 32 1's 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1's 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z 3.7 Interrupt (INT_N) The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ9021RL/RN PHY register. Bits [15:8] of register 27 (1Bh) are the interrupt control bits to enable and disable the conditions for asserting the INT_N signal. Bits [7:0] of register 27 (1Bh) are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 27 (1Bh). Bit 14 of register 31 (1Fh) sets the interrupt level to active high or active low. The default is active low. The MII management bus option gives the MAC processor complete access to the KSZ9021RL/RN control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change. 2009-2019 Microchip Technology Inc. DS00003050A-page 33 KSZ9021RL/RN 3.8 LED Mode The KSZ9021RL/RN provides two programmable LED output pins, LED2 and LED1, which are configurable to support two LED modes. The LED mode is configured by the LED_MODE strap-in pin. It is latched at power-up/reset and is defined as follows: * Pull-up: * Pull-down: 3.8.1 Single LED Mode Tri-color Dual LED Mode SINGLE LED MODE In Single LED Mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown in the following table. TABLE 3-8: SINGLE LED MODE - PIN DEFINITION LED Pin Pin State LED2 LED1 3.8.2 LED Definition Link/Activity H OFF Link off L ON Link on (any speed) H OFF No Activity Toggle Blinking Activity (RX, TX) TRI-COLOR DUAL LED MODE In Tri-color Dual LED Mode, the Link and Activity status are indicated by the LED2 pin for 1000Base-T, by the LED1 pin for 100Base-TX, and by both LED2 and LED1 pin, working in conjunction, for 10Base-T. This is summarized in the following table. TABLE 3-9: TRI-COLOR DUAL LED MODE - PIN DEFINITION LED Pin (State) LED2 LED Pin (Definition) LED1 LED2 Link/Activity LED1 H H OFF OFF Link off L H ON OFF 1000 Link / No Activity Toggle H Blinking OFF 1000 Link / Activity (RX, TX) H L OFF ON 100 Link / No Activity H Toggle OFF Blinking 100 Link / Activity (RX, TX) L L ON ON 10 Link / No Activity Toggle Toggle Blinking Blinking 10 Link / Activity (RX, TX) Each LED output pin can directly drive a LED with a series resistor (typically 220 to 470). For activity indication, the LED output toggles at approximately 12.5Hz (80ms) to ensure visibility to the human eye. DS00003050A-page 34 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 3.9 NAND Tree Support The KSZ9021RL/RN provides parametric NAND tree support for fault detection between chip I/Os and board. NAND tree mode is enabled at power-up/reset with the MODE[3:0] strap-in pins set to 0100. The following tables list the NAND tree pin order for KSZ9021RL and KSZ9021RN. TABLE 3-10: NAND TREE TEST PIN ORDER - FOR KSZ9021RL Pin Description LED2 Input LED1 Input TXD0 Input TXD1 Input TXD2 Input TXD3 Input TX_ER Input GTX_CLK Input TX_EN Input RX_DV Input RX_ER Input RX_CLK Input CRS Input COL Input INT_N Input MDC Input MDIO Input CLK125_NDO Output TABLE 3-11: NAND TREE TEST PIN ORDER - FOR KSZ9021RN Pin Description LED2 Input LED1 Input TXD0 Input TXD1 Input TXD2 Input TXD3 Input GTX_CLK Input TX_EN Input RX_DV Input RX_CLK Input INT_N Input MDC Input MDIO Input CLK125_NDO Output 2009-2019 Microchip Technology Inc. DS00003050A-page 35 KSZ9021RL/RN 3.10 Power Management The KSZ9021RL/RN offers the following power management modes: 3.10.1 POWER SAVING MODE This mode is a KSZ9021RL/RN green feature to reduce power consumption when the cable is unplugged. It is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). 3.10.2 SOFTWARE POWER DOWN MODE This mode is used to power down the KSZ9021RL/RN device when it is not in use after power-up. Power down mode is enabled by writing a one to register 0h bit 11. In the power down state, the KSZ9021RL/RN disables all internal functions, except for the MII management interface. The KSZ9021RL/RN exits power down mode after writing a zero to register 0h bit 11. 3.10.3 CHIP POWER DOWN MODE This mode provides the lowest power state for the KSZ9021RL/RN when it is not in use and is mounted on the board. Chip power down mode is enabled at power-up/reset with the MODE[3:0] strap-in pins set to 0111. The KSZ9021RL/ RN exits chip power down mode when a hardware reset is applied to the RESET_N pin with the MODE[3:0] strap-in pins set to an operating mode other than chip power down mode. DS00003050A-page 36 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 4.0 REGISTER DESCRIPTION 4.1 Register Map The IEEE 802.3 Specification provides a 32 register address space for the PHY. Registers 0 thru 15 are standard PHY registers, defined per the specification. Registers 16 thru 31 are vendor specific registers. The KSZ9021RL/RN uses the IEEE provided register space for IEEE Defined Registers and Vendor Specific Registers, and uses the following registers to access Extended Registers: * Register 11 (Bh) for Extended Register - Control * Register 12 (Ch) for Extended Register - Data Write * Register 13 (Dh) for Extended Register - Data Read Examples: * Extended Register Read 1. Write register 11 (Bh) with 0103h 2. Read register 13 (Dh) // Read from Operation Mode Strap Status Register // Set register 259 (103h) for read // Read register value * Extended Register Write 1. Write register 11 (Bh) with 8102h 2. Write register 12 (Ch) with 0010h // Write to Operation Mode Strap Override Register // Set register 258 (102h) for write // Write 0010h value to register to set NAND Tree mode Register Number (Hex) Description IEEE Defined Registers 0 (0h) Basic Control 1 (1h) Basic Status 2 (2h) PHY Identifier 1 3 (3h) PHY Identifier 2 4 (4h) Auto-Negotiation Advertisement 5 (5h) Auto-Negotiation Link Partner Ability 6 (6h) Auto-Negotiation Expansion 7 (7h) Auto-Negotiation Next Page 8 (8h) Auto-Negotiation Link Partner Next Page Ability 9 (9h) 1000Base-T Control 10 (Ah) 1000Base-T Status 11 (Bh) Extended Register - Control 12 (Ch) Extended Register - Data Write 13 (Dh) Extended Register - Data Read 14 (Eh) Reserved 15 (Fh) Extended - MII Status Vendor Specific Registers 16 (10h) Reserved 17 (11h) Remote Loopback, LED Mode 18 (12h) LinkMD(R) - Cable Diagnostic 19 (13h) Digital PMA/PCS Status 20 (14h) Reserved 21 (15h) RXER Counter 22 (16h) - 26 (1Ah) Reserved 27 (1Bh) Interrupt Control/Status 2009-2019 Microchip Technology Inc. DS00003050A-page 37 KSZ9021RL/RN Register Number (Hex) Description 28 (1Ch) Digital Debug Control 1 29 (1Dh) - 30 (1Eh) Reserved 31 (1Fh) PHY Control Extended Registers 256 (100h) Common Control 257 (101h) Strap Status 258 (102h) Operation Mode Strap Override 259 (103h) Operation Mode Strap Status 260 (104h) RGMII Clock and Control Pad Skew 261 (105h) RGMII RX Data Pad Skew 262 (106h) RGMII TX Data Pad Skew 263 (107h) Analog Test Register 4.1.1 Address IEEE DEFINED REGISTERS Name Description Mode (Note 1) Default Register 0 (0h) - Basic Control 0.15 Reset 1 = Software PHY reset 0 = Normal operation RW/SC 0 This bit is self-cleared after a `1' is written to it. 0.14 Loop-back 1 = Loop-back mode 0 = Normal operation RW 0 0.13 Speed Select (LSB) [0.6, 0.13] RW Hardware Setting RW 1 [1,1] = Reserved [1,0] = 1000Mbps [0,1] = 100Mbps [0,0] = 10Mbps This bit is ignored if auto-negotiation is enabled (register 0.12 = 1). 0.12 Auto-Negotia- 1 = Enable auto-negotiation process tion Enable 0 = Disable auto-negotiation process If enabled, auto-negotiation result overrides settings in register 0.13, 0.8 and 0.6. 0.11 Power Down 1 = Power down mode 0 = Normal operation RW 0 0.10 Isolate 1 = Electrical isolation of PHY from RGMII 0 = Normal operation RW 0 0.9 Restart AutoNegotiation 1 = Restart auto-negotiation process 0 = Normal operation. RW/SC 0 RW Hardware Setting This bit is self-cleared after a `1' is written to it. 0.8 Duplex Mode DS00003050A-page 38 1 = Full-duplex 0 = Half-duplex 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name 0.7 Reserved 0.6 Speed Select (MSB) Description [0.6, 0.13] Mode (Note 1) Default RW 0 RW 0 RO 00_0000 [1,1] = Reserved [1,0] = 1000Mbps [0,1] = 100Mbps [0,0] = 10Mbps This bit is ignored if auto-negotiation is enabled (register 0.12 = 1). 0.5:0 Reserved Register 1 (1h) - Basic Status 1.15 100Base-T4 1 = T4 capable 0 = Not T4 capable RO 0 1.14 100Base-TX Full Duplex 1 = Capable of 100Mbps full-duplex 0 = Not capable of 100Mbps full-duplex RO 1 1.13 100Base-TX Half Duplex 1 = Capable of 100Mbps half-duplex 0 = Not capable of 100Mbps half-duplex RO 1 1.12 10Base-T Full Duplex 1 = Capable of 10Mbps full-duplex 0 = Not capable of 10Mbps full-duplex RO 1 1.11 10Base-T Half Duplex 1 = Capable of 10Mbps half-duplex 0 = Not capable of 10Mbps half-duplex RO 1 RO 00 1.10:9 Reserved 1.8 Extended Sta- 1 = Extended Status Information in Reg. 15. RO tus 0 = No Extended Status Information in Reg. 15. 1 1.7 Reserved RO 0 1.6 No Preamble RO 1 1.5 Auto-Negotia- 1 = Auto-negotiation process completed RO tion Complete 0 = Auto-negotiation process not completed 0 1.4 Remote Fault 0 1.3 Auto-Negotia- 1 = Capable to perform auto-negotiation RO tion Ability 0 = Not capable to perform auto-negotiation 1 1.2 Link Status RO/LL 0 1.1 Jabber Detect 1 = Jabber detected 0 = Jabber not detected (default is low) RO/LH 0 1.0 Extended Capability RO 1 1 = Preamble suppression 0 = Normal preamble 1 = Remote fault 0 = No remote fault 1 = Link is up 0 = Link is down 1 = Supports extended capabilities registers RO/LH Register 2 (2h) - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the RO Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) 0022h Register 3 (3h) - PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) 2009-2019 Microchip Technology Inc. RO 0001_01 DS00003050A-page 39 KSZ9021RL/RN Address Name Description Mode (Note 1) Default 3.9:4 Model Number Six bit manufacturer's model number RO 10_0001 3.3:0 Revision Number Four bit manufacturer's revision number RO Indicates silicon revision RW 0 RO 0 RW 0 RO 0 RW 00 Register 4 (4h) - Auto-Negotiation Advertisement 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 4.11:10 Pause 1 = Next page capable 0 = No next page capability. 1 = Remote fault supported 0 = No remote fault [4.11, 4.10] [0,0] = No PAUSE [1,0] = Asymmetric PAUSE (link partner) [0,1] = Symmetric PAUSE [1,1] = Symmetric & Asymmetric PAUSE (local device) 4.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 4.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RW 1 4.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RW 1 4.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RW 1 4.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001 Register 5 (5h) - Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = Next page capable 0 = No next page capability RO 0 5.14 Acknowledge 1 = Link code word received from partner 0 = Link code word not yet received RO 0 5.13 Remote Fault 1 = Remote fault detected 0 = No remote fault RO 0 5.12 Reserved RO 0 5.11:10 Pause RW 00 [5.11, 5.10] [0,0] = No PAUSE [1,0] = Asymmetric PAUSE (link partner) [0,1] = Symmetric PAUSE [1,1] = Symmetric & Asymmetric PAUSE (local device) 5.9 100Base-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100Base-TX Full-Duplex 1 = 100Mbps full-duplex capable 0 = No 100Mbps full-duplex capability RO 0 DS00003050A-page 40 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name Description Mode (Note 1) Default 5.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 0 = No 100Mbps half-duplex capability RO 0 5.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 0 = No 10Mbps full-duplex capability RO 0 5.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 0 = No 10Mbps half-duplex capability RO 0 5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0000 Register 6 (6h) - Auto-Negotiation Expansion 6.15:5 Reserved RO 0000_0000_000 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection 0 = No fault detected by parallel detection. RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0 6.2 Next Page Able 1 = Local device has next page capability 0 = Local device does not have next page capability RO 1 6.1 Page Received 1 = New page received 0 = New page not received yet RO/LH 0 6.0 1 = Link partner has auto-negotiation capa- RO Link Partner bility Auto-Negotiation Able 0 = Link partner does not have auto-negotiation capability 0 Register 7 (7h) - Auto-Negotiation Next Page 7.15 Next Page 7.14 Reserved 7.13 Message Page 7.12 1 = Additional next page(s) will follow 0 = Last page RW 0 RO 0 1 = Message page 0 = Unformatted page RW 1 Acknowledge2 1 = Will comply with message 0 = Cannot comply with message RW 0 7.11 Toggle 1 = Previous value of the transmitted link code word equaled logic one 0 = Logic zero RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 Register 8 (8h) - Auto-Negotiation Link Partner Next Page Ability 8.15 Next Page 1 = Additional Next Page(s) will follow 0 = Last page RO 0 8.14 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word RO 0 8.13 Message Page 1 = Message page 0 = Unformatted page RO 0 8.12 Acknowledge2 1 = Able to act on the information 0 = Not able to act on the information RO 0 8.11 Toggle 1 = Previous value of transmitted link code word equal to logic zero 0 = Previous value of transmitted link code word equal to logic one RO 0 2009-2019 Microchip Technology Inc. DS00003050A-page 41 KSZ9021RL/RN Address 8.10:0 Name Mode (Note 1) Description Message Field Default RO 000_0000_0000 RW 000 Register 9 (9h) - 1000Base-T Control 9:15:13 Test Mode Bits Transmitter test mode operations [9.15:13] Mode [000] Normal Operation [001] Test mode 1 waveform test [010] Test mode 2 -Transmit jitter test in Master mode [011] Test mode 3 -Transmit jitter test in Slave mode [100] Test mode 4 -Transmitter distortion test [101] Reserved, operations not identified [110] Reserved, operations not identified [111] Reserved, operations not identified -Transmit 9.12 MASTERSLAVE Manual Config Enable 1 = Enable MASTER-SLAVE Manual configuration value 0 = Disable MASTER-SLAVE Manual configuration value RW 0 9.11 MASTERSLAVE Manual Config Value 1 = Configure PHY as MASTER during RW MASTER-SLAVE negotiation 0 = Configure PHY as SLAVE during MASTER-SLAVE negotiation 0 This bit is ignored if MASTER-SLAVE Manual Config is disabled (register 9.12 = 0). 9.10 Port Type 1 = Indicate the preference to operate as multiport device (MASTER) 0 = Indicate the preference to operate as single-port device (SLAVE) RW 0 This bit is valid only if the MASTER-SLAVE Manual Config Enable bit is disabled (register 9.12 = 0). 9.9 1000Base-T Full-Duplex 1 = Advertise PHY is 1000Base-T fullduplex capable 0 = Advertise PHY is not 1000Base-T fullduplex capable RW 1 9.8 1000Base-T Half-Duplex 1 = Advertise PHY is 1000Base-T halfduplex capable 0 = Advertise PHY is not 1000Base-T halfduplex capable RW Hardware Setting 9.7:0 Reserved Write as 0, ignore on read RO DS00003050A-page 42 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name Description Mode (Note 1) Default Register 10 (Ah) - 1000Base-T Status 10.15 MASTERSLAVE configuration fault 1 = MASTER-SLAVE configuration fault RO/LH/ detected SC 0 = No MASTER-SLAVE configuration fault detected 0 10.14 MASTERSLAVE configuration resolution 1 = Local PHY configuration resolved to MASTER 0 = Local PHY configuration resolved to SLAVE RO 0 10.13 Local 1 = Local Receiver OK (loc_rcvr_status = 1) RO Receiver Sta- 0 = Local Receiver not OK (loc_rcvr_status tus = 0) 0 10.12 Remote 1 = Remote Receiver OK (rem_rcvr_status RO Receiver Sta= 1) tus 0 = Remote Receiver not OK (rem_rcvr_status = 0) 0 10.11 LP 1000T FD 1 = Link Partner is capable of 1000Base-T full-duplex 0 = Link Partner is not capable of 1000Base-T full-duplex RO 0 A.10 LP 1000T HD 1 = Link Partner is capable of 1000Base-T half-duplex 0 = Link Partner is not capable of 1000Base-T half-duplex RO 0 10.9:8 Reserved 10.7:0 Idle Error Count Cumulative count of errors detected when receiver is receiving idles and PMA_TXMODE.indicate = SEND_N. RO 00 RO/SC 0000_0000 RW 0 The counter is incremented every symbol period that rxerror_status = ERROR. Register 11 (Bh) - Extended Register - Control 11.15 Extended Register - read/write select 1 = Write Extended Register 0 = Read Extended Register 11.14:9 Reserved RW 000_000 11.8 Extended Register - page Select page for Extended Register RW 0 11.7:0 Extended Register - address Select Extended Register Address RW 0000_0000 RW 0000_0000_0000_0000 RO 0000_0000_0000_0000 Register 12 (Ch) - Extended Register - Data Write 12.15:0 Extended Register - write 16-bit value to write to Extend Register Address in register 11 (Bh) bits [7:0] Register 13 (Dh) - Extended Register - Data Read 13.15:0 Extended Register - read 16-bit value read from Extend Register Address in register 11 (Bh) bits [7:0] 2009-2019 Microchip Technology Inc. DS00003050A-page 43 KSZ9021RL/RN Address Name Description Mode (Note 1) Default Register 15 (Fh) - Extended - MII Status 15.15 1000Base-X Full-duplex 1 = PHY able to perform 1000Base-X full-duplex 0 = PHY not able to perform 1000Base-X full-duplex RO 0 15.14 1000Base-X Half-duplex 1 = PHY able to perform 1000Base-X half-duplex 0 = PHY not able to perform 1000Base-X half-duplex RO 0 15.13 1000Base-T Full-duplex 1 = PHY able to perform 1000Base-T fullduplex 1000BASE-X 0 = PHY not able to perform 1000Base-T full-duplex RO 1 15.12 1000Base-T Half-duplex 1 = PHY able to perform 1000Base-T half-duplex 0 = PHY not able to perform 1000Base-T half-duplex RO 1 15.11:0 Reserved Ignore when read RO - Note 1: RW = Read/Write. RO = Read only. SC = Self-cleared. LH = Latch high. LL = Latch low. 4.1.2 Address VENDOR SPECIFIC REGISTERS Name Description Mode (Note 1) Default Register 17 (11h) - Remote Loopback, LED Mode 17.15:9 Reserved RW 0000_001 17.8 Remote Loop- 1 = Enable Remote Loopback back 0 = Disable Remote Loopback RW 0 17.7:6 Reserved RW 11 RW 11 RW 0 17.5:4 Reserved 17.3 LED Test Enable 17.2:1 Reserved RW 00 17.0 Reserved RO 0 RW/SC 0 1 = Enable LED test mode 0 = Disable LED test mode Register 18 (12h) - LinkMD(R) - Cable Diagnostic 18.15 Reserved 18.14:8 Reserved RW 000_0000 18.7:0 Reserved RO 0000_0000 DS00003050A-page 44 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name Description Mode (Note 1) Default Register 19 (13h) - Digital PMA/PCS Status 19.15:3 Reserved 19.2 1000Base-T Link Status 1000 Base-T Link Status RO/LH 0000_0000_0000_0 RO 0 RO 0 RO 0 RO/RC 0000_0000_0000_0000 RW 0 1 = Link status is OK 0 = Link status is not OK 19.1 100Base-TX Link Status 100 Base-TX Link Status 1 = Link status is OK 0 = Link status is not OK 19.0 Reserved Register 21 (15h) - RXER Counter 21.15:0 RXER Counter Receive error counter for Symbol Error frames Register 27 (1Bh) - Interrupt Control/Status 27.15 Jabber Interrupt Enable 1 = Enable Jabber Interrupt 0 = Disable Jabber Interrupt 27.14 Receive Error 1 = Enable Receive Error Interrupt Interrupt 0 = Disable Receive Error Interrupt Enable RW 0 27.13 Page Received Interrupt Enable 1 = Enable Page Received Interrupt 0 = Disable Page Received Interrupt RW 0 27.12 Parallel Detect Fault Interrupt Enable 1 = Enable Parallel Detect Fault Interrupt 0 = Disable Parallel Detect Fault Interrupt RW 0 27.11 Link Partner Acknowledge Interrupt Enable 1 = Enable Link Partner Acknowledge Inter- RW rupt 0 = Disable Link Partner Acknowledge Interrupt 0 27.10 Link Down Interrupt Enable 1 = Enable Link Down Interrupt 0 = Disable Link Down Interrupt RW 0 27.9 Remote Fault Interrupt Enable 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt RW 0 27.8 Link Up Interrupt Enable 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt RW 0 27.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occurred RO/RC 0 27.6 Receive Error Interrupt 1 = Receive Error occurred 0 = Receive Error did not occurred RO/RC 0 27.5 Page Receive 1 = Page Receive occurred Interrupt 0 = Page Receive did not occurred RO/RC 0 27.4 Parallel Detect Fault Interrupt RO/RC 0 1 = Parallel Detect Fault occurred 0 = Parallel Detect Fault did not occurred 2009-2019 Microchip Technology Inc. DS00003050A-page 45 KSZ9021RL/RN Address Name Description Mode (Note 1) Default 27.3 Link Partner Acknowledge Interrupt 1 = Link Partner Acknowledge occurred 0 = Link Partner Acknowledge did not occurred RO/RC 0 27.2 Link Down Interrupt 1 = Link Down occurred 0 = Link Down did not occurred RO/RC 0 27.1 Remote Fault Interrupt 1 = Remote Fault occurred 0 = Remote Fault did not occurred RO/RC 0 27.0 Link Up Interrupt 1 = Link Up occurred 0 = Link Up did not occurred RO/RC 0 RW 0000_0000 RW 0 RW 0 RW 00_000 RW 0 Register 28 (1Ch) - Digital Debug Control 1 28.15:8 Reserved 28.7 mdi_set mdi_set has no function when swapoff (reg28.6) is de-asserted. 1 = When swapoff is asserted, if mdi_set is asserted, chip will operate at MDI mode. 0 = When swapoff is asserted, if mdi_set is de-asserted, chip will operate at MDI-X mode. 28.6 swapoff 28.5:1 Reserved 28.0 PCS Loopback 1 = Disable auto crossover function 0 = Enable auto crossover function 1 = Enable 10Base-T and 100Base-TX Loopback for register 0h bit 14. 0 = normal function Register 31 (1Fh) - PHY Control 31.15 Reserved RW 0 31.14 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 31.13:12 Reserved RW 00 31.11:10 Reserved RO/LH/ RC 00 31.9 Enable Jabber RW 1 1 = Enable jabber counter 0 = Disable jabber counter 31.8:7 Reserved RW 00 31.6 Speed status 1000Base-T 1 = Indicate chip final speed status at 1000Base-T RO 0 31.5 Speed status 100Base-TX 1 = Indicate chip final speed status at 100Base-TX RO 0 31.4 Speed status 10Base-T 1 = Indicate chip final speed status at 10Base-T RO 0 31.3 Duplex status Indicate chip duplex status RO 0 RO 0 1 = Full-duplex 0 = Half-duplex 31.2 1000Base-T Mater/Slave status DS00003050A-page 46 1 = Indicate 1000Base-T Master mode 0 = Indicate 1000Base-T Slave mode 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name Description Mode (Note 1) Default 31.1 Software Reset 1 = Reset chip, except all registers 0 = Disable reset RW 0 31.0 Link Status Check Fail 1 = Fail 0 = Not Failing RO 0 Note 1: RW = Read/Write. RC = Read-cleared RO = Read only. SC = Self-cleared. LH = Latch high. 4.1.3 Address EXTENDED REGISTERS Name Description Mode (Note 1) Default Register 256 (100h) - Common Control 256.15:9 Reserved 256.8 RGMII Inband PHY Status 256.7:0 Reserved 1 = Enable 0 = Disable RW 0000_000 RW 0 RW Register 257 (101h) - Strap Status 257.15:6 Reserved RO 257.5 CLK125_EN status 1 = CLK125_EN strap-in is enabled 0 = CLK125_EN strap-in is disabled RO 257.4:0 PHYAD[4:0] status Strapped-in value for PHY Address RO Register 258 (102h) - Operation Mode Strap Override 258.15 RGMII all capabilities override 1 = Override strap-in for RGMII advertise all RW capabilities 258.14 RGMII no 1000BT_HD override 1 = Override strap-in for RGMII advertise all RW capabilities except 1000Base-T halfduplex 258.13 RGMII 1 = Override strap-in for RGMII advertise 1000BT_H/FD 1000Base-T full and half-duplex only only override RW 258.12 RGMII 1000BT_FD only override RW 258.11:8 Reserved 258.7 Tri-state all digital I/Os 258.6:5 Reserved 258.4 NAND Tree override 258.3:0 Reserved 1 = Override strap-in for RGMII advertise 1000Base-T full-duplex only RW 1 = Tri-state all digital I/Os for further power RW saving during software power down 0 RW 1 = Override strap-in for NAND Tree mode 2009-2019 Microchip Technology Inc. RW RW DS00003050A-page 47 KSZ9021RL/RN Address Name Description Mode (Note 1) Default Register 259 (103h) - Operation Mode Strap Status 259.15 RGMII all 1 = Strap to RGMII advertise all capabilities RO capabilities strap-in status 259.14 RGMII no 1 = Strap to RGMII advertise all capabilities RO 1000BT_HD except 1000Base-T half-duplex strap-in status 259.13 RGMII only 1 = Strap to RGMII advertise 1000Base-T 1000BT_H/FD full and half-duplex only strap-in status RO 259.12 RGMII only 1 = Strap to RGMII advertise 1000Base-T 1000BT_FD full-duplex only strap-in status RO 259.11:5 Reserved RO 259.4 NAND Tree 1 = Strap to NAND Tree mode strap-in status RO 259.3:0 Reserved RO Register 260 (104h) - RGMII Clock and Control Pad Skew 260.15:12 rxc_pad_skew RGMII RXC PAD Skew Control (0.12ns/ step) RW 0111 260.11:8 rxdv_pad_skew RW 0111 260.7:4 txc_pad_skew RGMII TXC PAD Skew Control (0.12ns/ step) RW 0111 260.3:0 txen_pad_ske RGMII TX_CTL PAD Skew Control (0.12ns/ RW w step) 0111 RGMII RX_CTL PAD Skew Control (0.12ns/step) Register 261 (105h) - RGMII RX Data Pad Skew 261.15:12 rxd3_pad_ske RGMII RXD3 PAD Skew Control (0.12ns/ w step) RW 0111 261.11:8 rxd2_pad_ske RGMII RXD2 PAD Skew Control (0.12ns/ w step) RW 0111 261.7:4 rxd1_pad_ske RGMII RXD1 PAD Skew Control (0.12ns/ w step) RW 0111 261.3:0 rxd0_pad_ske RGMII RXD0 PAD Skew Control (0.12ns/ w step) RW 0111 Register 262 (106h) - RGMII TX Data Pad Skew 262.15:12 txd3_pad_ske RGMII TXD3 PAD Skew Control (0.12ns/ w step) RW 0111 262.11:8 txd2_pad_ske RGMII TXD2 PAD Skew Control (0.12ns/ w step) RW 0111 262.7:4 txd1_pad_ske RGMII TXD1 PAD Skew Control (0.12ns/ w step) RW 0111 262.3:0 txd0_pad_ske RGMII TXD0 PAD Skew Control (0.12ns/ w step) RW 0111 DS00003050A-page 48 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Address Name Description Mode (Note 1) Default Register 263 (107h) - Analog Test Register 263.15 LDO disable 263.14:9 Reserved 263.8 Low frequency oscillator mode 1 = LDO controller disable 0 = LDO controller enable 1 = Low frequency oscillator mode enable 0 = Low frequency oscillator mode disable RW 0 RW 000_000 RW 0 RW 0000_0000 Use for further power saving during software power down. 263.7:0 Reserved Note 1: RW = Read/Write. RO = Read only. 2009-2019 Microchip Technology Inc. DS00003050A-page 49 KSZ9021RL/RN 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings (See Note 1) Supply Voltage (DVDDL, AVDDL, AVDDL_PLL) ............................................................................................................. -0.5V to +1.8V (AVDDH)................................................................................................................................................. -0.5V to +5.0V (DVDDH) ................................................................................................................................................ -0.5V to +5.0V Input Voltage (all inputs)............................................................................................................................ -0.5V to +5.0V Output Voltage (all outputs)....................................................................................................................... -0.5V to +5.0V Lead Temperature (soldering, 10s) ......................................................................................................................... 260C Storage Temperature (Ts)....................................................................................................................... -55C to +150C 5.2 Operating Ratings (See Note 2) Supply Voltage (DVDDL, AVDDL, AVDDL_PLL) ..................................................................................................... +1.140V to +1.260V (AVDDH)......................................................................................................................................... +3.135V to +3.465V (DVDDH @ 3.3V) ........................................................................................................................... +3.135V to +3.465V (DVDDH @ 2.5V) ........................................................................................................................... +2.375V to +2.625V Ambient Temperature (TA Commercial: KSZ9021RL/RN)...........................................................................................................0C to +70C (TA Industrial: KSZ9021RLI/RNI) ......................................................................................................... -40C to +85C Maximum Junction Temperature (TJ Max)............................................................................................................... 125C Thermal Resistance (JA).................................................................................................................................31.85C/W Thermal Resistance (JC)...................................................................................................................................8.07C/W 5.3 Electrical Characteristics (See Note 3) Symbol Parameter Condition Min Typ Max Units Supply Current - Core / Digital I/Os ICORE 1.2V total of: 1000Base-T Link-up (no traffic) DVDDL (1.2V digital core) + 1000Base-T Full-duplex @ 100% utilizaAVDDL (1.2V analog core) + tion AVDDL_PLL (1.2V for PLL) 100Base-TX Link-up (no traffic) 528 mA 563 mA 158 mA 158 mA 7 mA 10Base-T Full-duplex @ 100% utilization 7 mA Power Saving Mode (cable unplugged) 15 mA Software Power Down Mode (register 0.11 =1) 1.3 mA Chip Power Down Mode (strap-in pins MODE[3:0] = 0111) 1.3 mA 100Base-TX Full-duplex @ 100% utilization 10Base-T Link-up (no traffic) DS00003050A-page 50 2009-2019 Microchip Technology Inc. KSZ9021RL/RN Symbol IDVDDH_2.5 IDVDDH_3.3 Parameter Condition Min Typ Max Units 2.5V for digital I/Os 1000Base-T Link-up (no traffic) 13 mA (RGMII operating @ 2.5V) 1000Base-T Full-duplex @ 100% utilization 37 mA 100Base-TX Link-up (no traffic) 4 mA 100Base-TX Full-duplex @ 100% utilization 9 mA 10Base-T Link-up (no traffic) 2 mA 10Base-T Full-duplex @ 100% utilization 5 mA Power Saving Mode (cable unplugged) 7 mA Software Power Down Mode (register 0.11 =1) 3 mA Chip Power Down Mode (strap-in pins MODE[3:0] = 0111) 1 mA 3.3V for digital I/Os 1000Base-T Link-up (no traffic) 20 mA (RGMII operating @ 3.3V) 1000Base-T Full-duplex @ 100% utilization 58 mA 100Base-TX Link-up (no traffic) 11 mA 100Base-TX Full-duplex @ 100% utilization 15 mA 10Base-T Link-up (no traffic) 5 mA 10Base-T Full-duplex @ 100% utilization 11 mA Power Saving Mode (cable unplugged) 9 mA Software Power Down Mode (register 0.11 =1) 7 mA Chip Power Down Mode (strap-in pins MODE[3:0] = 0111) 1 mA Supply Current - Transceiver (equivalent to current draw through external transformer center taps for PHY transceivers with current-mode transmit drivers) IAVDDH 3.3V for transceiver 1000Base-T Link-up (no traffic) 75 mA 1000Base-T Full-duplex @ 100% utilization 75 mA 100Base-TX Link-up (no traffic) 29 mA 100Base-TX Full-duplex @ 100% utilization 29 mA 10Base-T Link-up (no traffic) 35 mA 10Base-T Full-duplex @ 100% utilization 43 mA Power Saving Mode (cable unplugged) 36 mA Software Power Down Mode (register 0.11 =1) 2 mA Chip Power Down Mode (strap-in pins MODE[3:0] = 0111) 1 mA TTL Inputs VIH Input High Voltage VIL Input Low Voltage IIN Input Current 2.0 VIN = GND ~ VDDIO V -10 0.8 V 10 A 0.4 V TTL Outputs VOH Output High Voltage IOH = -4mA VOL Output Low Voltage IOL = 4mA 2009-2019 Microchip Technology Inc. 2.4 V DS00003050A-page 51 KSZ9021RL/RN Symbol |Ioz| Parameter Condition Min Typ Output Tri-State Leakage Max Units 10 A 1.05 V 2 % 100Base-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Output Voltage 100 termination across differential output VIMB Output Voltage Imbalance 100 termination across differential output tr, tf Rise/Fall Time 3 5 ns Rise/Fall Time Imbalance 0 0.5 ns 0.25 ns 5 % 1.4 ns 2.8 V 0.95 Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET R(ISET) = 4.99k Output Jitter Peak-to-peak 0.535 0.7 V 10Base-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Output Voltage 100 termination across differential output Jitter Added Peak-to-peak Harmonic Rejection Transmit all-one signal sequence 2.2 3.5 ns -31 dB 400 mV 10Base-T Receive VSQ Squelch Threshold 5MHz square wave 300 Note 1: Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 2: The device is not guaranteed to function outside its operating rating. 3: TA = 25C. Specification is for packaged product only. DS00003050A-page 52 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 6.0 TIMING DIAGRAMS 6.1 RGMII Timing The KSZ9021RL/RN RGMII timing conforms to the timing requirements per the RGMII Version 1.3 Specification. FIGURE 6-1: TABLE 6-1: RGMII V1.3 SPECIFICATION (FIGURE 2 - MULTIPLEXING AND TIMING DIAGRAM) RGMII V1.3 SPECIFICATION (TIMING SPECIFICS FROM Table 6-2) Timing Parameter Description TskewT Data to Clock output Skew (at Transmitter) TskewR Data to Clock input Skew (at Receiver) Tcyc (1000Base-T) Clock Cycle Duration for 1000Base-T Min Typ -500 1 7.2 8 Max Unit 500 ps 2.6 ns 8.8 ns Tcyc (100Base-TX) Clock Cycle Duration for 100Base-TX 36 40 44 ns Tcyc (10Base-T) Clock Cycle Duration for 10Base-T 360 400 440 ns Accounting for TskewT, the TskewR specification in the above table requires the PCB board design to incorporate clock routing for TXC and RXC with an additional trace delay of greater than 1.5ns and less than 2.1ns for 1000Base-T. For 10Base-T/100Base-TX, the maximum delay is much greater than the 2.1ns for 1000Base-T, and thus is not specified. Alternatively, the KSZ9021RL/RN can be programmed to support RGMII v2.0 with the required data-to-clock skew implemented on-chip. If the delay is not implemented on the PCB and not programmed inside the MAC, the clock skew delay can be implemented via KSZ9021RL/RN registers 260 (104h), 261 (105h) and 262 (106h). See RGMII Pad Skew Registers section. 2009-2019 Microchip Technology Inc. DS00003050A-page 53 KSZ9021RL/RN 6.2 Auto-Negotiation Timing FIGURE 6-2: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING Auto-Negotiation Fast Link Pulse (FLP) Timing FLP Burst FLP Burst TX+/TX- tFLPW tBTB TX+/TX- Clock Pulse Data Pulse tPW tPW Data Pulse Clock Pulse tCTD tCTC TABLE 6-2: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS Timing Parameter Description Min Typ Max Units 8 16 24 ms tBTB FLP Burst to FLP Burst tFLPW FLP Burst width tPW Clock/Data Pulse width tCTD Clock Pulse to Data Pulse 55.5 64 69.5 s tCTC Clock Pulse to Clock Pulse 111 128 139 s Number of Clock/Data Pulse per FLP Burst 17 DS00003050A-page 54 2 ms 100 ns 33 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 6.3 MDC/MDIO Timing FIGURE 6-3: MDC/MDIO TIMING tP MDC tMD1 tMD2 Valid Data MDIO (PHY input) Valid Data tMD3 Valid Data MDIO (PHY output) TABLE 6-3: MDC/MDIO TIMING PARAMETERS Timing Parameter Description Min Typ Unit tP MDC period t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 tMD2 MDIO (PHY input) hold from rising edge of MDC 10 ns tMD3 MDIO (PHY output) delay from rising edge of MDC 0 ns 2009-2019 Microchip Technology Inc. 400 Max ns ns DS00003050A-page 55 KSZ9021RL/RN 6.4 Reset Timing The recommended KSZ9021RL/RN power-up reset timing is summarized in the following figure and table. FIGURE 6-4: RESET TIMING Supply Voltage tsr RESET_N TABLE 6-4: RESET TIMING PARAMETERS Parameter Description tsr Min Stable supply voltage to reset high 10 Max Units ms After the de-assertion of reset, it is recommended to wait a minimum of 100s before starting programming on the MIIM (MDC/MDIO) Interface. 6.5 Reset Circuit The following reset circuit is recommended for powering up the KSZ9021RL/RN if reset is triggered by the power supply. TABLE 6-5: RECOMMENDED RESET CIRCUIT DVDDH D1: 1N4148 KSZ9021RL/RN D1 R 10K RESET_N C 10uF DS00003050A-page 56 2009-2019 Microchip Technology Inc. KSZ9021RL/RN The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ9021RL/RN device. The RST_OUT_n from CPU/FPGA provides the warm reset after power up. FIGURE 6-5: RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET OUTPUT DVDDH KSZ9021RL/RN R 10K D1 CPU/FPGA RESET_N RST_OUT_n D2 C 10uF D1, D2: 1N4148 2009-2019 Microchip Technology Inc. DS00003050A-page 57 KSZ9021RL/RN 6.6 Reference Circuits - LED Strap-in Pins The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in the following figure. FIGURE 6-6: REFERENCE CIRCUITS FOR LED STRAPPING PINS DVDDH Pull-up KSZ9021RL/RN LED pin DVDDH Pull-down KSZ9021RL/RN LED pin DS00003050A-page 58 2009-2019 Microchip Technology Inc. KSZ9021RL/RN 6.7 Reference Clock - Connection and Selection A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9021RL/RN. The reference clock is 25 MHz for all operating modes of the KSZ9021RL/RN. The following figure and table show the reference clock connection to pins XI and XO of the KSZ9021RL/RN, and the reference clock selection criteria. FIGURE 6-7: 25MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION 22pF 22pF 22pF 22pF XI XI 25MHz OSC +/-50ppm XO NC TABLE 6-6: XO NC 25MHz XTAL +/-50ppm REFERENCE CRYSTAL/CLOCK SELECTION CRITERIA Characteristics Value Units Frequency 25 MHz Frequency tolerance (max) 50 ppm 6.8 Magnetics Specification A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The following tables provide recommended magnetic characteristics and a list of qualified magnetics for the KSZ9021RL/RN. TABLE 6-7: MAGNETICS SELECTION CRITERIA Parameter Value Turns ratio 1 CT : 1 CT Open-circuit inductance (min.) Insertion loss (max.) HIPOT (min.) TABLE 6-8: Test Condition 350H 100mV, 100kHz, 8mA 1.0dB 0MHz-100MHz 1500Vrms QUALIFIED SINGLE PORT 10/100/1000 MAGNETICS Magnetic Manufacturer Part Number Auto MDI-X Number of Port Pulse H5007NL Yes 1 TDK TLA-7T101LF Yes 1 2009-2019 Microchip Technology Inc. DS00003050A-page 59 KSZ9021RL/RN 7.0 PACKAGE INFORMATION FIGURE 7-1: Note: 64-PIN (10MM X 10MM) E-LQFP PACKAGE OUTLINE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00003050A-page 60 2009-2019 Microchip Technology Inc. KSZ9021RL/RN FIGURE 7-2: 48-PIN (7MM X 7MM) QFN PACKAGE OUTLINE TITLE 48 LEAD QFN 7x7mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING # QFN77-48LD-PL-1 UNIT MM 7.000.05 5.100.05 Exp.DAP 48 PIN #1 ID CHAMFER 0.35x45 0.400.05 1 2 0.50 Bsc 5.100.05 Exp.DAP 7.000.05 0.250.05 5.50 Ref. Top View Bottom View NOTE: 1, 2, 3 NOTE: 1, 2, 3 0.850.05 0.00-0.05 0.253 (REF) Side View NOTE: 1, 2, 3 NOTE: 1. MAX PACKAGE WARPAGE IS 0.05mm. 2. MAX ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. 3. PIN #1 IS ON TOP WILL BE LASER MARKED. 4. RED CIRCLE IN LAND PATTERN INDICATES THERMAL VIA. SIZE SHOULD BE 0.30-0.35mm IN DIAMETER AND SHOULD BE CONNECTED TO GND FOR MAX THERMAL PERFORMANCE. PITCH is 1.00mm. 5. GREEN RECTANGLES (SHADED AREA) REPRESENT SOLDER STENCIL OPENING ON EXPOSED PAD AREA. RECOMMENDED SIZE IS 1.00x1.00mm, SPACING IS 0.25mm. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 2009-2019 Microchip Technology Inc. DS00003050A-page 61 KSZ9021RL/RN FIGURE 7-2: 48-PIN (7MM X 7MM) QFN PACKAGE OUTLINE (CONTINUED) POD-Land Pattern drawing #: QFN77-48LD-PL-1-C Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00003050A-page 62 2009-2019 Microchip Technology Inc. KSZ9021RL/RN APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00003043A (06-04-19) Section/Figure/Entry Correction Replaces previous Micrel version Rev. 1.2 (02-13-14) Rev. 1.2 (02-13-14) Added RGMII Pad Skew Registers section. Corrected pad skew steps in Registers 260 (104h) and 261 (105h). Data sheet values are incorrect. There is no change to the silicon. Added Register 262 (106h) for RGMII TX Data Pad Skew. Updated boilerplate. Rev. 1.1 (10-13-09) Updated current consumption in Electrical Characteristics section. Corrected data sheet omission of register 1 bit 8 for 1000Base-T Extended Status information. Added the following register bits to provide further power saving during software power down: Tri-state all digital I/Os (reg. 258.7), LDO disable (reg. 263.15), Low frequency oscillator mode (reg. 263.8). Added KSZ9021RN device and updated entire data sheet accordingly. Added 48-Pin QFN package information. Rev. 1.0 (10-13-09) Data sheet created 2009-2019 Microchip Technology Inc. DS00003050A-page 63 KSZ9021RL/RN THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support DS00003050A-page 64 2009-2019 Microchip Technology Inc. KSZ9021RL/RN PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - [X] Temperature Range XXX Package Device: KSZ9021RL, KSZ9021RN Temperature: Blank I Package: RL RN Tape and Reel Option: Blank TR = 0C to = -40C to = = - +70C +85C [X](1) Tape and Reel Option (Commercial) (Industrial) 64-pin E-LQFP 48-pin QFN Examples: a) KSZ9021RL Commercial Temperature, RGMII 64-pin E-LQFP, Tray b) KSZ9021RLI Industrial Temperature, RGMII 64-pin E-LQFP, Tray c) KSZ9021RN Commercial Temperature, RGMII 48-pin QFN, Tray d) KSZ9021RNI Industrial Temperature, RGMII 48-pin QFN, Tray = Standard packaging (tray) = Tape and Reel(1) Note 1: 2009-2019 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS00003050A-page 65 KSZ9021RL/RN Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2009-2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 9781522444145 For information regarding Microchip's Quality Management Systems, please visit www.microchip.com/quality. DS00003050A-page 66 2009-2019 Microchip Technology Inc. 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