HB52A48DB Series, HB52A88DC Series
HB52A48DB
32 MB Unbuffered SDRAM S.O.DIMM
4-Mword × 64-bit, 66 MHz Memory Bus, 1-Bank Module
(4 pcs of 4 M × 16 components)
HB52A88DC
64 MB Unbuffered SDRAM S.O.DIMM
8-Mword × 64-bit, 66 MHz Memory Bus, 2-Bank Module
(8 pcs of 4 M × 16 components)
ADE-203-874B (Z)
Rev. 1.0
July 17, 1998
Description
The HB52A48DB is a 4M × 64 × 1 banks Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 4 pieces of 64-Mbit SDRAM (HM5264165TT) sealed in TSOP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). The HB52A88DC is
a 4M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module
(S.O.DIMM), mounted 8 pieces of 64-Mbit SDRAM (HM5264165TT) sealed in TSOP package and 1
piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin
Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting
possible without surface mount technology. They provide common data inputs and outputs. Decoupling
capacitors are mounted beside TSOP on the module board.
Features
• Fully compatible with JEDEC standard outline unbuffered 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length) × 25.40/29.21 mm (Height) × 3.80 mm (Thickness)
Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 66 MHz
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
HB52A48DB Series, HB52A88DC Series
2
• Programmable burst length : 1/2/4/8/full page
• 2 Variations of burst sequence
Sequential
interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
Auto refresh
Self refresh
• Low self refresh current: HB52A48DB/HB52A88DC-10L (L-version)
• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency Package Contact pad
HB52A48DB-10
HB52A48DB-10L 66 MHz
66 MHz Small outline DIMM (144-pin) Gold
HB52A88DC-10
HB52A88DC-10L 66 MHz
66 MHz
Pin Arrangement
Front Side
Back Side
2pin 60pin 62pin 144pin
1pin 59pin 61pin 143pin
HB52A48DB Series, HB52A88DC Series
3
Pin Arrangement (cont.)
Front side Back side
Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name
1V
SS 73 NC 2 VSS 74 CK1
3 DQ0 75 VSS 4 DQ32 76 VSS
5 DQ1 77 NC 6 DQ33 78 NC
7 DQ2 79 NC 8 DQ34 80 NC
9 DQ3 81 VCC 10 DQ35 82 VCC
11 VCC 83 DQ16 12 VCC 84 DQ48
13 DQ4 85 DQ17 14 DQ36 86 DQ49
15 DQ5 87 DQ18 16 DQ37 88 DQ50
17 DQ6 89 DQ19 18 DQ38 90 DQ51
19 DQ7 91 VSS 20 DQ39 92 VSS
21 VSS 93 DQ20 22 VSS 94 DQ52
23 DQMB0 95 DQ21 24 DQMB4 96 DQ53
25 DQMB1 97 DQ22 26 DQMB5 98 DQ54
27 VCC 99 DQ23 28 VCC 100 DQ55
29 A0 101 VCC 30 A3 102 VCC
31 A1 103 A6 32 A4 104 A7
33 A2 105 A8 34 A5 106 A13 (BA0)
35 VSS 107 VSS 36 VSS 108 VSS
37 DQ8 109 A9 38 DQ40 110 A12 (BA1)
39 DQ9 111 A10 (AP) 40 DQ41 112 A11
41 DQ10 113 VCC 42 DQ42 114 VCC
43 DQ11 115 DQMB2 44 DQ43 116 DQMB6
45 VCC 117 DQMB3 46 VCC 118 DQMB7
47 DQ12 119 VSS 48 DQ44 120 VSS
49 DQ13 121 DQ24 50 DQ45 122 DQ56
51 DQ14 123 DQ25 52 DQ46 124 DQ57
53 DQ15 125 DQ26 54 DQ47 126 DQ58
55 VSS 127 DQ27 56 VSS 128 DQ59
57 NC 129 VCC 58 NC 130 VCC
59 NC 131 DQ28 60 NC 132 DQ60
61 CK0 133 DQ29 62 CKE0 134 DQ61
63 VCC 135 DQ30 64 VCC 136 DQ62
65 RE 137 DQ31 66 CE 138 DQ63
HB52A48DB Series, HB52A88DC Series
4
Front side Back side
Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name
67 W139 VSS 68 NC (CKE1) *
2 140 VSS
69 S0 141 SDA 70 NC 142 SCL
71 NC (S1)*1143 VCC 72 NC 144 VCC
Notes: 1. NC: HB52A48DB, S1: HB52A88DC
2. NC: HB52A48DB, CKE1: HB52A88DC
Pin Description (HB52A48DB)
Pin name Function
A0 to A11 Address input
• Row address A0 to A11
• Column address A0 to A7
A12/A13 Bank select address BA1, BA0
DQ0 to DQ63 Data-input/output
S0 Chip select
RE Row address asserted bank enable
CE Column address asserted
WWrite enable
DQMB0 to DQMB7 Byte input/output mask
CK0/CK1 Clock input
CKE0 Clock enable
SDA Data-input/output for serial PD
SCL Clock input for serial PD
VCC Power supply
VSS Ground
NC No connection
HB52A48DB Series, HB52A88DC Series
5
Pin Description (HB52A88DC)
Pin name Function
A0 to A11 Address input
• Row address A0 to A11
• Column address A0 to A7
A12/A13 Bank select address BA1, BA0
DQ0 to DQ63 Data-input/output
S0/S1 Chip select
RE Row address asserted bank enable
CE Column address asserted
WWrite enable
DQMB0 to DQMB7 Byte input/output mask
CK0/CK1 Clock input
CKE0/CKE1 Clock enable
SDA Data-input/output for serial PD
SCL Clock input for serial PD
VCC Power supply
VSS Ground
NC No connection
HB52A48DB Series, HB52A88DC Series
6
Serial PD Matrix*1
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 Number of bytes used by
module manufacturer 1000000080 128
1 Total SPD memory size 0000100008 256 byte
2 Memory type 0000010004 SDRAM
3 Number of row addresses bits 000011000C 12
4 Number of column addresses
bits 0000100008 8
5 Number of bank s
( HB52A48DB) 0000000101 1
Number of bank s
( HB52A88DC) 0000001002 2
6 Module data width 0100000040 64
7 Module data width (continued) 0000000000 0 (+)
8 Module interface signal levels 0000000101 LVTTL
9 SDRAM cycle time
(highest CE latency)
15 ns
11110000F0 CL = 3
10 SDRAM access from Clock
(highest CE latency)
9 ns
1001000090
11 Module configuration type 0000000000 Non parity
12 Refresh rate/type 1000000080 Normal
(15.625 µs)
Self refresh
13 SDRAM width 0001000010 4M × 16
14 Error checking SDRAM width 0000000000 —
15 SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
0000000101 1 CLK
16 SDRAM device attributes:
Burst lengths supported 100011118F 1, 2, 4, 8, full
page
17 SDRAM device attributes:
number of banks on SDRAM
device
0000010004 4
18 SDRAM device attributes:
CE latency 0000011006 2, 3
19 SDRAM device attributes:
S0 latency 0000000101 0
20 SDRAM device attributes:
W latency 0000000101 0
HB52A48DB Series, HB52A88DC Series
7
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
21 SDRAM module attributes 0000000000 Non buffer
22 SDRAM device attributes:
General 000011100E V
CC ± 10%
23 SDRAM cycle time
(2nd highest CE latency)
15 ns
11110000F0 CL = 2
24 SDRAM access from Clock
(2nd highest CE latency)
9 ns
1001000090
25 SDRAM cycle time
(3rd highest CE latency)
Undefined
0000000000
26 SDRAM access from Clock
(3rd highest CE latency)
Undefined
0000000000
27 Minimum row precharge time 000111101E 30 ns
28 Row active to row active min 0001010014 20 ns
29 RE to CE delay min 000111101E 30 ns
30 Minimum RE pulse width 001111003C 60 ns
31 Density of each bank on
module (HB52A48DB) 0000100008 32M byte
Density of each bank on
module (HB52A88DC) 0000100008 2 bank
32M byte
32 Address and command signal
input setup time 0011000030 3 ns
33 Address and command signal
input hold time 0001010115 1.5 ns
34 Data signal input setup time 0011000030 3 ns
35 Data signal input hold time 0001010115 1.5 ns
36 to 61 Superset information 0000000000 Future use
62 SPD data revision code 0001001012 Rev. 1.2A
63 Checksum for bytes 0 to 62
(HB52A48DB) 010011004C 76
Checksum for bytes 0 to 62
(HB52A88DC) 010011014D 77
64 Manuf act ur er’ s JE DE C ID c ode0000011107 HITACHI
65 to 71 Manuf act ur er’ s JE DE C ID c ode0000000000
72 Manufacturing location ×××××××××× *
3
(ASCII-
8bit code)
HB52A48DB Series, HB52A88DC Series
8
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
73 Manufacturer’s part number 0100100048 H
74 Manufacturer’s part number 0100001042 B
75 Manufacturer’s part number 0011010135 5
76 Manufacturer’s part number 0011001032 2
77 Manufacturer’s part number 0100000141 A
78 Manufacturer’s part number
(HB52A48DB) 0011010034 4
Manufacturer’s part number
(HB52A88DC) 0011100038 8
79 Manufacturer’s part number 0011100038 8
80 Manufacturer’s part number 0100010044 D
81 Manufacturer’s part number
(HB52A48DB) 0100001042 B
Manufacturer’s part number
(HB52A88DC) 0100001143 C
82 Manufacturer’s part number 001011012D —
83 Manufacturer’s part number 0011000131 1
84 Manufacturer’s part number 0011000030 0
85 Manufacturer’s part number
(L-version) 010011004C L
Manufacturer’s part number 0010000020 (Space)
86 Manufacturer’s part number 0010000020 (Space)
87 Manufacturer’s part number 0010000020 (Space)
88 Manufacturer’s part number 0010000020 (Space)
89 Manufacturer’s part number 0010000020 (Space)
90 Manufacturer’s part number 0010000020 (Space)
91 Revision code 0011000030 Initial
92 Revision code 0010000020 (Space)
93 Manufacturing date ×××××××××× Year code
(BCD)*4
94 Manufacturing date ×××××××××× Week code
(BCD)*4
95 to 98 Assembly serial number *6
99 to 125 Manufacturer specific data ————————— *
5
126 Intel specification frequency 0110011066 66 MHz
127 Intel specification CE# latency
support 0000011006 CL = 2, 3
HB52A48DB Series, HB52A88DC Series
9
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
HB52A48DB Series, HB52A88DC Series
10
Block Diagram (HB52A48DB)
DQMB0
DQ0 to DQ7
RAS (D0 to D3)
CAS (D0 to D3)
A0 to A11 A0 to A11 (D0 to D3)
CKE0 CKE (D0 to D3)
V
CC
V
CC
(D0 to D3, U0)
V
SS
V
SS
(D0 to D3, U0)
C100-C103
Serial PD
SDA
A0
A1
A2
V
SS
SCL U0 SDA
SCL
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output. 
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
R0
CK0 CLK (D0)
8N0, N1
DQMB1
DQ8 to DQ15 8N2, N3
CLK (D1)
R1
C0-C7
D0
R2
CK1 CLK (D2)
CLK (D3)
R3
RE
CE
A13 (D0 to D3)
BA1 A12 (D0 to D3)
BA0
W
S0
CS DQMB4
DQ32 to DQ39 8N8, N9
DQMB5
DQ40 to DQ47 8N10, N11
D2
CS
DQMB2
DQ16 to DQ23 8N4, N5
DQMB3
DQ24 to DQ31 8N6, N7
D1
CS DQMB6
DQ48 to DQ55 8N12, N13
DQMB7
DQ56 to DQ63 8N14, N15
D3
CS
* D0 to D3 : HM5264165TT
U0 : 2-kbit EEPROM
C0 to C7 : 0.33 µF
C100 to C103 : 0.1 µF
N0 to N15 : Network resistors (10 Ω)
R0 to R3 : Resistors (10 Ω)
HB52A48DB Series, HB52A88DC Series
11
Block Diagram (HB52A88DC)
DQMB0
DQ0 to DQ7
RAS (D0 to D7)
CAS (D0 to D7)
A0 to A11 A0 to A11 (D0 to D7)
CKE0 CKE (D0 to D3)
CKE1 CKE (D4 to D7)
V
CC
V
CC
(D0 to D3, U0)
V
SS
V
SS
(D0 to D3, U0)
C100-C107
Serial PD
SDA
A0
A1
A2
V
SS
SCL U0 SDA
SCL
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output. 
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
R0
CK0 CLK (D0)
8N0, N1
DQMB4
DQ32 to DQ39 8N2, N3
CLK (D4)
CLK (D1)
CLK (D5)
R1
R2
CK1 CLK (D2)
CLK (D6)
CLK (D3)
CLK (D7)
R3
C0-C15
D0
RE
CE
A13 (D0 to D7)
BA1 A12 (D0 to D7)
BA0
S1
S0
W
CS DQMB2
DQ16 to DQ23 8N8, N9
DQMB6
DQ48 to DQ55 8N10, N11
D2
CS
DQMB1
DQ8 to DQ15 8N4, N5
DQMB5
DQ40 to DQ47 8N6, N7
D1
CS
D4
CS
D5
CS
D6
CS
D7
CS
DQMB3
DQ24 to DQ31 8N12, N13
DQMB7
DQ56 to DQ63 8N14, N15
D3
CS
* D0 to D7 : HM5264165TT
U0 : 2-kbit EEPROM
C0 to C15 : 0.33 µF
C100 to C107 : 0.1 µF
N0 to N15 : Network resistors (10 Ω)
R0 to R3 : Resistors (10 Ω)
HB52A48DB Series, HB52A88DC Series
12
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to VSS VT–0.5 to VCC + 0.5
(≤ 4.6 (max)) V1
Supply voltage relative to VSS VCC –0.5 to +4.6 V 1
Short circuit output current Iout 50 mA
Power dissipation PT4.0 W
Operating temperature Topr 0 to +65 °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Respect to VSS.
DC Operating Conditions (Ta = 0 to +65°C)
Parameter Symbol Min Max Unit Notes
Supply voltage VCC 3.0 3.6 V 1, 2
VSS 00V3
Input high voltage VIH 2.0 VCC + 0.3 V 1, 4, 5
Input low voltage VIL –0.3 0.8 V 1, 6
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level.
3. The supply voltage with all VSS pins must be on the same level.
4. CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
5. Others: VIH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
6. VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.
HB52A48DB Series, HB52A88DC Series
13
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52A48DB)
HB52A48DB-10/10L
Parameter Symbol Min Max Unit Test conditions Notes
Operating current
(CE latency = 2) ICC1 — 300 mA Burst length = 1
tRC = min 1, 2, 3
(CE latency = 3) ICC1 — 320 mA
Standby current in power down ICC2P — 12 mA CKE0 = VIL, tCK = 15 ns 6
Standby current in power down
(input signal stable) ICC2PS — 8 mA CKE0 = VIL, tCK = ∞7
Standby current in non power
down ICC2N — 80 mA CKE0, S = VIH,
tCK = 15 ns 4
Active standby current in power
down ICC3P — 24 mA CKE0, S = VIH,
tCK = 15 ns 1, 2, 6
Active standby current in non
power down ICC3N — 120 mA CKE0, S = VIH,
tCK = 15 ns 1, 2, 4
Burst operating current
(CE latency = 2) ICC4 — 480 mA tCK = 15 ns, BL = 4 1, 2, 5
(CE latency = 3) ICC4 — 680 mA
Refresh current ICC5 — 440 mA tRC = min 3
Self refresh current ICC6 — 8 mA VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V 8
Self refresh current
(L-version) ICC6 — 1.6 mA
Input leakage current ILI –10 10 µA0 ≤ Vin ≤ VCC
Output leakage current ILO –10 10 µA0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage VOH 2.4 — V IOH = –2 mA
Output low voltage VOL — 0.4 V IOL = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
HB52A48DB Series, HB52A88DC Series
14
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HB52A88DC)
HB52A88DC-10/10L
Parameter Symbol Min Max Unit Test conditions Notes
Operating current
(CE latency = 2) ICC1 — 420 mA Burst length = 1
tRC = min 1, 2, 3
(CE latency = 3) ICC1 — 440 mA
Standby current in power down ICC2P — 24 mA CKE0 = VIL, tCK = 15 ns 6
Standby current in power down
(input signal stable) ICC2PS — 16 mA CKE0 = VIL, CK0/CK1 =
VIL or VIH Fixed 7
Standby current in non power
down ICC2N — 160 mA CKE0, S = VIH,
tCK = 15 ns 4
Active standby current in power
down ICC3P — 48 mA CKE0, S = VIH,
tCK = 15 ns 1, 2, 6
Active standby current in non
power down ICC3N — 240 mA CKE0, S = VIH,
tCK = 15 ns 1, 2, 4
Burst operating current
(CE latency = 2) ICC4 — 600 mA tCK = min, BL = 4 1, 2, 5
(CE latency = 3) ICC4 — 800 mA
Refresh current ICC5 — 560 mA tRC = min 3
Self refresh current ICC6 —16mAV
IH ≥ VCC – 0.2 V
VIL ≤ 0.2 V 8
Self refresh current
(L-version) ICC6 — 3.2 mA
Input leakage current ILI –10 10 µA0 ≤ Vin ≤ VCC
Output leakage current ILO –10 10 µA0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage VOH 2.4 — V IOH = –2 mA
Output low voltage VOL — 0.4 V IOL = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
HB52A48DB Series, HB52A88DC Series
15
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52A48DB)
Parameter Symbol Max Unit Notes
Input capacitance (Address) CIN 40 pF 1, 2, 4
Input capacitance (RE, CE, W, CK0/CK1, CKE0) CIN 40 pF 1, 2, 4
Input capacitance (S0)C
IN 40 pF 1, 2, 4
Input capacitance (DQMB0 to DQMB7) CIN 20 pF 1, 2, 4
Input/Output capacitance (DQ0 to DQ63) CI/O 20 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) (HB52A88DC)
Parameter Symbol Max Unit Notes
Input capacitance (Address) CIN 60 pF 1, 2, 4
Input capacitance (RE, CE, W, CK0/CK1, CKE0) CIN 60 pF 1, 2, 4
Input capacitance (S0/S1)C
IN 40 pF 1, 2, 4
Input capacitance (DQMB0 to DQMB7) CIN 30 pF 1, 2, 4
Input/Output capacitance (DQ0 to DQ63) CI/O 27 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
HB52A48DB Series, HB52A88DC Series
16
AC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52A48DB-10/10L
HB52A88DC-10/10L
Parameter Symbol Min Max Unit Notes
System clock cycle time
(CE latency = 2) tCK 15 — ns 1
(CE latency = 3) tCK 15 —
CK0/CK1 high pulse width tCKH 5 — ns 1
CK0/CK1 low pulse width tCKL 5 — ns 1
Access time from CK0/CK1
(CE latency = 2) tAC — 9 ns 1, 2
(CE latency = 3) tAC —9
Data-out hold time tOH 2.5 — ns 1, 2
CK0/CK1 to Data-out low impedance tLZ 2 — ns 1, 2, 3
CK0/CK1 to Data-out high impedance tHZ — 7 ns 1, 4
Data-in setup time tDS 3 — ns 1
Data in hold time tDH 1.5 — ns 1
Address setup time tAS 3 — ns 1
Address hold time tAH 1.5 — ns 1
CKE0 setup time tCES 3 — ns 1, 5
CKE0 setup time for power down exit tCESP 3 — ns 1
CKE0 hold time tCEH 1.5 — ns 1
Command setup time tCS 3 — ns 1
Command hold time tCH 1.5 — ns 1
Ref/Active to Ref/Active command period tRC 105 — ns 1
Active to precharge command period tRAS 60 120000 ns 1
Active command to column command (same bank) tRCD 30 — ns 1
Precharge to active command period tRP 30 — ns 1
Write recovery or data in to precharge lead time tDPL 30 — ns 1
Active (a) to Active (b) command period tRRD 20 — ns 1
Transition time (rise to fall) tT15ns
Refresh period tREF —64ms
HB52A48DB Series, HB52A88DC Series
17
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.40 V.
2. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source.
3. tLZ (max) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max) defines the time at which the outputs achieves the high impedance state.
5. tCES defines CKE0 setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.4 V
• Input waveform and output load: See following figures
t
T
2.8 V
VSS
input 80%
20%
tT
50 Ω+1.4 V
DQ
CL
HB52A48DB Series, HB52A88DC Series
18
Relationship Between Frequency and Minimum Latency
Parameter HB52A48DB-10/10L
HB52A88DC-10/10L
Frequency (MHz) 66
tCK (ns) Symbol 15 Notes
Active command to column command
(same bank) IRCD 21
Active command to active command (same bank)
(CE latency = 2) IRC 7= [IRAS + IRP]
1
(CE latency = 3) IRC 8
Active command to precharge command
(same bank)
(CE latency = 2) IRAS 4
1
(CE latency = 3) IRAS 5
Precharge command to active command
(same bank) IRP 21
Write recovery or data input to precharge
command (same bank) IDPL 21
Active command to active command
(different bank) IRRD 21
Self refresh exit time ISREX 22
Last data in to active command
(Auto precharge, same bank) IAPW 5 = [IDPL + IRP]
Self refresh exit to command input ISEC 7 = [IRC]
3
Precharge command to high impedance
(CE latency = 2) IHZP 2
(CE latency = 3) IHZP 3
Last data out to active command (auto precharge)
(same bank) IAPR 1
Last data out to precharge (early precharge)
(CE latency = 2) IEP –1
(CE latency = 3) IEP –2
Column command to column command ICCD 1
Write command to data in latency IWCD 0
DQMB to data in IDID 0
DQMB to data out
(CE latency = 2) IDOD 2
(CE latency = 3) IDOD 3
CKE0 to CK0/CK1 disable ICLE 1
HB52A48DB Series, HB52A88DC Series
19
Relationship Between Frequency and Minimum Latency (cont)
Parameter HB52A48DB-10/10L
HB52A88DC-10/10L
Frequency (MHz) 66
tCK (ns) Symbol 15 Notes
Register set to active command tRSA 3
S0 to command disable ICDD 0
Power down exit to command input IPEC 1
Burst stop to output valid data hold
(CE latency = 2) IBSR 1
(CE latency = 3) IBSR 2
Burst stop to output high impedance
(CE latency = 2) IBSH 2
(CE latency = 3) IBSH 3
Burst stop to write data ignore IBSW 0
Notes: 1. tRCD to tRRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
HB52A48DB Series, HB52A88DC Series
20
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the
read or write command cycle CK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
A12/A13 (BS) is precharged.
A12/A13 (input pin): A12/A13 is a bank select signal (BS). The memory array is divided into bank0,
bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is
Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is
HIgh, bank3 is selected.
CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for
power-down mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is
Low, the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
HB52A48DB Series, HB52A88DC Series
21
Command Operation
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE0
Command Symbol n - 1 n S0 RE CE W A12/
A13 A10 A0
to A11
Ignore command DESL H ×H××××××
No operation NOP H ×LHHH×××
Burst stop in full page BST H ×LHHL×××
Column address and read command READ H ×LHLHVLV
Read with auto-precharge READ A H ×LHLHVHV
Column address and write command WRIT H ×LHLLVLV
Write with auto-precharge WRIT A H ×LHLLVHV
Row address strobe and bank act. ACTV H ×LLHHVVV
Precharge select bank PRE H ×LLHLVL×
Precharge all bank PALL H ×LLHL×H×
Refresh REF/SELF H V LLLH×××
Mode register set MRS H ×LLLLVVV
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S0 is High), the SDRAM module ignore command
input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page),
and is illegal otherwise. When data input/output is completed for a full page of data, it automatically
returns to the start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In
addition, the start address of burst read is determined by the column address and the bank select address
(BA). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation
after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page, this command is
illegal.
HB52A48DB Series, HB52A88DC Series
22
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address and the bank select address (BA) become the burst write
start address. When the single write mode is selected, data is only written to the location specified by the
column address and the bank select address (BA).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation
after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is
full-page, this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
bank select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low,
bank0 is activated. When A12 is High and A13 is Low, bank1 is activated. When A12 is Low and A13 is
High, bank2 is activated. When A12 and A13 are High, bank3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected.
If A12 is Low and A13 is High, bank2 is selected. If A12 and A13 are High, bank3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh
operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE0 truth table
section.
Mode register set [MRS]: The SDRAM module has a mode register that defines how it operates. The
mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer
to the mode register configuration. After power on, the contents of the mode register are undefined,
execute the mode register set command to set up the mode register.
DQMB Truth Table
CKE0
Command Symbol n - 1 n DQMB
Write enable/output enable ENB H ×L
Write inhibit/output disable MASK H ×H
Note: H: VIH. L: VIL. ×: VIH or VIL.
IDOD is needed.
The SDRAM module can mask input/output data by means of DQMB During reading, the output buffer is
set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to
High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting
DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not written).
Desired data can be masked during burst read or burst write by setting DQMB. For details, refer to the
DQMB control section of the SDRAM module operating instructions.
HB52A48DB Series, HB52A88DC Series
23
CKE Truth Table
CKE0
Current state Command n-1 n S0 RE CE W Address
Active Clock suspend mode entry H L H ××××
Any Clock suspend L L ×××××
Clock suspend Clock suspend mode exit L H ×××××
Idle Auto refresh command REF H H L L L H ×
Idle Self refresh entry SELF H L L L L H ×
Idle Power down entry H L L H H H ×
HLH××××
Self-refresh Self refresh exit SELFX L H L H H H ×
LHH××××
Power down Power down exit L H L H H H ×
LHH××××
Note: H: VIH. L: VIL. ×: VIH or VIL.
Clock suspend mode entry: The SDRAM module enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as
shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues
to be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM module exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the SDRAM module
starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAM
module.) During the auto refresh operation, refresh address and bank select address are generated inside
the SDRAM module. For every auto refresh cycle, the internal address counter is updated. Accordingly,
4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the
banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed
after auto refresh, no precharge command is required after auto refresh.
HB52A48DB Series, HB52A88DC Series
24
Self refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM module
starts self refresh operation. After the execution of this command, self refresh continues while CKE0 is
Low. Since self refresh is performed internally and automatically, external refresh operations are
unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self refresh exit: When this command is executed during self refresh mode, the SDRAM module can exit
from self refresh mode. After exiting from self refresh mode, the SDRAM module enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM module can
exit from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE
state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM module. The following table assumes that CKE is high.
Current
state
SRECEWAddress Command Operation
Precharge H ×××× DESL Enter IDLE after tRP
LHHH×NOP Enter IDLE after tRP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA ACTV ILLEGAL
L L H L BA, A10 PRE, PALL NOP
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Idle H ×××× DESL NOP
LHHH×NOP NOP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA ACTV Bank and row active
L L H L BA, A10 PRE, PALL NOP
LLLH×REF, SELF Refresh
L L L L MODE MRS Mode register set
HB52A48DB Series, HB52A88DC Series
25
Current
state
SRECEWAddress Command Operation
Row active H ×××× DESL NOP
LHHH×NOP NOP
LHHL×BST NOP
L H L H BA, CA, A10 READ/READ A Begin read
L H L L BA, CA, A10 WRIT/WRIT A Begin write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Precharge
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read H ×××× DESL Continue burst to end
LHHH×NOP Continue burst to end
LHHL×BST Burst stop to full page
L H L H BA, CA, A10 READ/READ A Continue burst read to CE latency
and new read
L H L L BA, CA, A10 WRIT/WRIT A Term burst read/start write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Term burst read and Precharge
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read with
auto-
precharge
H×××× DESL Continue burst to end and
precharge
LHHH×NOP Continue burst to end and
precharge
LHHL×BST ILLEGAL
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL ILLEGAL
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
HB52A48DB Series, HB52A88DC Series
26
Current
state
SRECEWAddress Command Operation
Write H ×××× DESL Continue burst to end
LHHH×NOP Continue burst to end
LHHL×BST Burst stop on full page
L H L H BA, CA, A10 READ/READ A Term burst and new read
L H L L BA, CA, A10 WRIT/WRIT A Term burst and new write
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL Term burst write and precharge*2
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Write with
auto-
precharge
H×××× DESL Continue burst to end and
precharge
LHHH×NOP Continue burst to end and
precharge
LHHL×BST ILLEGAL
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA ACTV Other bank active
ILLEGAL on same bank*3
L L H L BA, A10 PRE, PALL ILLEGAL
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Refresh
(auto refresh) H×××× DESL Enter IDLE after tRC
LHHH×NOP Enter IDLE after tRC
LHHL×BST Enter IDLE after tRC
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA ACTV ILLEGAL
L L H L BA, A10 PRE, PALL ILLEGAL
LLLH×REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of tDPL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
HB52A48DB Series, HB52A88DC Series
27
From PRECHARGE state, command operation
To [DESL], [NOR] or [BST]: When these commands are executed, the SDRAM module enters the IDLE
state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM module enters refresh mode (auto refresh or self refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM module to precharge mode. (However, an interval
of tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CE
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
HB52A48DB Series, HB52A88DC Series
28
From READ with AUTO PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM module then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge
mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
SDRAM module enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM module automatically
enters the IDLE state.
HB52A48DB Series, HB52A88DC Series
29
Simplified State Diagram
PRECHARGE
WRITE
SUSPEND READ
SUSPEND
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
ON
WRITEA
WRITEA
SUSPEND READA READA
SUSPEND
ACTIVE
CLOCK
SUSPEND
SR ENTRY
SR EXIT
MRS REFRESH
CKE
CKE_
ACTIVE
WRITE READ
WRITE
WITH AP READ
WITH AP
POWER
APPLIED
CKE CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
PRECHARGE
AP
READ WRITE
WRITE
WITH
AP
READ
WITH
READ
WITH AP WRITE
WITH AP
PRECHARGE
PRECHARGE PRECHARGE
BST
(on full page)
BST
(on full page)
*1
READ
Read
WRITE
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
HB52A48DB Series, HB52A88DC Series
30
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM module has two types of write modes. One is
the burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only “sequential” can be
selected.
A2, A1, A0: (BL): These pins specify the burst length.
A2 A1 A0 Burst Length
000 1
001 2
010 4
011 8
1 1 1 F.P.
BT=0 BT=1
100 R
110 R
1
2
4
8
R
R
R
A3
0 Sequential
1 Interleave
Burst TypeA6 A5 A4 CAS Latency
000 R
001 R
010 2
011 3
1XX R
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE 0 LMODE BT BL
A9
0
0R
Write mode
A8
0
1Burst read and burst write
1 Burst read and single write
0
1R
1
101 R R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
A11 A10
A10
X
X
X
A11
X
X
X
00
A12
A13
A13
X
X
X
0A12
X
X
X
0
HB52A48DB Series, HB52A88DC Series
31
Burst Sequence
A2 A1 A0 Addressing(decimal)
000
001
010
011
111
InterleaveSequential
100
110
101
Starting Ad.
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
Burst length = 8
A1 A0 Addressing(decimal)
00
01
10
11
InterleaveSequential
Starting Ad.
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Burst length = 4
A0 Addressing(decimal)
0
1
InterleaveSequential
Starting Ad.
0, 1,
1, 0, 0, 1,
1, 0,
Burst length = 2
HB52A48DB Series, HB52A88DC Series
32
Operation of the SDRAM module
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank0, bank1, bank2 or bank3 is activated according
to the status of the bank select address pin, and the row address (AX0 to AX11) is activated by the A0 to
A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CE Latency-1) cycle after read command set. The SDRAM module can perform a burst read
operation. The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is
specified by the column address and the bank select address (BA) at the read command set cycle. In a read
operation, data output starts after the number of clocks specified by the CE Latency. The CE Latency can
be set to 2 or 3. When the burst length is 1, 2, 4, or 8, full-page, the Dout buffer automatically becomes
High-Z at the next clock after the successive burst-length data has been output. The CE latency and burst
length must be specified at the mode register.
CE Latency
READ
CK
Command
Dout
ACTV
Row Column
Address
CL = 2
CL = 3
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3
t
RCD
CL = CE latency
Burst Length = 4
HB52A48DB Series, HB52A88DC Series
33
Burst Length
READ
CK
Command
Dout
ACTV
Row Column
out 0
out 6 out 7
out 8
Address
out 0 out 1
out 4 out 5
out 0 out 1 out 2 out 3
BL = 1
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3 out 6 out 7
out 4 out 5 out 0-1 out 0 out 1
BL = 2
BL = 4
BL = 8
BL = full page
tRCD
BL : Burst Length
CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9,
A8) of the mode register.
Burst write
A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same
clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4,
8, and full-page, like burst read operations. The write start address is specified by the column address and
the bank select address (BA) at the write command set cycle.
WRIT
CK
Command
Din
ACTV
Row Column
in 0
in 6 in 7
in 8
Address
in 1
in 4 in 5
in 3
BL = 1
in 6 in 7
in 4 in 5 in 0-1 in 0 in 1
BL = 2
BL = 4
BL = 8
BL = full page
tRCD
in 0
in 0
in 0
in 0
in 1
in 1
in 1
in 2
in 2
in 2
in 3
in 3
CE Latency = 2, 3
HB52A48DB Series, HB52A88DC Series
34
Single write
A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data
is only written to the column address and the bank select address (BA) specified by the write command set
cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CK
Command
Din
ACTV
Row Column
in 0
Address
tRCD
CE Latency = 2, 3
Burst Length = 1, 2, 4, 8, full page
Auto Precharge
Read with auto precharge: In this operation, since precharge is automatically performed after completing
a read operation, a precharge command need not be executed after each read operation. The command
executed for the same bank after the execution of this command must be the bank active (ACTV)
command. In addition, an interval defined by IAPR is required before execution of the next command.
CE latency Precharge start cycle
3 2 cycle before the final data is output
2 1 cycle before the final data is output
Burst Read (Burst Length = 4)
CK
lAPR
lRAS
lAPR
CL=2 Command
CL=3 Command
Dout
Dout
Note: Internal auto-precharge starts at the timing indicated by " ". 
And an interval of t
RAS
(l
RAS
) is required between previous active (ACTV) command and internal precharge " ". 
ACTV READ A ACTV
out3out2out1out0
lRAS
ACTV READ A ACTV
out3out2out1out0
HB52A48DB Series, HB52A88DC Series
35
Write with auto-precharge: In this operation, since precharge is automatically performed after
completing a burst write or single write operation, a precharge command need not be executed after each
write operation. The command executed for the same bank after the execution of this command must be the
bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data
input and input of next command.
Burst Write (Burst Length = 4)
CK
Command
Din
lAPW
IRAS
ACTV WRIT A
in0 in1 in2 in3
ACTV
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command 
and internal precharge " ".
Single Write
CK
Command
Din
lAPW
IRAS
ACTV WRIT A
in
ACTV
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command 
and internal precharge " ".
HB52A48DB Series, HB52A88DC Series
36
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output
during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst
read. The timing from command input to the last data changes depending on the CE latency setting. In
addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1,
2, 4 and 8.
CE latency BST to valid data BST to high impedance
21 2
32 3
CE Latency = 2, Burst Length = full page
l = 1 clock
BSR
CK
Command
Dout out out outout
l = 2 clocks
BSH
BST
out out
CE Latency = 3, Burst Length = full page
l = 2 clocks
BSR
CK
Command
Dout out out outout
l = 3 clocks
BSH
BST
outout out
HB52A48DB Series, HB52A88DC Series
37
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same clock as the BST command and in subsequent
clocks. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge
command.
Burst Length = full page
t
CK
Command
Din in
DPL
in
PRE/PALL
BST
I = 0 clock
BSW
HB52A48DB Series, HB52A88DC Series
38
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the
data read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CK
Command
Dout out B3
Address
out B1 out B2
BA
ACTV
Row Column A
READ READ
Column B
out A0 out B0
Bank0
Active Column =A
Read Column =B
Read Column =A
Dout Column =B
Dout CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive
read commands cannot be executed; it is necessary to separate the two read commands with a precharge
command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a
burst read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
Dout out B3
Address
out B1 out B2
BA
ACTV
Row 0 Row 1
ACTV READ
Column A
out A0 out B0
Bank0
Active Bank3
Active Bank0
Read Bank3
Read
READ
Column B
Bank0
Dout Bank3
Dout CE Latency = 3
Burst Length = 4
HB52A48DB Series, HB52A88DC Series
39
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW
address of the same bank as the preceding write command, the second write can be performed after an
interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Din
in B3
Address
in B1 in B2
BA
ACTV
Row
Column A
WRIT WRIT
Column B
in A0 in B0
Bank0
Active Column =A
Write Column =B
Write
Burst Write Mode
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
Din
in B3
Address
in B1 in B2
BA
ACTV
Row 0
Row 1
ACTV WRIT
Column A
in A0 in B0
Bank0
Active Bank3
Active Bank0
Write Bank3
Write
WRIT
Column B
Burst Write Mode
Burst Length = 4
HB52A48DB Series, HB52A88DC Series
40
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data
input.
READ to WRITE Command Interval (1)
CK
Command
Dout
in B2 in B3
READ WRIT
in B0 in B1
High-Z
Din
CL=2
CL=3
DQMB
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CK
Command
Dout
READ WRIT
Din
CL=2
CL=3
DQMB
High-Z
2 clock
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set
High so that the output buffer becomes High-Z before data input.
HB52A48DB Series, HB52A88DC Series
41
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of
the same bank as the preceding write command, the read command can be performed after an interval of no
less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle
before the read command is executed.
WRITE to READ Command Interval (1)
CK
Command
Din
WRIT READ
in A0
out B1 out B2 out B3
out B0
Dout
Column = A
Write Column = B
Read Column = B
Dout
CE Latency
DQMB
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
WRITE to READ Command Interval (2)
CK
Command
Din
WRIT READ
in A0
out B1 out B2 out B3
out B0Dout
Column = A
Write Column = B
Read Column = B
Dout
CE Latency
in A1
DQMB
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst
write, data will continue to be written until one clock before the read command is executed (as in the case
of the same bank and the same address).
Read command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the read command that preceded it, the minimum interval between the two
HB52A48DB Series, HB52A88DC Series
42
commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by
IHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is
input during burst read. To read all data by burst read, the clocks defined by IEP must be assured as an
interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 2, Burst Length = 4
CK
Command
Dout
READ
PRE/PALL
out A0 out A1 out A2 out A3
CL=2 l = -1 cycle
EP
CE Latency = 3, Burst Length = 4
CK
Command
Dout
READ
PRE/PALL
out A0 out A1 out A2 out A3
CL=3 l = -2 cycle
EP
HB52A48DB Series, HB52A88DC Series
43
READ to PRECHARGE Command Interval (same bank): To stop output data
CE Latency = 2, Burst Length = 1, 2, 4, 8, full pqge burst
CK
Command
Dout
READ PRE/PALL
out A0 High-Z
l
HZP
= 2
CE Latency = 3, Burst Length = 1, 2, 4, 8, full pqge burst
CK
Command
Dout
READ PRE/PALL
out A0 High-Z
l
HZP
= 3
HB52A48DB Series, HB52A88DC Series
44
Write command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the write command that preceded it, the minimum interval between the two
commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked
by means of DQMB for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CK
Command
Din
WRIT PRE/PALL
tDPL
DQMB
CK
in A0 in A1
Command
Din
WRIT
PRE/PALL
DQMB
t
DPL
Burst Length = 4 (To write all data)
CK
in A0 in A1 in A2
Command
Din
WRIT
PRE/PALL
in A3
DQMB
t
DPL
HB52A48DB Series, HB52A88DC Series
45
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank active to bank active for same bank
CK
Command
Address
BA
Bank 0
Active
ACTV
ROW
ACTV
ROW
Bank 0
Active
t
RC
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank active to bank active for different bank
CK
Command
Address
BA
Bank 0
Active Bank 3
Active
ACTV
ROW:0
ACTV
ROW:1
tRRD
HB52A48DB Series, HB52A88DC Series
46
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than lRSA.
CK
Command
Address
Mode
Register Set Bank
Active
MRS ACTV
IRSA
BS & ROWCODE
HB52A48DB Series, HB52A88DC Series
47
DQMB Control
The DQMB mask the lower and upper bytes of the DQ data, respectively. The timing of DQMB is
different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low,
the output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue.
The latency of DQMB during reading is 2 clocks.
CK
Dout out 0 out 1
l = 2 Latency
out 3
DOD
DQMB
High-Z
Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In
addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held.
The latency of DQMB during writing is 0 clock.
CK
Din in 0 in 1
l = 0 Latency
in 3

DID
DQMB
HB52A48DB Series, HB52A88DC Series
48
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-
refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after
exiting from self-refresh mode.
Others
Power-down mode: The SDRAM module enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM
module exits from the power down mode, and command input is enabled from the next clock. In this
mode, internal refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend
mode, and command input is enabled from the next clock. For details, refer to the “CKE Truth Table”.
Power-up sequence: The SDRAM module should be initialized by the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 µs or more has past after the above power on, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML to High, the output buffer becomes High-Z during Initialization sequence,
to avoid DQ bus contention on memory system formed with a number of device.
HB52A48DB Series, HB52A88DC Series
49
VCC
Power up sequence Initialization sequence
100 µs
0 V
Low
Low
Low
CKE, DQMB
CK
S, DQ
200 µs
Power stabilize
HB52A48DB Series, HB52A88DC Series
50
Timing Waveforms
Read Cycle
Bank 0
Active Bank 0
Read
CK
CKE
S
tRAS
tRCD
tCH
tCS
RE
CE
W
BA

A10
Address
DQMB
Din
Dout
tCH
tCS
tCKH t
tCK
CKL
tRP
tRC
CE latency = 2
Burst length = 4
Bank 0 access
= V or V
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
VIH
IH IL
Bank 0
Precharge
tAC tAC
tAC
tOH
tOH tOH
tOH
tAC
tLZ
tHZ







HB52A48DB Series, HB52A88DC Series
51
Write Cycle
CK
CKE
S
tRAS
tRCD
RE
CE
W
BA
A10
Address
Din
Dout
tCH
tCS
tCKH t
tCK
tDH tDH
CKL
tDH tDH
tDS
tDS tDS
tDS
tRP
tRC
tDPL
Bank 0
Write
tCH
tCS
Bank 0
Active Bank 0
Precharge
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tAH
tAS
tCH
tCS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tCH
tCS
tAH
tAS
tCH
tCS
tCH
tCS
tCH
tCS
tAH
tAS
tAH
tAS
VIH
CE latency = 2
Burst length = 4
Bank 0 access
= V or V
IH IL
DQMB
HB52A48DB Series, HB52A88DC Series
52
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CK
CKE
S
RE
CE
W
BA
Address
DQMB
Din
Dout




High-Z
bb+3 b’ b’+1 b’+2 b’+3
l
valid C: b’
RSA
code
lRCD
lRP
Precharge
If needed Mode 
register
Set
Bank 3
Active Bank 3
Read







R: b C: b



Output mask
VIH
l = 3
CE latency = 3
Burst length = 4
= V or V

IH IL
RCD
HB52A48DB Series, HB52A88DC Series
53
Read Cycle/Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
R:a C:a R:b C:b C:b' C:b"
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
CKE
RE
S
CE
W
Address
DQMB
Dout
Din
CK
BA


R:a C:a R:b C:b C:b' C:b"

a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1b"+2 b"+3




Bank 0
Active Bank 0
Read Bank 3
Active Bank 3
Read Bank 3
Read Bank 3
Read
Bank 0
Precharge Bank 3
Precharge
Bank 0
Active Bank 0
Write Bank 3
Active Bank 3
Write Bank 3
Write Bank 3
Write
Bank 0
Precharge Bank 3
Precharge
CKE
RE
S
CE
W
Address
DQMB
Din
Dout
BA
High-Z
High-Z

VIH
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
HB52A48DB Series, HB52A88DC Series
54
Read/Single Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920

R:a C:a R:b C:a'
R:a C:a C:a
a
a
a
a
Bank 0
Active Bank 0
Read Bank 3
Active Bank 0
Write Bank 0
Precharge Bank 3
Precharge
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
R:b
Bank 3
Active

C:a
Bank 0
Read
a a+1 a+2 a+3
Bank 0
Write Bank 0
Write
CKE
RE
S
CE
W
Address
DQMB
Din
Dout
CK
BA
CKE
RE
S
CE
W
Address
DQMB
BA
C:b
bc
a+1 a+3
a+1 a+2 a+3
C:c
VIH
VIH
Read/Single write
RE, CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
Din
Dout
HB52A48DB Series, HB52A88DC Series
55
Read/Burst Write Cycle
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
R:a C:a R:b C:a'
R:a C:a C:a
a a+1 a+2 a+3
a+1
a a+1 a+2 a+3
Bank 0
Active Bank 0
Read Bank 0
Write Bank 0
Precharge
R:b
Bank 3
Active
CKE
RE
S
CE
W
Address
DQMB
CK
BA
CKE
RE
S
CE
W
Address
DQMB
BA
a+1 a+2 a+3
a a+3
a
Bank 0
Active Bank 0
Read Bank 3
Active Clock
suspend Bank 0
Write Bank 0
Precharge Bank 3
Precharge
VIH
Read/Burst write
RE, CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
Din
Dout
Din
Dout
HB52A48DB Series, HB52A88DC Series
56
Full Page Read/Write Cycle
High-Z
R:a C:a R:b
R:a C:a R:b
High-Z

Bank 0
Active Bank 0
Read Bank 3
Active Burst stop Bank 3
Precharge
Bank 0
Active Bank 0
Write Bank 3
Active Burst stop Bank 3
Precharge
CKE
RE
S
CE
W
Address
DQMB
Din
Dout
CK
BA
CKE
RE
S
CE
W
Address
DQMB
BA
VIH
VIH
a a+1 a+2 a+3
Read cycle
RE, CE delay = 3
CE latency = 3
Burst length = full page
= V or V
IH IL
Write cycle
RE, CE delay = 3
CE latency = 3
Burst length = full page
= V or V
IH IL
a a+1 a+2 a+3 a+6a+5a+4
Din
Dout
HB52A48DB Series, HB52A88DC Series
57
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
CK
CKE
S
CE
W
BA
Address
DQMB
Din
Dout




High-Z
RP

Precharge
If needed Auto Refresh Active
Bank 0
tRC
tRC
t
Auto Refresh Read
Bank 0



R:a C:a
A10=1
RE








a a+1
VIH
Refresh cycle and
Read cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= V or V
IH IL
Self Refresh Cycle
CK
CKE
S
RE
CE
W
BA
Address
DQMB
Din
Dout







Precharge command
If needed Self refresh entry
command Auto
refresh
Self refresh exit
ignore command
or No operation


CKE Low
A10=1
RC
t
RP
t
Self refresh cycle
RE, CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
High-Z
Next
clock
enable
RC
t
Next
clock
enable

lSREX
Self refresh entry
command
HB52A48DB Series, HB52A88DC Series
58
Clock Suspend Mode
012345 6 7 8 9 101112131415161718192021

R:a C:a R:b
a a+1 a+2 a+3 b b+1 b+2



R:a C:a R:b C:b
a a+1 a+2 b b+1 b+2 b+3

C:b



Bank0
Active Active clock
suspend start Active clock
supend end
Bank0
Read
Bank3
Active
Read suspend
end Bank0
Precharge
Bank3
Read Precharge
Bank0
Write
Bank0
Active Active clock
suspend start Active clock
suspend end Bank3
Active
Write suspend
start Write suspend
end Bank3
Write Bank0
Precharge Earliest Bank3
Precharge
b+3
CKE
RE
S
CE
W
Address
DQMB
CK
BA
CKE
RE
S
CE
W
Address
DQMB
BA
a+3
High-Z
High-Z






tCES tCEH tCES
Read cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= V or V
IH IL
Write cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= V or V
IH IL
Dout
Din
Dout
Din
Read suspend
start Earliest Bank3
HB52A48DB Series, HB52A88DC Series
59
Power Down Mode
CK
CKE
S
RE
CE
W
BA
Address
DQMB
Din
Dout









Precharge command
If needed Power down entry
Active Bank 0
Power down 
mode exit
CKE Low
R: a


A10=1
RP
t


High-Z
Power down cycle
RE, CE delay = 3
CE latency = 3
Burst length = 4
= V or V
IH IL
Initialization Sequence
78910 52 53 54
48 49 50 51
Auto Refresh Bank active
If needed
RC
tRC
t
Auto Refresh
Valid
0123456
CK
CKE
S
RE
CE
W
Address
DQMB
DQ
t
valid
RSA
tRP
All banks
Precharge Mode register
Set

VIH
VIH
55
High-Z






code
HB52A48DB Series, HB52A88DC Series
60
Physical Outline (HB52A48DB)


















2
144
1.00 ± 0.10
0.039 ± 0.004
Detail A
0.25 Max.
0.010 Max.
2.55 Min.
0.100 Min.
0.60 ± 0.05
0.024 ± 0.002
0.80
0.031
2- ø1.80
2- ø0.071
2-R2.00
2-R0.079
3.70
0.146 23.20
0.913
4.60
0.181
2.10
0.083 32.80
1.291
4.00 ± 0.10
0.157 ± 0.004
3.80Max.
0.150Max.
(Datum -A-)
1.50 ± 0.10
0.059 ± 0.004
4.00 ± 0.10
0.157 ± 0.004
(DATUM -A-)
Detail B
R0.75
R0.030
2.5
0.098
2.00Min.
0.079Min.









Component area
(back)
2R3.00Min
2R0.118Min.
4.00Min.
0.157Min.
3.20Min.
0.126Min.
1
143
3.30
0.130 23.20
0.913 4.60
0.181
2.50
0.098
32.80
1.291
(Datum -A-)
25.40
1.000
6.00
0.236
20.00
0.787
67.60
2.661 63.60
2.504
24.50
0.965
A
B
Component area
(front)
Unit: mm
inch
HB52A48DB Series, HB52A88DC Series
61
Physical Outline (HB52A88DC)


















2
144
1.00 ± 0.10
0.039 ± 0.004
Detail A
0.25 Max.
0.010 Max.
2.55 Min.
0.100 Min.
0.60 ± 0.05
0.024 ± 0.002
0.80
0.031
2-R2.00
2-R0.079
3.70
0.146 23.20
0.913
4.60
0.181
2.10
0.083 32.80
1.291
4.00 ± 0.10
0.157 ± 0.004
3.80Max.
0.150Max.
(Datum -A-)
1.50 ± 0.10
0.059 ± 0.004
4.00 ± 0.10
0.157 ± 0.004
(DATUM -A-)
Detail B
R0.75
R0.030
2.5
0.098
2.00Min.
0.079Min.
Component area
(back)
2R3.00Min
2R0.118Min.
4.00Min.
0.157Min.
3.20Min.
0.126Min.
1
143
3.30
0.130 23.20
0.913 4.60
0.181
2.50
0.098
32.80
1.291
(Datum -A-)
29.21
1.150
20.00
0.787
67.60
2.661
A
B
Component area
(front)
Unit: mm
inch
HB52A48DB Series, HB52A88DC Series
62
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
Hitachi Asia Pte. Ltd.
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Singapore 049318
Tel: 535-2100
Fax: 535-1533
URL NorthAmerica  : http:semiconductor.hitachi.com/
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Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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Tel: <852> (2) 735 9218
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Telex: 40815 HITEC HX
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Tel: <44> (1628) 585000
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(America) Inc.
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Brisbane, CA 94005-1897
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
For further information write to:
HB52A48DB Series, HB52A88DC Series
63
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Dec. 20, 1997 Initial issue
(referred to HM5264165/HM5264805/HM5264405 Series
rev 0.5)
T. Sato K. Tsuneda
0.1 Feb. 20, 1998 (referred to HM5264165/HM5264805/HM5264405 Series
rev 0.6)
Unification of HB52A48DB and HB52A88DC
Change of Block diagram
Operation of Synchronous DRAM module
Change of description for Power-up sequence
AC Characteristics
tRP min: 45 ns to 30 ns
tRRD min: 30 ns to 20 ns
Timing Waveforms: Change of title
Power up sequence to Initialization sequence
T. Sato K. Tsuneda
1.0 Jul. 17, 1998 (referred to HM5264165/HM5264805/HM5264405 Series
rev 1.0)
Change of word: cycle to clock
: A12/A13 to BA (In figures and timing)
Serial PD Matrix
Change of based Intel specification: rev.1.2 to rev.1.2A
Change of Block Diagram
Change of title
Recommended DC Operating Conditions
to DC Operating Conditions
DC Operating Conditions
Deletion of typ
Addition of notes 2 to 3
DC Characteristics
ICC6 max (L-version): TBD to 1.6 mA (HB52A48DB)
ICC6 max (L-version): TBD to 3.2 mA (HB52A88DC)
Capacitance
CIN max: 25 pF to 20 pF
AC Characteristics
Relationship Between Frequency and Minimum Latency
lRP: 3 to 2
Change of notes 2 and Addition of notes 3
Command Truth Table
Addition of description for Burst stop in full page
Change of figures for Burst length, Auto precharge,
Power-up sequence and
WRITE to READ command interval (1) and (2)
Change of description for
Read command to Precharge command interval:
To output all data
Change of description for Self-refresh,
Power-up sequence and Initialization sequence
Timing Waveforms
Change of Read/Single Write Cycle
and Clock Suspend mode