Clock Generator PLL with Integrated VCO
Data Sheet ADF4360-9
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.
An additional divider stage allows division of the VCO signal.
The CMOS level output is equivalent to the VCO signal divided
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
14-BIT R
COUNTER
A
V
DD
CLK
DATA
V
TUNE
C
N
C
C
RF
OUT
A
RF
OUT
B
LD
CP
V
VCO
L1
DIVOUT
L2
LE
DV
DD
R
SET
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
24-BIT DATA
REGISTER
ADF4360-9
13-BIT B
COUNTER
N = B
VCO
CORE
DIVIDE-BY-A
(2 TO 31)
DIVIDE-BY-2
OUTPUT
STAGE
24-BIT
FUNCTION
LATCH
REF
IN
AGND DGND CPGND
07139-001
Figure 1.
ADF4360-9 Data Sheet
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
N Counter.................................................................................... 10
R Counter .................................................................................... 10
PFD and Charge Pump.............................................................. 10
Lock Detect ................................................................................. 10
Input Shift Register .................................................................... 10
VCO ............................................................................................. 11
Output Stage................................................................................ 12
DIVOUT Stage............................................................................ 12
Latch Structure ........................................................................... 13
Power-Up..................................................................................... 17
Control Latch.............................................................................. 18
N Counter Latch......................................................................... 19
R Counter Latch ......................................................................... 19
Applications..................................................................................... 20
Choosing the Correct Inductance Value................................. 20
Encode Clock for ADC.............................................................. 20
GSM Test Clock.......................................................................... 21
Interfacing ................................................................................... 22
PCB Design Guidelines for Chip Scale Package .................... 22
Output Matching........................................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
2/12—Rev. A to Rev. B
Added EPAD Note............................................................................ 7
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/08—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 3
Changes to Figure 23...................................................................... 14
Changes to Output Matching Section.......................................... 23
1/08—Revision 0: Initial Version
Data Sheet ADF4360-9
Rev. B | Page 3 of 24
SPECIFICATIONS
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 1.
Parameter B Version Unit Conditions/Comments
REFIN CHARACTERISTICS
REFIN Input Frequency 10/250 MHz min/MHz max For f < 10 MHz, use a dc-coupled, CMOS-compatible
square wave, slew rate > 21 V/μs
REFIN Input Sensitivity 0.7/AVDD V p-p min/V p-p max AC-coupled
0 to AVDD V max CMOS-compatible
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±60 μA max
PHASE DETECTOR
Phase Detector Frequency2 8 MHz max
CHARGE PUMP
ICP Sink/Source3 With RSET = 4.7 kΩ
High Value 2.5 mA typ
Low Value 0.312 mA typ
RSET Range 2.7/10 kΩ min/kΩ max
ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % typ VCP = 2.0 V
LOGIC INPUTS
Input High Voltage, VINH 1.5 V min
Input Low Voltage, VINL 0.6 V max
Input Current, IINH/IINL ±1 μA max
Input Capacitance, CIN 3.0 pF max
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V min CMOS output chosen
Output High Current, IOH 500 μA max
Output Low Voltage, VOL 0.4 V max IOL = 500 μA
POWER SUPPLIES
AVDD 3.0/3.6 V min/V max
DVDD AVDD
VVCO AVDD
AIDD4 5 mA typ
DIDD4 2.5 mA typ
IVCO4, 5 12.0 mA typ ICORE = 5 mA
IRFOUT4 3.5 to 11.0 mA typ RF output stage is programmable
Low Power Sleep Mode4 7 μA typ
RF OUTPUT CHARACTERISTICS5
Maximum VCO Output Frequency 400 MHz ICORE = 5 mA; depending on L1 and L2; see the
Choosing the Correct Inductance Value section
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 90/108 MHz min/MHz max L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other frequency values
VCO Frequency Range 1.2 Ratio fMAX/fMIN
VCO Sensitivity 2 MHz/V typ L1, L2 = 270 nH; see the Choosing the Correct
Inductance Value section for other sensitivity values
Lock Time6 400 μs typ To within 10 Hz of final frequency
ADF4360-9 Data Sheet
Rev. B | Page 4 of 24
Parameter B Version Unit Conditions/Comments
Frequency Pushing (Open Loop) 0.24 MHz/V typ
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load
Harmonic Content (Second) −16 dBc typ
Harmonic Content (Third) −21 dBc typ
Output Power5, 7 −9/0 dBm typ Using tuned load, programmable in 3 dB steps;
see Figure 35
Output Power5, 8 −14/−9 dBm typ
Using 50 Ω resistors to VVCO, programmable in
3 dB steps; see Figure 33
Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/V max
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance9,10 −91 dBc/Hz typ @ 10 kHz offset from carrier
−117 dBc/Hz typ @ 100 kHz offset from carrier
−139 dBc/Hz typ @ 1 MHz offset from carrier
−140 dBc/Hz typ @ 3 MHz offset from carrier
−147 dBc/Hz typ @ 10 MHz offset from carrier
Normalized In-Band Phase Noise 10, 11 −218 dBc/Hz typ
In-Band Phase Noise10, 11 −110 dBc/Hz typ @ 1 kHz offset from carrier
RMS Integrated Jitter12 1.4 ps typ Measured at RFOUTA
Spurious Signals Due to PFD Frequency13 −75 dBc typ
DIVOUT CHARACTERISTICS12
Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)
VCO frequency = 320 MHz to 380 MHz
DIVOUT = 180 MHz 1.4 ps rms A = 2, A output selected
DIVOUT = 95 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 80 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 52 MHz 1.4 ps rms A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MHz)
DIVOUT = 45 MHz 1.4 ps rms A = 4, A/2 output selected
DIVOUT = 10 MHz 1.6 ps rms A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MHz)
DIVOUT Duty Cycle
A Output 1/A × 100 % typ Divide-by-A selected
A/2 Output 50 % typ Divide-by-A/2 selected
1 Operating temperature range is −40°C to +85°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6 Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7 For more detail on using tuned loads, see the Out section. put Matching
8 Using 50 Ω resistors to VVCO into a 50 Ω load.
9 The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.
10 The phase noise is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer.
11 fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the
VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN.
12 The jitter is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz, unless otherwise
noted.
13 The spurious signals are measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides
the REFIN for the synthesizer; fREFIN = 10 MHz @ 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz.
Data Sheet ADF4360-9
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
1 Refer to the section for the recommended power-up procedure for this device. Power-Up
CLK
DATA
LE
LE
DB23 (MSB) DB22 DB2 DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
07139-002
Figure 2. Timing Diagram
ADF4360-9 Data Sheet
Rev. B | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VVCO to GND −0.3 V to +3.9 V
VVCO to AVDD −0.3 V to +0.3 V
Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance
Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 GND = CPGND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
The transistor count is 12,543 (CMOS) and 700 (bipolar).
ESD CAUTION
Data Sheet ADF4360-9
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1CPGND
2AV
DD
3AGND
4RF
OUT
A
5RF
OUT
B
6V
VCO
15 DGND
16 REF
IN
17 CLK
18 DATA
14 C
N
13 R
SET
7
V
TUNE
8
AGND
9
L1
11
AGND
12
C
C
10
L2 21 DV
DD
22 AGND
23 LD
24 CP
20 DIVOU
T
19 LE
TOP VIEW
(Not to Scale)
ADF4360-9
07139-003
NOTE
THE EXPOSED P
A
DDLE MUST BE CONNECTED TO
A
GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RFOUTA VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
5 RFOUTB VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output
Matching section for a description of the various output stages.
6 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
7 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
9 L1
An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and
L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
ICPmax = 11.75/RSET
For example, RSET = 4.7 kΩ and ICPmax = 2.5 mA.
14 CN Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.
15 DGND Digital Ground.
16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20 DIVOUT
This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.
Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD must have the same value as AVDD.
23 LD Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the
internal VCO.
EP Exposed Pad. The exposed pad must be connected to AGND.
ADF4360-9 Data Sheet
Rev. B | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–
20
–40
–60
–80
–100
–120
–140
–1601k 10k 100k 1M 10M
07139-004
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k100 10k 100k 1k 10M
07139-005
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth,
RMS Jitter = 1.4 ps
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
1k100 10k 100k 1M 10M
07139-006
FREQUENCY OFFSET (Hz)
Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A Selected, A = 2
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k100 10k 100k 1M 10M
07139-007
PHASE NOISE (dBc/Hz)
FREQUENCY (Hz)
Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
1k100 10k 100k 1M 10M
07139-008
FREQUENCY OFFSET (Hz)
Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,
Divide-by-A/2 Selected, A = 2
100 1k 10k 100k 1M
FREQUENCY OFFSET (Hz)
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
07139-009
Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz,
PFD Frequency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps,
Divide-by-A/2 Selected, A = 3
Data Sheet ADF4360-9
Rev. B | Page 9 of 24
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
PHASE NOISE (dBc/Hz)
1k100 10k 100k 1M 10M
07139-010
FREQUENCY OFFSET (Hz)
Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz,
PFD Frequency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.4 ps,
Divide-by-A/2 Selected, A = 2
–
100
–110
–120
–130
–140
–150
–160
1k 10k 100k 1M 10M
07139-011
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
+25°C
–40°C
+85°C
Figure 11. DIVOUT Phase Noise over Temperature, 52 MHz, VCO = 312 MHz,
PFD Frequency = 1 MHz, Loop Bandwidth = 60 kHz,
Divide-by-A/2 Selected, A = 3
07139-012
CH1 500mV M 2.00ns A CH1 20mV
1
C1 FREQUENCY: 180MHz
C1 + DUTY: 45.32%
Figure 12. DIVOUT 180 MHz Waveform, VCO = 360 MHz,
Divide-by-A Selected, A = 2, Duty Cycle = ~50%
07139-013
CH1 500mV M 2.00ns
1
A CH1 20mV
C1 FREQUENCY: 90MHz
C1 + DUTY: 28.98%
C1 PEAK TO PEAK: 1.55V
Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
A = 4, Duty Cycle = ~25%
07139-014
CH1 500mV M 5.00ns A CH1 920mV
1
C1 FREQUENCY: 36.01MHz
C1 + DUTY: 13.13%
C1 PEAK TO PEAK 1.28V
Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,
A = 10, Duty Cycle = ~10%
07139-015
CH1 500mV M 12.5ns A CH1 920mV
1
C1 FREQUENCY: 36MHz
C1 + DUTY: 49.41%
Figure 15. DIVOUT 36 MHz Waveform, VCO = 360 MHz,
Divide-by-A/2 Selected, A = 5, Duty Cycle = ~50%
ADF4360-9 Data Sheet
Rev. B | Page 10 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches, and SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin at
power-down.
07139-016
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference
frequency divided by R. The VCO frequency equation is
fVCO = B × fREFIN/R
where:
fVCO is the output frequency of the VCO.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
fREFIN is the external reference frequency oscillator.
R COUNTER
The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = B)
and produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs. Two bits in the R
counter latch, ABP2 and ABP1, control the width of the pulse
(see Figure 25).
07139-017
PROGRAMMABLE
DELAY U3
CLR2
Q2D2
U2
CLR1
Q1D1
CHARGE
PUMP
DOWN
UP
HI
HI
U1
ABP1 ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
V
P
Figure 17. PFD Simplified Schematic and Timing (In Lock)
LOCK DETECT
The LD pin outputs a lock detect signal. Digital lock detect is
active high. When lock detect precision (LDP) in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is <15 ns.
When LDP is set to 1, five consecutive cycles of <15 ns phase
error are required to set the lock detect. It stays set high until a
phase error of >25 ns is detected on any subsequent PD cycle.
INPUT SHIFT REGISTER
The digital section of the ADF4360 family includes a 24-bit
input shift register, a 14-bit R counter, and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
Data Sheet ADF4360-9
Rev. B | Page 11 of 24
The truth table for these bits is shown in Tabl e 5. Figure 22
shows a summary of how the latches are programmed. Note
that the test modes latch is used for factory testing and should
not be programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 Control
0 1 R Counter
1 0 N Counter (B)
1 1 Test Modes
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 18, to allow a wide frequency range
to be covered without a large VCO sensitivity (KV) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated.
It is important that the correct write sequence be followed at
power-up. The correct write sequence is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
During band selection, which takes five PFD cycles, the VCO
VTUNE is disconnected from the output of the loop filter and
connected to an internal reference voltage.
0
1.0
0.5
2.5
2.0
1.5
3.5
3.0
80 85 90 10095 105 115110
FREQUENCY (MHz)
V
TUNE
(V)
07139-019
Figure 18. VTUNE, ADF4360-9, L1 and L2 = 270 nH vs. Frequency
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by the BSC1 bit and the BSC2 bit in the R counter
latch. Where the required PFD frequency exceeds 1 MHz, the
divide ratio should be set to allow enough time for correct band
selection. For many applications, it is usually best to set this to 8.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of the inductors used (see the
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
It is strongly recommended that only the 5 mA setting be used.
However, in applications requiring a low VCO frequency, the
high temperature coefficient of some inductors may lead to the
VCO tuning voltage varying as temperature changes. The 7.5 mA
VCO core power setting shows less tuning voltage variation over
temperature in these applications and can be used, provided that
240 Ω resistors are used in parallel with Pin 9 and Pin 10, instead of
the default 470 Ω.
ADF4360-9 Data Sheet
Rev. B | Page 12 of 24
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 19. To
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −9 dBm, −6 dBm,
−3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to VDD and ac coupling into a 50 Ω load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
VCO
RF
OUT
A
RF
OUT
B
BUFFER
07139-020
Figure 19. RF Output Stage
DIVOUT STAGE
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in Figure 23. Figure 20 shows the DIVOUT
section in block diagram form.
R COUNTER OUTPUT
N COUNTER OUTPUT
A COUNTER OUTPUT
DGND
CONTROLMUX DIVOUT
DV
DD
A
COUNTER/2 OUTPUT
07139-018
Figure 20. DIVOUT Circuit
The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,
Pulse Width [seconds] = 1/fVCO (Frequency [Hz])
See Figure 21 for a graphical description. By selecting the
divide-by-2 function, this divided down frequency can in turn
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see Figure 21).
fVCO
fVCO/A (A = 4)
fVCO/2A (A = 4)
07139-021
Figure 21. DIVOUT Waveforms
Data Sheet ADF4360-9
Rev. B | Page 13 of 24
LATCH STRUCTURE
Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
PC1PC2CRD1D2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 D3
CONTROL
BITS
DIVOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
CONTROL LATCH
DB21DB22DB23
POWER-
DOWN 2
POWER-
DOWN 1
COUNTER
RESET
MUTE-TILL-
LD
RESERVED
RESERVED
CP GAIN
CP
THREE-
STATE
PHASE
DETECTOR
POLARITY
PD2RSVRSV
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
CONTROL
BITS
5-BIT DIVOUT
13-BIT B COUNTER
N COUNTER LATCH
DB21DB22DB23
CP GAIN
RESERVED
RESERVED
RESERVED
CPGRSVRSV
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
CONTROL
BITS
ANTI-
BACKLASH
PULSE WIDTH
14-BIT REFERENCE COUNTER
BAND
SELECT
CLOCK
R COUNTER LATCH
DB21
DB22DB23
RESERVED
RESERVED
TEST MODE
BIT
LOCK
DETECT
PRECISION
BSC2RSVRSV
07139-034
Figure 22. Latch Structure
ADF4360-9 Data Sheet
Rev. B | Page 14 of 24
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
PC1PC2CRD1D2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 D3
CONTROL
BITS
DIVOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21DB22DB23
POWER-
DOWN 2
POWER-
DOWN 1
COUNTER
RESET
MUTE-TILL-
LD
RESERVED
RESERVED
CP GAIN
CP
THREE-
STATE
PHASE
DETECTOR
POLARITY
PD2RSVRSV
CR
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
PC2
0
0
10
CORE POWER LEVEL
2.5mA
5mA (RECOMMENDED)
7.5mA
PC1
0
1
1 1 10mA
CP
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
PDP
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPG
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MTLD
0
1
MUTE-TIL-LOCK DETECT
DISABLED
ENABLED
D3 D2 D1 MUXOUT
DVDD
000
001
010
011
100
101
110
111
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
A CNTR/2 OUT
A CNTR OUT
DGND
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
CPI6 CPI5 CPI4 ICP (mA)
CPI3 CPI2 CPI1 4.7kΩ
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PL2 PL1 OUTPUT POWER LEVEL
CURRENT USING TUNED LOAD
–9dBm
–6dBm
–3dBm
0dBm
USING 50Ω TO VVCO
–19dBm
–15dBm
–12dBm
–9dBm
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
07139-022
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
Figure 23. Control Latch
Data Sheet ADF4360-9
Rev. B | Page 15 of 24
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
CONTROL
BITS
5-BIT DIVOUT13-BIT B COUNTER
DB21DB22DB23
CP GAIN
RESERVED
RESERVED
CPGRSVRSV
B13
0
0
0
0
.
.
.
1
1
1
1
B12
0
0
0
0
.
.
.
1
1
1
1
B11
0
0
0
0
.
.
.
1
1
1
1
............
............
............
............
............
............
............
............
............
............
............
B3
0
0
1
0
.
.
.
1
1
1
1
B2
0
0
1
1
.
.
.
0
0
1
1
B1
0
1
1
0
.
.
.
0
1
0
1
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
3
NOT ALLOWED
.
.
.
8188
8189
8190
8191
A5
0
0
0
0
.
.
.
1
1
1
1
A4
0
0
0
0
.
.
.
1
1
1
1
............
............
............
............
............
............
............
............
............
............
............
A2
0
0
1
1
.
.
.
0
0
1
1
A1
0
1
1
0
.
.
.
0
1
0
1
OUTPUT DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
3
2
.
.
.
28
29
30
31
CP GAIN OPERATION
0 CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
1 CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
07139-023
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
THIS BIT IS NOT
USED BY THE
DEVICE AND IS A
DON'T CARE BIT.
Figure 24. N Counter Latch
ADF4360-9 Data Sheet
Rev. B | Page 16 of 24
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21DB22DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
RESERVED
BSC2RSVRSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14 R13 R12 R3 R2 R1 DIVIDE RATIO
.......... 000 0
00 0
00 0
00 0
01 1
.......... 0 1 0 2
.......... 0 1 1 3
.......... 1 0 0 4
.......... ... .
.. .
.. .
.. .
.......... . . . .
.......... . . . .
.......... 111 1
11 1
11 1
11 1
0 0 16380
.......... 1 0 1 16381
.......... 1 1 0 16382
.......... 1 1 1 16383
THESE BITS ARE
NOT USED BY
THE DEVICE
AND ARE DON'T
CARE BITS.
07139-024
LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
00 3.0ns
01 1.3ns
10 6.0ns
11 3.0ns
BSC2 BSC1 BAND SELECT CLOCK DIVIDER
001
01 2
104
118
Figure 25. R Counter Latch
Data Sheet ADF4360-9
Rev. B | Page 17 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-9 after
power-up is as follows:
1. R Counter Latch
2. Control Latch
3. N Counter Latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AVDD, DVDD, and VVCO pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-9 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the CN pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-9 VCO. The
recommended value of this capacitor is 10 μF. Using this
value requires an interval of ≥15 ms between the latching in
of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in Table 6.
Table 6. CN Capacitance vs. Interval and Phase Noise
Open-Loop Phase Noise @ 10 kHz Offset
CN Value
Recommended Interval Between
Control Latch and N Counter Latch L1 and L2 = 18.0 nH L1 and L2 = 110.0 nH L1 and L2 = 560.0 nH
10 μF ≥15 ms −100 dBc/Hz −97 dBc/Hz −99 dBc/Hz
440 nF ≥600 μs −99 dBc/Hz −96 dBc/Hz −98 dBc/Hz
CLK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
07139-033
Figure 26. Power-Up Timing
ADF4360-9 Data Sheet
Rev. B | Page 18 of 24
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N counter
latch during power-down, the part locks at the correct frequency
because the part is already in the correct frequency band. The
lock time depends on the value of capacitance on the CN pin,
which is <15 ms for 10 μF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 μs.
The N counter value cannot be changed while the part is in
power-down because the part may not lock to the correct
frequency on power-up. If it is updated, the correct program-
ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Figure 23
shows the input data format for programming the control latch.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded in PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When a power-down is activated (either
synchronous or asynchronous mode), the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital lock detect circuitry is reset.
• The RF outputs are debiased to a high impedance state.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1. CPI6, CPI5, and CPI4 determine Current
Setting 2 (see the truth table in Figure 23).
Output Power Level
Bit PL1 and Bit PL2 set the output power level of the VCO (see
the truth table in Figure 23).
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360 family is the mute-
till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit (DB9) puts the charge pump into three-state mode
when programmed to a 1. For normal operation, it should be
set to 0.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.
DIVOUT Control
The on-chip multiplexer is controlled by D3, D2, and D1 (see
the truth table in Figure 23).
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The
recommended setting is 5 mA. The 7.5 mA setting is
permissible in some applications (see the truth table in Figure 23).
Data Sheet ADF4360-9
Rev. B | Page 19 of 24
N COUNTER LATCH
Figure 24 shows the input data format for programming the
N counter latch.
5-Bit Divider
A5 to A1 program the output divider. The divide range is 2 (00010)
to 31 (11111). If unused, this divider should be set to 0. The output
or the output divided by 2 is available at the DIVOUT pin.
Reserved Bits
DB23, DB22, and DB7 are spare bits and are designated as
reserved. They should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00 … 0011) to 8191 (11 … 111).
Overall Divide Range
The overall VCO feedback divide range is defined by B.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the
control latch. The bit always reflects the latest value written to it,
whether this is through the control latch or the N counter latch.
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Figure 25 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is
1 (00 … 001) to 16,383 (111 … 111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with <15 ns phase error for entering the locked
state. With LDP at 1, five cycles are taken; with LDP at 0, three
cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
Band Select Clock
These bits (DB20 and DB21) set a divider for the band select
logic clock input. The output of the R counter is, by default, the
value used to clock the band select logic; if this value is too high
(>1 MHz), a divider can be switched on to divide the R counter
output to a smaller value (see Figure 25). A value of 8 is
recommended.
Reserved Bits
DB23 to DB22 are spare bits that are designated as reserved.
They should be programmed to 0.
ADF4360-9 Data Sheet
Rev. B | Page 20 of 24
APPLICATIONS
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-9 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 27 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
The lowest center frequency of oscillation possible is approximately
65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
()
EXT
OL
f+
=nH0.9pF9.32π
1
where:
fO is the center frequency.
LEXT is the external inductance.
0
150
50
100
350
250
300
200
450
400
0 100 200 300 400 600500
INDUCTANCE (nH)
FREQUENCY (MHz)
07139-025
Figure 27. Output Center Frequency vs. External Inductor Value
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 28 shows a graph of the tuning sensitivity (in MHz/V)
vs. the inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the previous equation; that is, because the
inductance increased, the change in capacitance from the
varactor has less of an effect on the frequency.
0
4
2
10
8
6
12
0 100 200 300 400 600500
INDUCTANCE (nH)
SENSITIVITY (MHz/V)
07139-026
Figure 28. Tuning Sensitivity vs. Inductance
ENCODE CLOCK FOR ADC
Analog-to-digital converters (ADCs) require a sampling clock
for their operation. Generally, this is provided by TCXO or VCXOs,
which can be large and expensive. The frequency range is usually
quite limited. An alternative solution is the ADF4360-9, which can
be used to generate a CMOS clock signal suitable for use in all
but the most demanding converter applications.
Figure 29 shows an ADF4360-9 with a VCO frequency of
320 MHz and a DIVOUT frequency of 80 MHz. Because a 50%
duty cycle is preferred by most sampling clock circuitry, the A/
mode is selected. Therefore, A is programmed to 2, giving an
overall divide value of 4. The
2
to
z
ter of <1.5 ps, which is more than adequate
for the application.
AD9215-80 is a 10-bit, 80 MSPS
ADC that requires an encode clock jitter of 6 ps or less. The
ADF4360-9 takes a 10 MHz TCXO frequency and divides this
1 MHz; therefore, R = 10 is programmed and N = 320 is
programmed
to achieve a VCO frequency of 320 MHz. The resultant 80 MH
CMOS signal has a jit
TCXO
10MHz
ADF4360-9
80MHz
470Ω
470Ω
21nH
21nH
LPF
SIGNAL
GENERATOR
HC-ADC-
EVALA-SC
USB
SPI
PC
ENCODE
CLOCK
AD9215-80
A
IN
07139-036
Figure 29. The ADF4360-9 Used as an Encode Clock for an ADC
Data Sheet ADF4360-9
Rev. B | Page 21 of 24
GSM TEST CLOCK
Figure 30 shows the ADF4360-9 used to generate three different
frequencies at DIVOUT. The frequencies required are 45 MHz,
80 MHz, and 95 MHz. This is achieved by generating 360 MHz,
320 MHz, and 380 MHz and programming the correct A divider
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT
mode is selected. This means that A values of 4, 2, and 2 are
selected, respectively, for each of the output frequencies
previously mentioned.
The low-pass filter was designed using ADIsimPLL™ for a
channel spacing of 1 MHz and an open-loop bandwidth of
40 kHz. Larger PFD frequencies can be used to reduce in-band
noise and, therefore, rms jitter. However, for the purposes of
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.
Two 21 nH inductors are required for the specified frequency
range. The reference frequency is from a 20 MHz TCXO from
Fox; therefore, an R value of 20 is programmed. Taking into
account the high PFD frequency and its effect on the band
select logic, the band select clock divider is enabled. In this case,
a value of 8 is chosen. A very simple shunt resistor and dc-blocking
capacitor complete the RF output stage. Because these outputs
are not used, they are terminated in 50 Ω resistors. This is
recommended for circuit stability. Leaving the RF outputs
open is not recommended.
The CMOS level output frequency is available at DIVOUT. If
the frequency has to drive a low impedance load, a buffer is
recommended.
SPI-COMPATIBLE SERIAL BUS
ADF4360-9
V
VCO
V
VCO
FOX
801BE-160
20MHz
V
VCO
CPGND AGND DGND L1 L2 RF
OUT
B
RF
OUT
A
CP
DIVOUT
1nF
150pF
21nH470Ω
21nH
470Ω
56pF
2.2nF
51Ω
100pF
100pF
1nF1nF
10µF
4.7kΩ
5.6kΩ
12kΩ
R
SET
C
C
LE
DATA
CLK
REF
IN
C
N
V
TUNE
AV
DD
DV
DD
LD
5
4
7
23212
6
14
16
17
18
19
13
1 3 8 91011 22 15
12
51Ω
51Ω
51Ω
51Ω
V
VDD
LOC
K
DETECT
07139-027
20
24
Figure 30.GSM Test Clock
ADF4360-9 Data Sheet
Rev. B | Page 22 of 24
INTERFACING
The ADF4360 family has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that are clocked into
the appropriate register on each rising edge of CLK are transferred
to the appropriate latch. See Figure 2 for the timing diagram
and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz, or
one update every 1.2 μs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 31 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. After the
third byte is written, the LE input should be brought high to
complete the transfer.
07139-028
ADuC812
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 31. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are used to detect lock (MUXOUT
configured as lock detect and polled by the port input). When
operating in the described mode, the maximum SCLOCK rate
of the ADuC812 is 4 MHz. This means that the maximum rate
at which the output frequency can be changed is 166 kHz.
ADSP-21xx Interface
Figure 32 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.
07139-029
ADSP-21xx
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
TFS
I/O PORTS
Figure 32. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the autobuffered mode, and write to
the transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The leads on the chip scale package (CP-24-2) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The lead should be centered on the pad to ensure that
the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated into the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 ounce of copper to plug the via.
The user should connect the printed circuit thermal pad to AGND.
This is internally connected to AGND.
Data Sheet ADF4360-9
Rev. B | Page 23 of 24
The recommended value of this inductor changes with the VCO
center frequency. Figure 35 shows a graph of the optimum
inductor value vs. center frequency.
OUTPUT MATCHING
There are a number of ways to match the VCO output of the
ADF4360-9 for optimum operation; the most basic is to use a
51 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected
in series, as shown in Figure 33. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in the circuit in Figure 33 typically gives
−9 dBm output power into a 50 Ω load.
CENTER FREQUENCY (MHz)
INDUCTANCE (nH)
300
250
150
200
100
0
50
0 100 200 300 500400
07139-032
100pF
07139-030
RF
OUT
V
VCO
50Ω
51Ω
Figure 33. Simple Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power.
Figure 35. Optimum Shunt Inductor vs. Center Frequency
Both complementary architectures can be examined using the
EV-ADF4360-9EB1Z evaluation board. If the user does not
need the differential outputs available on the ADF4360-9, the
user should either terminate the unused output with the same
circuitry as much as possible or combine both outputs using a
balun. Alternatively, instead of the LC balun, both outputs can
be combined using a 180° rat-race coupler.
Experiments have shown that the circuit shown in Figure 34
provides an excellent match to 50 Ω over the operating range of
the ADF4360-9. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-9 using the
recommended shunt inductor, followed by a 100 pF dc-blocking
capacitor.
L
100pF
07139-031
RF
OUT
V
VCO
50Ω
If the user is only using DIVOUT and does not use the RF
outputs, it is still necessary to terminate both RF output pins
with a shunt inductor/resistor to VVCO and also a dc bypass
capacitor and a 50 Ω load. The circuit in Figure 33 is probably
the simplest and most cost-effective solution. It is important
that the load on each pin be balanced because an unbalanced
load is likely to cause stability problems. Terminations should
be identical as much as possible.
Figure 34. Optimum Output Stage
ADF4360-9 Data Sheet
Rev. B | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGD-2
08-18-2010-A
1
0.50
BSC
PIN1
INDICATOR
2.50 BCS
0.50
0.40
0.30
TOP VIEW
12° MAX 0.70 MAX
0.65 TYP
SEATING
PLANE
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
2.45
2.30 SQ
2.15
24
7
19
12
13
18
6
(BOTTOM VIEW)
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
3.75 BSC
SQ
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Frequency Range Package Option
ADF4360-9BCPZ −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
ADF4360-9BCPZRL −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
ADF4360-9BCPZRL7 −40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
EV-ADF4360-9EB1Z Evaluation Board
1 Z = RoHS Compliant Part.
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07139-0-2/12(B)
