© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2 1Publication Order Number:
NCP5006/D
NCP5006
Compact Backlight LED
Boost Driver
The NCP5006 is a high efficiency boost converter operating in
current loop, based on a PFM mode, to drive White LED. The current
mode regulation allows a uniform brightness of the LEDs. The chip
has been optimized for small ceramic capacitors, capable to supply
up to 1.0 W output power.
Features
•2.7 to 5.5 V Input Voltage Range
•Vout to 24 V Output Compliance Allows up to 5 LEDs Drive in
Series
•Built−in Overvoltage Protection
•Inductor Based Converter brings up to 90% Efficiency
•Constant Output Current Regulation
•0.3 mA Standby Quiescent Current
•Includes Dimming Function (PWM)
•Enable Function Driven Directly from Low Battery Voltage Source
•Automatic LEDs Current Matching
•Thermal Shutdown Protection
•All Pins are Fully ESD Protected
•Low EMI Radiation
•Pb−Free Package is Available
Typical Applications
•LED Display Back Light Control
•Keyboard Back Light
•High Efficiency Step Up Converter
NCP5006SNT1 TSOP−5 3000 Tape & Ree
l
TSOP−5
SN SUFFIX
CASE 483
PIN CONNECTIONS
Device Package Shipping†
ORDERING INFORMATION
NCP5006SNT1G TSOP−5
(Pb−Free) 3000 Tape & Ree
l
MARKING
DIAGRAM
1
5
DCS = Device Code
A = Assembly Location
Y = Year
W = W ork Week
G= Pb−Free Package
1
5
DCSAYWG
G
1
3EN
Vout
2GND
FB 4
Vbat
5
(Top View)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
http://onsemi.com
(Note: Microdot may be in either location)
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Figure 1. Typical Application
GND
U1
EN
Vbat
4Vbat
GNDGND
FB
NCP5006
5
Vbat
Vout
C1
4.7 mF
GND
2
31D1
MBR0530
GND
15 W
R1 D6
LWT67C
D5
LWT67C
D4
LWT67C
D3
LWT67C
D2
LWT67C
L1
22 mH
C2
1.0 mF
Figure 2. Block Diagram
Thermal Shutdown Current Sense
Vsense
CONTROLLER
100 k
GND
4
EN
3
FB
+
−
300 k
+200 mV
Band Gap
Q1
2GND
GND
1Vout
5Vbat
Vbat
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PIN FUNCTION DESCRIPTION
Pin Pin Name Type Description
1 Vout POWER This pin is the power side of the external inductor and must be connected to the
external Schottky diode. It provides the output current to the load. Since the boost
converter operates in a current loop mode, the output voltage can range up to
+24 V but shall not extend this limit. However, if the voltage on this pin is higher
than the Over Voltage Protection threshold (OVP) the device comes back to
shutdown mode. To restart the chip, one must either send a Low to High
sequence on Pin EN, or switch off the Vbat supply. A capacitor must be used on
the output voltage to avoid false triggering of the OVP circuit. This capacitor
should be 1.0 mF minimum. Ceramic type, (ESR <100 mW), is mandatory to
achieve the high end efficiency. This capacitor limits the noise created by the fast
transients present in this circuitry. In order to limit the inrush current and to
operate with an acceptable start−up time, it is recommended to use any value
between 1.0 mF and 8.2 mF capacitor maximum. Care must be observed to avoid
EMI through the PCB copper tracks connected to this pin.
2 GND POWER This pin is the system ground for the NCP5006 and carries both the power and
the analog signals. High quality ground must be provided to avoid spikes and/or
uncontrolled operation. Care must be observed to avoid high−density current flow
in a limited PCB copper track. Ground plane technique is recommended.
3 FB ANALOG INPUT This pin provides the output current range adjustment by means of a sense
resistor connected to the analog control or with a PWM control. The dimming
function can be achieved by applying a PWM voltage technique to this pin (see
Figure 29). The current output tolerance depends upon the accuracy of this
resistor. Using a "5% metal film resistor or better, yields a good enough output
current accuracy.
Note: A built−in comparator switch OFF the DC/DC converter if the voltage
sensed across this pin and ground is higher than 700 mV (typical).
4 EN DIGITAL INPUT This is an Active−High logic input which enables the boost converter. The built−in
pull down resistor disables the device when the EN pin is left open. The LED
brightness can be controlled by applying a pulse width modulated signal to the
enable pin (see Figure 31).
5 Vbat POWER The external voltage supply is connected to this pin. A high quality reservoir
capacitor must be connected across Pin 1 and Ground to achieve the specified
output voltage parameters. A 4.7 mF/6.3 V, low ESR capacitor must be connected
as close as possible across Pin 5 and ground Pin 2. The X5R or X7R ceramic
MURATA types are recommended. The return side of the external inductor shall
be connected to this pin. Typical application will use a 22 mH, size 1008, to handle
the 1.0 to 100 mA max output current range. On the other hand, when the desired
output current is above 20 mA, the inductor shall have an ESR < 1.5 W to achieve
a good efficiency over the Vbat range.
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MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Vbat 6.0 V
Output Power Supply Voltage Compliance Vout 28 V
Digital Input Voltage
Digital Input Current EN −0.3 < Vin < Vbat + 0.3
1.0 V
mA
ESD Capability (Note 1)
Human Body Model (HBM)
Machine Model (MM)
VESD 2.0
200 kV
V
TSOP−5 Package
Power Dissipation @ TA = +85°C (Note 2)
Thermal Resistance, Junction−to−Air PD
RqJA
160
250 mW
°C/W
Operating Ambient Temperature Range TA−25 to +85 °C
Operating Junction Temperature Range TJ−25 to +125 °C
Maximum Junction Temperature TJmax +150 °C
Storage Temperature Range Tstg −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may af fect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) "200 V per JEDEC standard: JESD22−A115
2. The maximum package power dissipation limit must not be exceeded.
3. Latch−up current maximum rating: "100 mA per JEDEC standard: JESD78.
4. Moisture Sensivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
POWER SUPPLY SECTION (Typical values are referenced to T A = +25°C, Min & Max values are referenced −25°C to +85°C ambient
temperature, unless otherwise noted.)
Rating Pin Symbol Min Typ Max Unit
Power Supply 4 Vbat 2.7 − 5.5 V
Output Load Voltage Compliance 5 Vout 21 24 − V
Continuous DC Current in the Load @ Vout = 3xLED, L = 22 mH,
ESR < 1.5 W, Vbat = 3.60 V 5 Iout 50 − − mA
Stand By Current, @ Iout = 0 mA, EN = L, Vbat = 3.6 V 4 Istdb − 0.3 − mA
Stand By Current, @ Iout = 0 mA, EN = L, Vbat = 5.5 V 4 Istdb − 0.8 3.0 mA
Inductor Discharging Time @ Vbat = 3.6 V, L = 22 mH, 3xLED,
Iout = 10 mA 4 Toffmax − 320 − ns
Thermal Shutdown Protection − TSD − 160 − °C
Thermal Shutdown Protection Hysteresis − TSDH − 30 − °C
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ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −25°C to +85°C ambient
temperature, unless otherwise noted.)
Rating Pin Symbol Min Typ Max Unit
High Level Input Voltage
Low Level Input Voltage 4 EN 1.3
−−
−−
0.4 V
V
EN Pull Down Resistor 4 REN − 100 − kW
Feedback Voltage Threshold 3 FB 185 200 225 mV
Output Current Stabilization Time Delay following a DC/DC Start−up,
@ Vbat = 3.60 V, L = 22 mH, Iout = 20 mA 1 Ioutdly − 100 − ms
Internal Switch ON Resistor @ Tamb = +25°C 1 QRDSON − 1.7 − W
5. The overall tolerance depends upon the accuracy of the external resistor.
ESD PROTECTION
The NCP5006 includes silicon devices to protect the pins
against the ESD spikes voltages. To cope with the different
ESD voltages developed in the applications, the built−in
structures have been designed to handle "2.0 kVin Human
Body Model (HBM) and "200 V in Machine Model (MM)
on each pin.
DC/DC OPERATION
The DC/DC converter is designed to supply a constant
current to the external load, the circuit being powered from
a standard battery supply. Since the regulation is made by
means of a current loop, the output voltage will varies
depending upon the dynamic impedance presented by the
load.
Considering high intensity LED, the output voltage can
range from a low 6.40 V (two LED in series biased with a
low current), up to 21 V, the voltage compliance the chip
can sustain continuously.
The basic DC/DC structure is depicted in Figure 3. With
a 28 V maximum rating voltage capability, the power
device can accommodate high voltage source without any
leakage current downgrading.
POR
LOGIC
CONTROL
TIME_OUT
ZERO_CROSSING
RESET
GND
Vdsense
Q1 Vds
L1
22 mH
Vbat
D1
C1
D5 D4 D3 D2
GND
Vs
R2
xR
GND
R1
C2
+
−
GND
Vref
V(Ipeak)
+
−
Vdsense
Figure 3. Basic DC/DC Converter Structure
1
3
1.0 mF
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Basically, the chip operates with two cycles:
Cycle #1: time t1, the energy is stored into the inductor
Cycle #2: time t2, the energy is dumped to the load
The POR signal sets the flip−flop and the first cycle takes
place. When the current hits the peak value, defined by the
error amplifier associated to the loop regulation, the
flip−flop resets, the NMOS is deactivated and the current
is dumped into the load. Since the timings depend on the
environment, the internal timer limits the toff cycle to
320 ns (typical), making sure the system operates in a
continuous mode to maximize the energy transfer.
Figure 4. Basic DC−DC Operation
First Start−Up Normal Operation
IL
0 mA
Ids
0 mA
Io
0 mA
Iv
Ipeak
t
t
t
t1 t2
Based on the data sheet, the current flowing into the
inductor is bounded by two limits:
•Ipeak Value: Internally fixed to 350 mA typical
•Iv Value: Limited by the fixed Toff time built in the
chip (320 ns typical)
The system operates in a continuous mode as depicted in
Figure 4 and t1 and t2 times can be derived from basic
equations. (Note: The equations are for theoretical analysis
only, they do not include the losses.)
L+E*dI
dt (eq. 1)
Let Vbat = E, then:
t1 +(Ip *Iv) * L
Vbat (eq. 2)
t2 +(Ip *Iv) * L
Vo *Vbat (eq. 3)
Since t2 = 320 ns typical and Vo = 21 V maximum, then
(assuming a typical Vbat = 3.0 V):
DI+t2 * (Vo *Vbat)
L(eq. 4)
DImax +320 ns * (21−3.0)
22 mH+261 mA
Of course, from a practical stand point, the inductor must
be sized to cope with the peak current present in the circuit
to avoid saturation of the core. On top of that, the ferrite
material shall be capable to operate at high frequency
(1.0 MHz) to minimize the Foucault’s losses developed
during the cycles.
The operating frequency can be derived from the
electrical parameters. Let V = Vo − Vbat, rearranging
Equation 1:
ton +dI *L
E(eq. 5)
Since toff is nearly constant (according to the 320 ns
typical time), the dI is constant for a given load and
inductance value. Rearranging Equation 5 yields:
ton +
V*dt
L*L
E(eq. 6)
Let E = Vbat, and Vopk = output peak voltage, then:
ton +(Vopk *Vbat)*dt
Vbat (eq. 7)
Finally, the operating frequency is:
f+1
ton )toff (eq. 8)
The output power supplied by the NCP5006 is limited to
one watt: Figure 5 shows the maximum power that can be
delivered by the chip as a function of the output voltage.
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1200
6
400
53
P
out
(mW)
0
Vbat (V)
200
800
1000
600
24
Pout = f(Vbat) @ Rsense = 2.0 W
4 LED
120
40
Iout (mA)
0
Vbat (V)
20
80
100
60
3.0 4.0 5.02.5 3.5 4.5 5.5
Figure 5. Maximum Output Power as a Function of
the Battery Supply Voltage Figure 6. Typical Inductor Peak Current as a
Function of Vbat Voltage
Figure 7. Maximum Output Current as a Function of Vbat
350
432
Ipeak (mA)
150
400
Vbat (V)
200
300
5
250
6
Test conditions: L = 22 mH, Rsense = 10 W, Tamb = +20°C
Test conditions: L = 22 mH, Rsense = 2.0 W, Tamb = +25°C
2 LED
3 LED
4 LED
5 LED
P
out
= f(V
bat
) @ Rs = 2.0
W
I
peak
= f(V
bat
) @ L
out
= 22
m
H
3 LED
2 LED
5 LED
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Output Current Range Set−Up
The current regulation is achieved by means of an external sense resistor connected in series with the LED string.
CONTROLLER
GND
3
FB
GND
1
Vout D1
Load
Q1
Figure 8. Output Current Feedback
Vbat L1
22 mH
R1
xW
The current flowing through the LED creates a voltage
drop across the sense resistor R1. The voltage drop is
constantly monitored internally, and maximum peak
current allowed in the inductor is set accordingly in order
to keep constant this voltage drop (and thus the current
flowing through the LED). For example, should one need
a 10 mA output current, the sense resistor should be sized
according to the following equation:
R1+Feedback Threshold
Iout +200 mV
10 mA +20 W(eq. 9)
A standard 5% tolerance resistor, 22 W SMD device,
yields 9.09 mA, good enough to fulfill the back light
demand. The typical application schematic diagram is
provided in Figure 9.
Figure 9. Basic Schematic Diagram
GND
EN
2 1
5
Vout
Vbat
NCP5006
L1
22 mH
Vbat
C1
4.7 mF
GND
D6 D5 D4 D3
U1
4
D2
GND
3
GND R1
22 W
D1
MBR0530
GND
C2
1.0 mF
FB
Pulse
LWT67C LWT67C LWT67C LWT67C LWT67C
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Output Load Drive
In order to optimize the built−in Boost capabilities, one
shall operate the NCP5006 in the continuous output current
mode. Such a mode is achieved by using and external
reservoir capacitor (see Table 1) across the LED.
At this point, the peak current flowing into the LED
diodes shall be within the maximum ratings specified for
these devices. Of course, pulsed operation can be achieved,
due to the EN signal Pin 4, to force high current into the
LED when necessary.
The Schottky diode D1, associated with capacitor C2
(see Figure 9), provides a rectification and filtering
function.
When a pulse−operating mode is acceptable:
•A PWM mode control can be used to adjust the output
current range by means of a resistor and a capacitor
connected across FB pin. On the other hand, the
Schottky diode can be removed and replaced by at
least one LED diode, keeping in mind such LED shall
sustain the large pulsed peak current during the
operation.
TYPICAL OPERATING CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
YIELD (%)
5 LED/10 mA 3 LED/10 mA
4 LED/10 mA
2 LED/10 mA
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
YIELD (%)
5 LED/4 mA 3 LED/4 mA
4 LED/4 mA
2 LED/4 mA
Figure 10. Overall Efficiency vs. Power Supply @
Iout = 4.0 mA, L = 22 mHFigure 11. Overall Efficiency vs. Power Supply @
Iout = 10 mA, L = 22 mH
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Vbat (V)
YIELD (%)
5 LED/20 mA
3 LED/20 mA
4 LED/20 mA 2 LED/20 mA
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
Vbat (V)
YIELD (%)
5 LED/15 mA
3 LED/15 mA
4 LED/15 mA 2 LED/15 mA
Figure 12. Overall Efficiency vs. Power Supply @
Iout = 15 mA, L = 22 mHFigure 13. Overall Efficiency vs. Power Supply @
Iout = 20 mA, L = 22 mH
Yield = f(Vbat) @ Iout = 4.0 mA/Lout = 22 mH Yield = f(Vbat) @ Iout = 10 mA/Lout = 22 mH
Yield = f(Vbat) @ Iout = 15 mA/Lout = 22 mH Yield = f(Vbat) @ Iout = 20 mA/Lout = 22 mH
Vbat (V) Vbat (V)
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Figure 14. Overall Efficiency vs. Power Supply @
Iout = 40 mA, L = 22 mHFigure 15. Feedback Voltage Stability
YIELD (%)
Vbat (V)
205
200
FEEDBACK VOLTAGE (mV)
195
TEMPERATURE (°C)
199
202
203
201
020 10
0
198
197
196
−40 40−20 60 80
204
5
0
FEEDBACK VARIATION (%)
−5
TEMPERATURE (°C)
−1
2
3
1
0 20 100
−2
−3
−4
−40 40−20 60 80
4
Vbat = 3.1 V thru 5.5 V
Vbat = 3.1 V thru 5.5 V
Figure 16. Feedback Voltage Variation
0
10
20
30
40
50
60
70
80
90
100
2.50 3.00 3.50 4.00 4.50 5.00 5.50
5 LED/40 mA
3 LED/40 mA
4 LED/40 mA
2 LED/40 mA
Feedback V ariation vs. Temperature
Feedback Variation vs. Nominal
(Vbat = 3.0 V, 6.0 V, T = 255C)
Figure 17. Standby Current
1.4
2.7
IStby (mA)
0.0
Vbat (V)
0.6
1.0
0.8
5
.5
0.4
0.2
1.2 −40°C thru 125°C
3.3 3.9 4.5 5.1
Standby Current vs. Vbat
4 LED
5 LED
Figure 18. Typical Operating Frequency
0
0.5
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
2 LED
f (mHz)
Vbat (V)
3 LED
Figure 19. Overvoltage Protection
26
24
−40
OVERVOLTAGE PROTECTION (V)
22
TEMPERATURE (°C)
25
0 100
23
40 80
Vbat = 5.5 V
Vbat = 2.7 V Vbat = 3.6 V
20 13
0
−20 60 120
Frequency = f(Vbat) @ Iout = 20 mA−Lout = 22 mH OVP vs. Temperature
Yield = f(V
bat
) @ I
out
= 40 mA/L
out
= 22
m
H
All curve conditions: L = 22 mH, Cin = 4.7 mF, Cout = 1.0 mF,
Typical curve @ T° = +25°C
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Figure 20. Typical Power Up Response
Figure 21. Typical Start−Up Inductor Current and Output Voltage
TYPICAL OPERATING WAVEFORMS
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Inductor
Current
Vout
Vout
Inductor
Current
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Figure 22. Typical Inductor Current
Figure 23. Typical Output Voltage Ripple
TYPICAL OPERATING WAVEFORMS
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Inductor
Current
Inductor
Current
Vout Ripple
50 mV/div
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Figure 24. Typical Output Peak Voltage
TYPICAL OPERATING WAVEFORMS
Test Conditions: L = 22 mH, Iout = 15 mA, Vbat = 3.6 V, Ambient Temperature
Output Voltage
Inductor Current
Figure 25. Efficiency as a Function of Vbat and Inductor ESR
78.00
80.00
82.00
84.00
86.00
88.00
90.00
92.00
3 3.5 4 4.5 5 5.5
Vbat (V)
EFFICIENCY (%)
ESR = 1.3 W
ESR = 0.3 W
NCP5006: Efficiency = f(ESR) @ 5 LED, ILed = 20 mA
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Figure 26. Noise Returned to the Battery
Test Conditions: Vbat = 3.6 V, Iout = 20 mA, string of 3 LED (OSRAM LWT67C)
Figure 27. Relative EMI Over 100 kHz − 30 MHz Bandwidth
10.00
1.00
0.10
0.01 10001001010.1 FREQUENCY (MHz)
NOISE (mV/SQR/Hz)
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TYPICAL APPLICATIONS CIRCUITS
Standard Feedback
The standard feedback provides a constant current to the
LED, independently of the Vbat supply and number of LED associated in series. Figure 28 depicts a typical application
to supply 13 mA to the load.
Figure 28. Basic DC Current Mode Operation with Analog Feedback
EN
1
5
Vout
Vbat
R1
NCP5006
L1
22 mH
Vbat
C1
4.7 mF
D6 D5 D4 D3
U1
4
D2
Vbat
2
GND GND
FB
3
D1
MBR0530
15 W
GND GND
C2
1.0 mF
LWT67C
GND
LWT67C LWT67C LWT67C LWT67C
PWM Operation
The analog feedback Pin 3 provides a way to dim the
LED by means of an external PWM signal as depicted in
Figure 29. By optimizing the internal high impedance
presented by the FB pin, one can set up a simple R/C
network to accommodate such a dimming function. Two
modes of operation can be considered:
•Pulsed mode, with no filtering
•Averaged mode with filtering capacitor
Although the pulsed mode will provide a good dimming
function, from a human eye standpoint, it will continuously
start and stop the converter, yielding high transients . These
transients might generate spikes dif ficult to filter out in the
rest of the application, a situation not recommended. The
output current depends upon the duty cycle of the signal
presented to the node Pin 3: this is very similar to the digital
control discussed in Figure 31.
The average mode yields a noise free operation since the
converter operates continuously, together with a very good
dimming function. The cost is an extra resistor and one
extra capacitor, both being low cost parts.
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Figure 29. Basic DC Current Mode Operation with PWM Control
EN
1
5
Vout
Vbat
R1
NCP5006
L1
22 mH
Vbat
C1
4.7 mF
U1
4
Vbat
2
GND GND
FB
3
D1
MBR0530
10 W
GND
GND
C2
1.0 mF
R4
5.6 k
R3
10 k
GND
C3
100 nF
Sense Resistor
R2
150 k
PWM
Average Network
NOTE: RC filter R2 and C3 is optional (see text)
GND
D6 D5 D4 D3 D2
LWT67C LWT67C LWT67C LWT67C LWT67C
To implement such a function, let consider the feedback
input as an operational amplifier with a high impedance
input (reference schematic Figure 29). The analog loop
will keep going to balance the current flowing through the
sense resistor R1 until the feedback voltage is 200 mV. An
extra resistor (R4) isolates the FB node from low resistance
to ground, making possible to add an external voltage to
this pin.
The time constant R2/C3 generates the voltage across C3,
added to the node Pin 1, while R2/R3/R4/R1/C3 create the
discharge time constant. In order to minimize the pick up
noise at FB node, the resistors shall have relative medium
value, pref erab ly well below 1 .0 MW. Consequently, let R2 =
150 k, R3 = 10 k and R4 = 5.6 k. On the other hand, the
feedback delay to control the luminosity of the LED shall be
acceptable by the user, 10 ms or less being a good
compromise. The time constant can now be calculated based
on a 400 mV offset voltage at the C3/R2/R3 node to force
zero current to the LED. Assuming the PWM signal comes
from a standard gate powered by a 3.0 V supply, running at
10 kHz, then a f ull d imming o f the LED can b e achieved w ith
a 95% spa n of the Dut y Cyc le signal. Figure 30 depicts the
behavior under such PWM analog mode.
Figure 30. Operation with Analog PWM, f = 10 kHz, DC = 25%
PWM
VFB
VPWM
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Digital Control
Due to the EN pin, a digitally controlled luminosity can
be implemented by providing a PWM signal to this pin (see
Figure 31). The output current depends upon the Duty
Cycle, but care must be observed as the DC/DC converter
is continuously pulsed ON/OFF and noise are likely to be
generated.
Figure 31. Typical Semi−Pulsed Mode of Operation
EN
1
5
Vout
Vbat
R1
NCP5006
L1
22 mH
Vbat
C1
4.7 mF
GND
U1
4
2
GND GND
FB
3
D1
MBR0530
22 W
GND GND
Pulse
C2
1.0 mF
NOTE: Pulse width and frequency depends upon the application constraints.
D6 D5 D4 D3 D2
LWT67C LWT67C LWT67C LWT67C LWT67C
The PWM operation, using the EN pin as a digital
control, is depicted in Figures 32 and 33. The tests have been carried out at room temperature with Vbat = 3.60 V,
L = 22 mH, five LEDs in series, RFB = 22 W.
PWM
VFB
VPWM
Vout
Figure 32. Operation @ PWM = 10 kHz, DC = 10%
NCP5006
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PWM
VFB
PWR CLK
Vout
Figure 33. Operation @ PWM = 10 kHz, DC = 25%
PWM
PWR CLK
Vout
Figure 34. Magnified View of Operation @ PWM = 10 kHz, DC = 25%
NCP5006
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19
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.00
0 20 40 60 80 100 120
DC (%)
Figure 35. Output Current as a Function of the Operating Condition
Iout (mA)
Digital EN
Analog PWM
NCP5006 Iout = f(PWM) @ f = 10 kHz
Table 1. Recommended Passive Parts
Part Manufacturer Description Part Number
Ceramic Capacitor 1.0 mF/16 V MURATA GRM42 − X7R GRM42−6X7R−105K16
Ceramic Capacitor 1.0 mF/25 V MURATA GRM42 – X5R GRM
Ceramic Capacitor 4.7 mF/6.3 V MURATA GRM40 – X5R GRM40−X5R−475K6.3
Inductor 22 mH CoilCraft 1008PS − Shielded 1008PS−223MC
Inductor 22 mH CoilCraft Power Wafer LPQ4812−223KXC
Inductor 22 mH WURTH Power Choke 744031220
Inductor 22 mH TDK Power Inductor VLP4614T−220MR40
NCP5006
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Typical LEDs Load Mapping
Since the output power is voltage battery limited (see
Figure 5), one shall arrange the LED to cope with a specific
need. In particular , since the power cannot extend 600 mW
under realistic battery supply, powering ten LED can be
achieved by a series/parallel combination as depicted in
Figure 36.
Figure 36. Examples of Possible LED Arrangements
D1
LED
D2
LED
D3
LED
D4
LED
D5
LED
D6
LED
D7
LED
D8
LED
D9
LED
D10
LED
Load 75 mA
7.0 V (Typ.)
D1
LED
D2
LED
D3
LED
D4
LED
Load 50 mA
14 V ( Typ.)
D1
LED
D2
LED
Load 60 mA
10.5 V (Typ.)
D3
LED
D4
LED
D5
LED
D6
LED
D7
LED
D8
LED
D9
LED
D5
LED
D6
LED
D7
LED
D8
LED
D10
LED
D11
LED
D12
LED
D13
LED
D14
LED
D15
LED
GND
R1
3.9 W
Sense
Resistor
Test conditions: Vbat = 3.6 V
Lout = 22 mH
Cout = 1.0 mF
GND
R1
2.7 W
Sense
Resistor
GND
R1
3.3 W
Sense
Resistor
NCP5006
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Figure 37. NCP5006 Demo Board Schematic Diagram
GND
C2
4.7 mF/
16 V
C3
4.7 mF/
16 V
TP?
Vout
LWT67C
D9
LWT67C
D10
LWT67C
D11
LWT67C
D6
LWT67C
D7
LWT67C
D8
LWT67C
D5
LWT67C
D12
MMBF0201NLT1 R7
3.3 R
Q2 GND
Q1
R6
51 R
MMBF0201NLT1
RCCOM
CTC
TRA
TRB
CLR
U4A
M54HC123
Q
Q
13
4
15
14
1
2
3
VCC
GND
U5
16
4
5
NLAS4599
Vout
TP1
VFB
U1
Vout FB
GND
D2
MBR0530
L1
22 mH
4
GND
1
2
Vbat
5EN 3
NCP5006
C9
1.0 mF/
10 V
GND
R4
10 k
500 kA
P2
VCC
Adjust Flash Pulse Width
4.7 mF/6.0 V
C1
GND
8
U2C
HC132
10
9
GND
1N4148
D4
VCC
10 k
R1
10 k
R2
C7
1.0 nF
1N4148
D3
VCC
11
U2D
12
13
SNJ54HC132
C8
10 mF/
10 V
11
U2D
12
13
HC132
6
U2B
4
5
SNJ54HC132
HC132
R3
10 k
P1
100 kA
Adjust Flash Duty Cycle
3
U2A
1
2
SNJ54HC132
HC132
R5
100 k
S1 GND
TRIG
1
2
3
VCC
GND
GND
GND
1
2
J1
ENABLE
J2
Vbat
D1
MBR0530
VCC
C4
4.7 mF/
16 V
C5
100 nF
C6
100 nF GND
D13
REPEAT
R8
1.5 k
GND
VCC
S2
SINGLE/REPEAT
NCP5006
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Figure 38. NCP5006 Demo Board PCB: Top Layer
Figure 39. NCP5006 Demo Board PCB: Bottom Layer
Figure 40. NCP5006 Demo Board Top Silkscreen
NCP5006
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FIGURES INDEX
Figure 1: Typical Application 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2: Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3: Basic DC/DC Converter Structure 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4: Basic DC/DC Operation 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5: Maximum Output Power as a Function of the Battery Supply Voltage 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6: Typical Inductor Peak Current as a Function of Vbat Voltage 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7: Maximum Output Current as a Function of Vbat 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8: Output Current Feedback 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9: Basic Schematic Diagram 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10: Overall Efficiency vs. Power Supply @ Iout = 4.0 mA, L = 22 mH9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11: Overall Efficiency vs. Power Supply @ Iout = 10 mA, L = 22 mH9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12: Overall Efficiency vs. Power Supply @ Iout = 15 mA, L = 22 mH9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13: Overall Efficiency vs. Power Supply @ Iout = 20 mA, L = 22 mH9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14: Overall Efficiency vs. Power Supply @ Iout = 40 mA, L = 22 mH10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15: Feedback Voltage Stability 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16: Feedback Voltage Variation 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17: Standby Current 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18: Typical Operating Frequency 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19: Overvoltage Protection 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20: Typical Power Up Response 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21: Typical Start−Up Inductor Current and Output Voltage 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22: Typical Inductor Current 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23: Typical Output Voltage Ripple 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24: Typical Output Peak Voltage 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25: Efficiency as a Function of Vbat and Inductor ESR 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26: Noise Returned to the Battery 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27: Relative EMI Over 100 kHz−30 MHz Bandwidth 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28: Basic DC Current Mode Operation with Analog Feedback 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29: Basic DC Current Mode Operation with PWM Control 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30: Operation with Analog PWM, f = 10 kHz, DC = 25% 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31: Typical Semi−Pulsed Mode of Operation 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 32: Operation @ PWM = 10 kHz, DC = 10% 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 33: Operation @ PWM = 10 kHz, DC = 25% 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34: Magnified View of Operation @ PWM = 10 kHz, DC = 25% 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35: Output Current as a Function of the Operating Conditions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36: Examples of Possible LED Arrangements 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37: NCP5006 Demo Board Schematic Diagram 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38: NCP5006 Demo Board PCB: Top Layer 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 39: NCP5006 Demo Board PCB: Bottom Layer 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 40: NCP5006 Demo Board Top Silkscreen 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE CAPTIONS INDEX
Note 1: This device series contains ESD protection and exceeds the following tests 4. . . . . . . . . . . . . . . . . . . . . . . . .
Note 2: The maximum package power dissipation limit must not be exceeded 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 3: Latch−up current maximum rating: "100 mA per JEDEC standard: JESD78 4. . . . . . . . . . . . . . . . . . . . . . . .
Note 4: Moisture Sensivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A 4. . . . . . . . . . . . . . . . . . . . . . . .
Note 5: The overall tolerance depends upon the accuracy of the external resistor 5. . . . . . . . . . . . . . . . . . . . . . . . . . .
ABBREVIATIONS
EN Enable
FB Feed Back
POR Power On Reset: Internal pulse to reset the chip when the power supply is applied
NCP5006
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24
PACKAGE DIMENSIONS
TSOP−5
SN SUFFIX
CASE 483−02
ISSUE C NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.1142 0.1220
B1.30 1.70 0.0512 0.0669
C0.90 1.10 0.0354 0.0433
D0.25 0.50 0.0098 0.0197
G0.85 1.05 0.0335 0.0413
H0.013 0.100 0.0005 0.0040
J0.10 0.26 0.0040 0.0102
K0.20 0.60 0.0079 0.0236
L1.25 1.55 0.0493 0.0610
M0 10 0 10
S2.50 3.00 0.0985 0.1181
0.05 (0.002)
123
54
S
AG
L
B
D
H
C
KM
J
___ _
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Phone: 81−3−5773−3850
NCP5006/D
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