FEATURES
DHigh Speed:
− 70 MHz Bandwidth (G = 1, −3 dB)
− 240 V/µs Slew Rate
− 60-ns Settling Time (0.1%)
DHigh Output Drive, IO = 100 mA (typ)
DExcellent Video Performance:
− 0.1 dB Bandwidth of 30 MHz (G = 1)
− 0.01% Differential Gain
− 0.01° Differential Phase
DVery Low Distortion:
− THD = −82 dBc (f = 1 MHz, RL = 150 Ω)
− THD = −89 dBc (f = 1 MHz, RL = 1 kΩ)
DWide Range of Power Supplies:
− VCC = ±5 V to ±15 V
DAvailable in Standard SOIC, MSOP
PowerPAD, JG, or FK Packages
DEvaluation Module Available
DESCRIPTION
The THS4051 and THS4052 are general-purpose,
single/dual, high-speed voltage feedback amplifiers ideal
for a wide range of applications including video,
communication, and imaging. The devices offer very good
ac performance with 70-MHz bandwidth, 240-V/µs slew
rate, and 60-ns settling time (0.1%). The THS4051/2 are
stable at all gains for both inverting and non-
inverting configurations. These amplifiers have a high
output drive capability of 100 mA and draw only 8.5-mA
supply current per channel. Excellent professional video
results can be obtained with the low dif ferential gain/phase
errors of 0.01%/ 0.01° and wide 0.1-dB flatness to 30 MHz.
For applications requiring low distortion, the THS4051/2 is
ideally suited with total harmonic distortion of −82 dBc at
1 MHz.
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/2
THS4031/2
THS4081/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High-Speed Amplifiers
175-MHz Low Power High-Speed Amplifiers
THS4052
D AND DGN† PACKAGES
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
−VCC
VCC+
2OUT
2IN−
2IN+
1
2
3
4
8
7
6
5
NULL
IN−
IN+
VCC−
NULL
VCC+
OUT
NC
THS4051
D, DGN, AND JG PACKAGES
(TOP VIEW)
NC − No internal connection
Cross Section View Showing
PowerPAD Option (DGN)
†This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
VCC+
NC
OUT
NC
NC
IN−
NC
IN+
NC
NC
NULL
NC
NULL
NC
V
NC
NC
NC
NC
THS4051
FK PACKAGE
(TOP VIEW)
CC−
SLOS238D − MAY 1999 − REVISED AUGUST 2008
!" # $%&" !# '%()$!" *!"&+ *%$"#
$ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+
*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+
www.ti.com
Copyright 1999−2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments. SMBus is a trademark of Intel Corp.
All other trademarks are the property of their respective owners.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
2
CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS
OTHERWISE NOTED)(1)
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VIO ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M-suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package 300°C. . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
θ
JA
θ
JC
TA = 25
°
C
PACKAGE
θJA
(°C/W)
θJC
(°C/W)
TA = 25 C
POWER RATING
D 167‡38.3 740 mW
DGN§58.4 4.7 2.14 W
JG 119 28 1050 mW
FK 87.7 20 1375 mW
‡This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K
test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
§This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC.
For further information, refer to Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VCC+ and VCC−
Dual supply ±4.5 ±16
V
Supply voltage, V
CC+
and V
CC− Single supply 9 32
V
C-suffix 0 70
Operating free-air temperature, T
A
I-suffix −40 85 °C
Operating free-air temperature, TA
M-suffix −55 125
C
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
3
AVAILABLE OPTIONS(1)
PACKAGED DEVICES
TANUMBER
OF
CHANNELS
PLASTIC
SMALL
OUTLINE†
PLASTIC MSOP†
(DGN) CERAMIC DIP
(JG)
CHIP
CARRIER
EVALUATION
MODULE
CHANNELS
OUTLINE†
(D) DEVICE SYMBOL (JG)
CARRIER
(FK)
MODULE
0°C to 70°C
1 THS4051CD THS4051CDGN ACQ — — THS4051EVM
0
°
C to 70
°
C
2 THS4052CD THS4052CDGN‡ACE — — THS4052EVM
−40°C to 85°C
1 THS4051ID THS4051IDGN ACR — — —
−40
°
C to 85
°
C
2 THS4052ID THS4052IDGN‡ACF — — —
−55°C to 125°C 1 — — — THS4051MJG THS4051MFK —
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
†The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4051CDGN).
‡This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
FUNCTIONAL BLOCK DIAGRAM
OUT
86
1
IN−
IN+
2
3
Null
Figure 1. THS4051 − Single Channel
1OUT
1IN−
1IN+
VCC
2OUT
2IN−
2IN+
−VCC
Figure 2. THS4052 − Dual Channel
−100
−90
−80
−70
−60
−50
−40
T OT AL HARMONIC DISTORTION
vs
FREQUENCY
f - Frequency - Hz 20M10M100k 1M
THD - Total Harmonic Distortion - dBc
VCC = ± 15 V
Gain = 2
VO(PP) = 2 V
RL = 150 Ω
RL = 1 kΩ
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
4
ELECTRICAL CHARACTERISTICS AT TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise
noted)
dynamic performance
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V
Gain = 1
70
MHz
Dynamic performance small-signal bandwidth
VCC = ±5 V
Gain = 1
70
MHz
Dynamic performance small-signal bandwidth
(−3 dB) VCC = ±15 V
Gain = 2
38
MHz
BW
(−3 dB)
VCC = ±5 V
Gain = 2
38
MHz
BW
Bandwidth for 0.1 dB flatness
VCC = ±15 V
Gain = 1
30
MHz
Bandwidth for 0.1 dB flatness
VCC = ±5 V
Gain = 1
30
MHz
Full power bandwidth§
VO(pp) = 20 V, VCC = ±15 V 3.8
MHz
Full power bandwidth
§
VO(pp) = 5 V, VCC = ±5 V 12.7
MHz
SR
Slew rate‡
VCC = ±15 V, 20-V step, Gain = 5 240
V/ s
SR
Slew rate‡
VCC = ±5 V, 5-V step Gain = −1 200
V/
µ
s
Settling time to 0.1%
VCC = ±15 V, 5-V step
Gain = −1
60
ns
ts
Settling time to 0.1%
VCC = ±5 V, 2-V step
Gain = −1
60
ns
t
s
Settling time to 0.01%
VCC = ±15 V, 5-V step
Gain = −1
130
ns
Settling time to 0.01%
VCC = ±5 V, 2-V step
Gain = −1
140
ns
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
‡Slew rate is measured from an output level range of 25% to 75%.
§Full power bandwidth = slew rate/2 πVO(Peak).
noise/distortion performance
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V
RL = 150 Ω−82
THD
Total harmonic distortion
VO(pp) = 2 V,
V
CC
=
±
15 V
RL = 1 kΩ−89
dBc
THD
Total harmonic distortion
VO(pp) = 2 V,
f = 1 MHz, Gain = 2
VCC = ±5 V
RL = 150 Ω−78
dBc
f = 1 MHz, Gain = 2
V
CC
=
±
5 V
RL = 1 kΩ−87
VnInput voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 14 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V, f = 10 kHz 0.9 pA/√Hz
Differential gain error
Gain = 2,
NTSC,
VCC = ±15 V 0.01%
Differential gain error
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp VCC = ±5 V 0.01%
Differential phase error
Gain = 2,
NTSC,
VCC = ±15 V 0.01°
Differential phase error
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp VCC = ±5 V 0.03°
Channel-to-channel crosstalk
(THS4052 only) VCC = ±5 V or ±15 V, f = 1 MHz −57 dB
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
5
electrical characteristics at TA = 25°C, VCC = ±15 V, R L = 150 Ω (unless otherwise noted) (continued)
dc performance
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V, RL = 1 kΩ
VO = ±10 V
TA = 25°C 5 9
V/mV
Open loop gain
V
CC
=
±
15 V, R
L
= 1 k
Ω
V
O
=
±
10 V
TA = full range 3
V/mV
Open loop gain
VCC = ±5 V, RL = 250 Ω
VO = ±2.5 V
TA = 25°C 2.5 6
V/mV
V
CC
=
±
5 V, R
L
= 250
Ω
V
O
=
±
2.5 V
TA = full range 2
V/mV
VOS
Input of fset voltage
VCC = ±5 V or ±15 V
TA = 25°C 2.5 10
mV
V
OS
Input of fset voltage
V
CC
=
±
5 V or
±
15 V
TA = full range 12
mV
Offset voltage drift VCC = ±5 V or ±15 V TA = full range 15 µV/°C
IIB
Input bias current
VCC = ±5 V or ±15 V
TA = 25°C 2.5 6
A
I
IB
Input bias current
V
CC
=
±
5 V or
±
15 V
TA = full range 8µ
A
IOS
Input of fset current
VCC = ±5 V or ±15 V
TA = 25°C 35 250
nA
I
OS
Input of fset current
V
CC
=
±
5 V or
±
15 V
TA = full range 400
nA
Offset current drift TA = full range 0.3 nA/°C
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
input characteristics
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VICR
Common-mode input voltage range
VCC = ±15 V ±13.8 ±14.3
V
V
ICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.3
V
CMRR
Common mode rejection ratio
VCC = ±15 V, VICR = ±12 V
TA = full range
70 100
dB
CMRR
Common mode rejection ratio
VCC = ±5 V, VICR = ±2.5 V
T
A
= full range
70 100
dB
riInput resistance 1 MΩ
CiInput capacitance 1.5 pF
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
output characteristics
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V RL = 250 Ω ±11.5 ±13
V
VO
Output voltage swing
VCC = ±5 V RL = 150 Ω ±3.2 ±3.5
V
V
O
Output voltage swing
VCC = ±15 V
RL = 1 kΩ
±13 ±13.6
V
VCC = ±5 V
R
L
= 1 k
Ω±3.5 ±3.8
V
IO
Output current‡
VCC = ±15 V
RL = 20 Ω
80 100
mA
I
O
Output current‡
VCC = ±5 V
R
L
= 20
Ω50 75
mA
ISC Short-circuit current‡VCC = ±15 V 150 mA
ROOutput resistance Open loop 13 W
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
‡Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted.
See the absolute maximum ratings section of this data sheet for more information.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
6
electrical characteristics at TA = 25°C, VCC = ±15 V, R L = 150 Ω (unless otherwise noted) (continued)
power supply
PARAMETER
TEST CONDITIONS†
THS405xC, THS405xI
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC
Supply voltage operating range
Dual supply ±4.5 ±16.5
V
V
CC
Supply voltage operating range
Single supply 9 33
V
VCC = ±15 V
TA = 25°C 8.5 10.5
ICC
Supply current (per amplifier)
V
CC
=
±
15 V
TA = full range 11.5
mA
I
CC
Supply current (per amplifier)
VCC = ±5 V
TA = 25°C 7.5 9.5
mA
V
CC
=
±
5 V
TA = full range 10.5
PSRR
Power supply rejection ratio
VCC = ±5 V or ±15 V
TA = 25°C 70 84
dB
PSRR
Power supply rejection ratio
V
CC
=
±
5 V or
±
15 V
TA = full range 68
dB
†Full range = 0°C to 70°C for C suffix and −40°C to 85°C for I suffix
ELECTRICAL CHARACTERISTICS AT TA = FULL RANGE, VCC = ±15 V, RL = 1 KΩ (UNLESS
OTHERWISE NOTED)
dynamic performance
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
Unity gain bandwidth VCC = ±15 V, Closed loop RL = 1 kΩ50§70 MHz
VCC = ±15 V
Gain = 1
70
Dynamic performance small-signal bandwidth (−3
VCC = ±5 V
Gain = 1
70
MHz
Dynamic performance small-signal bandwidth (−3
dB) VCC = ±15 V
Gain = 2
38
MHz
BW
dB)
VCC = ±5 V
Gain = 2
38
BW
Bandwidth for 0.1 dB flatness
VCC = ±15 V
Gain = 1
30
MHz
Bandwidth for 0.1 dB flatness
VCC = ±5 V
Gain = 1
30
MHz
Full power bandwidth‡
VO(pp) = 20 V, VCC = ±15 V 3.8
MHz
Full power bandwidth
‡
VO(pp) = 5 V, VCC = ±5 V 12.7
MHz
SR
Slew rate
VCC = ±15 V, RL = 1 kΩ240§300
V/ s
SR
Slew rate
VCC = ±5 V, 5-V step Gain = −1 200
V/
µ
s
Settling time to 0.1%
VCC = ±15 V, 5-V step
Gain = −1
60
ns
ts
Settling time to 0.1%
VCC = ±5 V, 2-V step
Gain = −1
60
ns
t
s
Settling time to 0.01%
VCC = ±15 V, 5-V step
Gain = −1
130
ns
Settling time to 0.01%
VCC = ±5 V, 2-V step
Gain = −1
140
ns
†Full range = −55°C to 125°C for the THS4051M.
‡Full power bandwidth = slew rate/2 πVO(Peak).
§This parameter is not tested.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
7
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
noise/distortion performance
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
V = 2 V,
VCC = ±15 V
RL = 150 Ω−82
THD
Total harmonic distortion
VO(pp) = 2 V,
f = 1 MHz, Gain = 2,
V
CC
=
±
15 V
RL = 1 kΩ−89
dBc
THD
Total harmonic distortion
O(pp)
f = 1 MHz, Gain = 2,
TA = 25
°
C
VCC = ±5 V
RL = 150 Ω−78
dBc
TA = 25°C
V
CC
=
±
5 V
RL = 1 kΩ−87
VnInput voltage noise VCC = ±5 V or ±15 V,
TA = 25°Cf = 10 kHz, RL = 150 Ω14 nV/√Hz
InInput current noise VCC = ±5 V or ±15 V,
TA = 25°Cf = 10 kHz, RL = 150 Ω0.9 pA/√Hz
Differential gain error
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp,
VCC = ±15 V 0.01%
Differential gain error
40 IRE modulation,
T
A
= 25°C, ±
100 IRE ramp,
R
L
= 150 ΩVCC = ±5 V 0.01%
Differential phase error
Gain = 2,
40 IRE modulation,
NTSC,
±100 IRE ramp,
VCC = ±15 V 0.01°
Differential phase error
40 IRE modulation,
T
A
= 25°C, ±
100 IRE ramp,
R
L
= 150 ΩVCC = ±5 V 0.03°
†Full range = −55°C to 125°C for the THS4051M.
dc performance
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V, VO = ±10 V
TA = 25°C 5 9
V/mV
Open loop gain
V
CC
=
±
15 V, V
O
=
±
10 V
TA = full range 3
V/mV
Open loop gain
VCC = ±5 V, VO = ±2.5 V
TA = 25°C 2.5 6
V/mV
V
CC
=
±
5 V, V
O
=
±
2.5 V
TA = full range 2
V/mV
VIO
Input of fset voltage
VCC = ±5 V or ±15 V
TA = 25°C 2.5 10
mV
V
IO
Input of fset voltage
V
CC
=
±
5 V or
±
15 V
TA = full range 13
mV
Offset voltage drift VCC = ±5 V or ±15 V TA = full range 15 µV/°C
IIB
Input bias current
VCC = ±5 V or ±15 V
TA = 25°C 2.5 6
A
I
IB
Input bias current
V
CC
=
±
5 V or
±
15 V
TA = full range 8µ
A
IIO
Input of fset current
VCC = ±5 V or ±15 V
TA = 25°C 35 250
nA
I
IO
Input of fset current
V
CC
=
±
5 V or
±
15 V
TA = full range 400
nA
Offset current drift TA = full range 0.3 nA/°C
†Full range = −55°C to 125°C for the THS4051M.
input characteristics
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VICR
Common-mode input voltage range
VCC = ±15 V ±13.8 ±14.3
V
V
ICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.3
V
CMRR
Common mode rejection ratio
VCC = ±15 V, VICR = ±12 V
TA = full range
70 100
dB
CMRR
Common mode rejection ratio
VCC = ±5 V, VICR = ±2.5 V
T
A
= full range
70 100
dB
riInput resistance 1 MΩ
CiInput capacitance 1.5 pF
†Full range = −55°C to 125°C for the THS4051M.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
8
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
output characteristics
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC = ±15 V RL = 250 Ω ±12 ±13
V
VO
Output voltage swing
VCC = ±5 V RL = 150 Ω ±3.2 ±3.5
V
V
O
Output voltage swing
VCC = ±15 V
RL = 1 kΩ
±13 ±13.6
V
VCC = ±5 V
R
L
= 1 k
Ω±3.5 ±3.8
V
VCC = ±15 V,
TA = 25°C80 100
IOOutput current‡VCC = ±15 V,
TA = full range RL = 20 Ω70 mA
VCC = ±5 V 50 75
ISC Short-circuit current‡VCC = ±15 V 150 mA
ROOutput resistance Open loop 13 W
†Full range = −55°C to 125°C for the THS4051M.
‡Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted.
See the absolute maximum ratings section of this data sheet for more information.
power supply
PARAMETER
TEST CONDITIONS†
THS4051M
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VCC
Supply voltage operating range
Dual supply ±4.5 ±16.5
V
V
CC
Supply voltage operating range
Single supply 9 33
V
VCC = ±15 V
TA = 25°C 8.5 10.5
ICC
Supply current (per amplifier)
V
CC
=
±
15 V
TA = full range 11.5
mA
I
CC
Supply current (per amplifier)
VCC = ±5 V
TA = 25°C 7.5 9.5
mA
V
CC
=
±
5 V
TA = full range 10.5
PSRR Power supply rejection ratio VCC = ±5 V or ±15 V TA = full range 70 84 dB
†Full range = −55°C to 125°C for the THS4051M.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
9
TYPICAL CHARACTERISTICS
Figure 3
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0.0
−40 −20 0 20 40 60 80 100
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
VIO − Input Offset Voltage − mV
VCC = ± 5 V
VCC = ± 15 V
Figure 4
2.2
2.3
2.4
2.5
2.6
2.7
2.8
−40 −20 0 20 40 60 80 100
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
Input Bias Current −
I
IB µA
VCC = ± 5 V & ± 15 V
Figure 5
2
4
6
8
10
12
14
5 7 9 11 13 15
OUTPUT V O LTAGE
vs
SUPPLY VOLTAGE
±VCC - Supply Voltage - V
O - Output Voltage -V V
TA=25°C
RL = 1 kΩ
RL = 150 Ω
Figure 6
3
5
7
9
11
13
15
5 7 9 11 13 15
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
±VCC - Supply Voltage - V
- Common-Mode Input Voltage −
VICR ±V
TA=25°C
Figure 7
O - Output Voltage -V V
OUTPUT V O LTAGE
vs
FREE-AIR TEMPERATURE
12.5
12
4.5
4
3.5
2.5
−40 −20 0 20 40 60 80 100
TA − Free-Air Temperature − _C
3
13.5
13
14
VCC = ± 15 V
RL = 1 kΩ
VCC = ± 5 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
VCC = ± 5 V
RL = 150 Ω
Figure 8
5
6
7
8
9
10
11
5 7 9 11 13 15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
± VCC - Supply Voltage - V
ICC − Supply Current − mA
TA=85°C
TA=25°C
TA=−40°C
Figure 9
VOLTAGE & CURRENT NOISE
vs
FREQUENCY
f - Frequency - Hz
100 1k 10k10 100k
1000
100
10
1
0.10
nV/ Hz
− Voltage Noise −Vn
In− Current Noise − pA/ Hz
VCC = ± 15 V and ± 5V
TA = 25°C
VN
IN
Figure 10
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
POWER-SUPPLY REJECTION
RATIO
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
PSRR - Power Supply Rejection Ratio - dB
VCC = ±15 V & ±5 V
+VCC
−VCC
Figure 11
CMRR
vs
FREQUENCY
−30
−40
−50
−60
−70
−80
10k 100k 1M
−90
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz10M 100M
−20
−100
VCC = ±15 V or ±5 V
RF = 1 kΩ
VI(PP) = 2 V
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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10
TYPICAL CHARACTERISTICS
Figure 12
−20
−30
−40
−50
−60
−70
100k 1M
−80
f − Frequency − Hz
10M 100M
VCC = ± 15 V
Gain = 2
RF = 3.6 kΩ
RL = 150 Ω
CROSSTALK
vs
FREQUENCY
Crosstalk − dB
Figure 13
−20
0
20
40
60
80
100
OPEN LOOP GAIN AND
PHASE RESPONSE
vs
FREQUENCY
f - Frequency - Hz 100M100k1k 10k
−60
−90
0
30
−150
−120
−30
Open Loop Gain − dB
Phase
1M 10M
VCC = ± 5 V & ±15 V
Gain
Phase
Gain
Figure 14
−100
−90
−80
−70
−60
−50
−40
T OT AL HARMONIC DISTORTION
vs
FREQUENCY
f - Frequency - Hz 20M10M100k 1M
THD - Total Harmonic Distortion - dBc
VCC = ± 15 V
Gain = 2
VO(PP) = 2 V
RL = 150 Ω
RL = 1 kΩ
Figure 15
0
DISTORTION
vs
OUTPUT V O LTAGE
−55
−60
−66
−70
−75
−80
VO − Output Voltage − V
−85
Distortion − dBc
−90 5101520
−50
3rd Harmonic
VCC = ± 15 V
RL = 1 kΩ
G = 5
f = 1 MHz
2nd Harmonic
Figure 16
0
DISTORTION
vs
OUTPUT V O LTAGE
−55
−60
−66
−70
−75
−80
−85
Distortion − dBc
−90 5101520
−50 VCC = ± 15 V
RL = 150 Ω
G = 5
f = 1 MHz
2nd
Harmonic
VO − Output Voltage − V
3rd Harmonic
Figure 17
DISTORTION
vs
FREQUENCY
−40
−50
−60
−70
−80
f − Frequency − Hz
−90
Distortion − dBc
−100100k 1M 10M 100M
VCC = ± 15 V
RL = 1 kΩ
G = 2
VO(PP) = 2 V
2nd Harmonic
3rd Harmonic
Figure 18
DISTORTION
vs
FREQUENCY
−40
−50
−60
−70
−80
f − Frequency − Hz
−90
Distortion − dBc
−100100k 1M 10M 100M
VCC = ± 5 V
RL = 1 kΩ
G = 2
VO(PP) = 2 V
2nd Harmonic
3rd Harmonic
Figure 19
DISTORTION
vs
FREQUENCY
−40
−50
−60
−70
−80
f − Frequency − Hz
−90
Distortion − dBc
−100100k 1M 10M 100M
VCC = ± 15 V
RL = 150 Ω
G = 2
VO(PP) = 2 V
2nd Harmonic
3rd Harmonic
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11
TYPICAL CHARACTERISTICS
Figure 20
DISTORTION
vs
FREQUENCY
−40
−50
−60
−70
−80
f − Frequency − Hz
−90
Distortion − dBc
−100100k 1M 10M 100M
VCC = ± 5 V
RL = 150 Ω
G = 2
VO(PP) = 2 V
2nd Harmonic
3rd Harmonic
Figure 21
−6
−5
−4
−3
−2
−1
0
1
2
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
RF = 750 Ω
RF = 620 Ω
RF = 0 Ω
VCC = ± 15 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV
Figure 22
−6
−5
−4
−3
−2
−1
0
1
2
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ± 5 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV
RF = 750 Ω
RF = 0 Ω
RF = 620 Ω
Figure 23
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ± 15 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV RF = 750 Ω
RF = 620 Ω
RF = 0 Ω
Figure 24
−0.4
−0.3
−0.2
−0.1
−0.0
0.1
0.2
0.3
0.4
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ± 5 V
Gain = −1
RL = 150 Ω
VO(PP) = 62 mV RF = 750 Ω
RF = 620 Ω
RF = 0 Ω
Figure 25
0
1
2
3
4
5
6
7
8
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ±15 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
RF = 3.6 kΩ
RF = 2.7 kΩ
RF = 1 kΩ
Figure 26
0
1
2
3
4
5
6
7
8
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
RF = 3.6 kΩ
RF = 2.7 kΩ
RF = 1 kΩ
VCC = ±5 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
Figure 27
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
RF = 3.6 kΩ
RF = 2.7 kΩ
RF = 1 kΩ
VCC = ±15 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
Figure 28
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ±5 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
RF = 3.6 kΩ
RF = 1 kΩ
RF = 2.7 kΩ
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12
TYPICAL CHARACTERISTICS
Figure 29
0
1
2
3
4
5
6
7
8
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
CL= 10 pF
RL = 1 kΩ
RL = 150 Ω
VCC = ±15 V
Gain = 2
RL = 2.7 k Ω
VO(PP) = 125 mV
Figure 30
−6
−5
−4
−3
−2
−1
0
1
2
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ± 15 V
Gain = −1
RL = 150 Ω
VO(PP) = 62 mV
RF = 1 kΩ
RF = 3.9 kΩ
RF = 5.6 kΩ
Figure 31
−6
−5
−4
−3
−2
−1
0
1
2
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
Output Amplitude − dB
VCC = ± 5 V
Gain = −1
RL = 150 Ω
VO(PP) = 62 mV
RF = 1 kΩ
RF = 5.6 kΩ
RF = 3.9 kΩ
Figure 32
−30
−25
−20
−15
−10
−5
0
5
10
OUTPUT AMPLITUDE
vs
FREQUENCY
f - Frequency - Hz 100M10M100k 1M
VO(PP) - Output Voltage - dBV
VCC = ± 15 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
VO(PP)=125 mV
VO(PP)=2.25 V
VO(PP)=0.4 V
Figure 33
20
40
60
80
100
120
140
160
180
12345
SETTING TIME
vs
OUTPUT STEP
VO - Output Step Voltage - V
Settling Time − ns
RF = 360 Ω
VCC = ± 5 V
0.1%
VCC = ± 15 V
0.1%
VCC = ± 5 V
0.01%
VCC = ± 15 V
0.01%
Figure 34
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.06
0.04
1234
Number of 150-Ω Loads
0.02
Differential Gain − %
0
0.08
0.10
0.12 Gain = 2
40 IRE-NTSC Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
Figure 35
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.12
0.08
1234
Number of 150-Ω Loads
0.04
Differential Gain − %
0
0.16
0.2 Gain = 2
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
Figure 36
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.4°
0.3°
0.2°
1234
Number of 150-Ω Loads
0.1°
Differential Phase
0°
0.5°Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
Figure 37
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.4°
0.3°
0.2°
1234
Number of 150-Ω Loads
0.1°
Differential Phase
0°
0.6°
0.5°
Gain = 2
40 IRE-PAL Modulation
Worst Case ±100 IRE Ramp
VCC = ± 15 V
VCC = ± 5 V
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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13
TYPICAL CHARACTERISTICS
Figure 38
−0.6
−0.4
−0.2
−0.0
0.2
0.4
0.6
0 50 100 150 200 250 300 350 400
1-V STEP RESPONSE
t - Time - ns
− Output Voltage − V
VO
VCC = ± 5 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
Figure 39
−3
−2
−1
0
1
2
3
0 50 100 150 200 250 300 350 400
5-V STEP RESPONSE
t - Time - ns
− Output Voltage − V
VO
VCC = ± 5 V
Gain = −1
RF = 3.9 kΩ
RL = 150 Ω
Figure 40
−0.6
−0.4
−0.2
−0.0
0.2
0.4
0.6
0 50 100 150 200 250 300 350 400
1-V STEP RESPONSE
t - Time - ns
− Output Voltage − V
VO
VCC = ± 15 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
−15
−10
−5
0
5
10
15
0 100 200 300 400 500
20-V STEP RESPONSE
t - Time - ns
− Output Voltage − V
VO
VCC = ± 15 V
Gain = 5
RF = 2.7 kΩ
RL = 150 & 1 kΩ
Figure 41
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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14
APPLICATION INFORMATION
THEORY OF OPERATION
The THS405x is a high-speed operational amplifier
configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary
bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high
performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified
schematic is shown in Figure 42.
IN− (2)
IN+ (3)
NULL (1) NULL (8)
(6) OUT
(4) VCC−
(7) VCC+
Figure 42. THS405x Simplified Schematic
NOISE CALCULATIONS AND NOISE FIGURE
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise
ratio (SNR) is very important. The noise model for the THS405x is shown in Figure 43. This model includes all of the noise
sources as follows:
•en = Amplifier internal voltage noise (nV/√Hz)
•IN+ = Noninverting current noise (pA/√Hz)
•IN− = Inverting current noise (pA/√Hz)
•eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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15
APPLICATION INFORMATION
NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED)
RS
e
Rs
e
n
IN+
IN−
eni
Figure 43. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
eni +ǒenǓ2)ǒIN ) RSǓ2)ǒIN– ǒRFøRGǓǓ2)4kTR
s)4kT
ǒRFøRGǓ
Ǹ
Where: k = Boltzmann’s constant = 1.380658 × 10−23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier
gain (AV).
eno +eni AV+eniǒ1)RF
RGǓ(noninverting case)
As the previous equations show , to keep noise at a minimum, small value resistors should be used. As the closed-loop gain
is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads
to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise
voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest
noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to
calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits
Applications Report (literature number SLVA043).
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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16
APPLICATION INFORMATION
NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a
measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically
50 Ω in RF applications.
NF +10logȧ
ȧ
ȱ
Ȳ
e2
ni
ǒeRsǓ2ȧ
ȧ
ȳ
ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we
can approximate noise figure as:
NF +10logȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)
ȧ
ȡ
ȢǒenǓ2
)ǒIN ) RSǓ2ȧ
ȣ
Ȥ
4kTR
S
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
Figure 44 shows the noise figure graph for the THS405x.
0
5
10
15
20
25
30
35
40
NOISE FIGURE
vs
SOURCE RESISTANCE
Source Resistance - Ω
Noise Figure (dB)
100 1k 10k10 100k
f = 10 kHz
TA = 25°C
Figure 44. Noise Figure vs Source Resistance
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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17
APPLICATION INFORMATION
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The
first is t o realize that the THS405x has been internally compensated to maximize its bandwidth and slew rate performance.
When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device’s phase
margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is
recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 45. A minimum value
of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value
to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end.
+
_
THS405x
CLOAD
1 kΩ
Input
Output
1 kΩ
20 Ω
Figure 45. Driving a Capacitive Load
OFFSET NULLING
The THS405x has very low input offset voltage for a high-speed amplifier. However , if additional correction is required, an
offset nulling function has been provided on the THS4051. The input offset can be adjusted by placing a potentiometer
between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 46.
_
+
THS4051
VCC−
VCC+
0.1 µF
0.1 µF
10 kΩ
Figure 46. Offset Nulling Schematic
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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18
APPLICATION INFORMATION
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
VOO +VIOǒ1)RF
RGǓ"IIB)RSǒ1)RF
RGǓ"IIB*RF
+
−
VIO +
RG
RS
RF
+IIB− VO
+IIB+ −
Figure 47. Output Offset Voltage Model
OPTIMIZING UNITY GAIN RESPONSE
Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still maintain
stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there
is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending
upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum
settling time and minimum ringing, a feedback resistor of 620 Ω should be used as shown in Figure 48. Additional
capacitance can also be used in parallel with the feedback resistance if even finer optimization is required.
_
+
THS405x
620 Ω
Input
Output
Figure 48. Noninverting, Unity Gain Schematic
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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19
APPLICATION INFORMATION
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The
simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 49).
VIC1
+
−
R
G
R
F
R1
f–3dB
+
Figure 49. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best
results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can
result in phase shift of the amplifier.
VI
C2
R2R1
C
RG
Figure 50. 2-Pole Low-Pass Sallen-Key Filter
SLOS238D − MAY 1999 − REVISED AUGUST 2008
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APPLICATION INFORMATION
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high frequency
design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation board is available to use
as a guide for layout or for evaluating the device performance.
DGround planes − It is highly recommended that a ground plane be used on the board to provide all components
with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
DProper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In
addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive
for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
DSockets − Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance
in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the
printed-circuit board is the best implementation.
DShort trace runs/compact part placements − Optimum high frequency performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input
of the amplifier.
DSurface-mount passive components − Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size
of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance
and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as
possible.
GENERAL POWERPAD DESIGN CONSIDERATIONS
The THS405x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family
of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 51(a) and
Figure 51(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package
[see Figure 51(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can
be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During t h e
surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area
underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the
package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface
mount with the, heretofore, awkward mechanical methods of heatsinking.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
21
APPLICATION INFORMATION
GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED)
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 51. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 52. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etch for the leads as well
as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so
that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS405xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area
to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes
under the THS405xDGN package should make their connection to the internal ground plane with a complete
connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes
exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder
from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS405xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
22
APPLICATION INFORMATION
GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED)
The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the application.
In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches (or 76.2 mm × 76.2 mm),
then the expected thermal coefficient, θJA, is about 58.4°C/W. For comparison, the non-PowerPAD version of the
THS405x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated
by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of THS405x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θJA = 98°C/W
TJ = 150°C
SOIC Package
Low-K Test PCB
θJA = 167°C/W
2
1.5
1
0
−40 −20 0 20 40
Maximum Power Dissipation − W
2.5
3
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
60 80 100
0.5
TA − Free-Air T emperature − °C
NOTE A: Results are with no air flow and PCB size = 3”×3”
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found in the
Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web
site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales
office. Refer to literature number SLMA002 when ordering.
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
23
APPLICATION INFORMATION
GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and
output power. The designer should never forget about the quiescent heat generated within the device, especially devices
with multiple amplifiers. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at
low output voltages with high output currents. Figure 54 to Figure 57 show this effect, along with the quiescent heat, with
an ambient air temperature of 50°C. Obviously, as the ambient temperature increases, the limit lines shown will drop
accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line
will exceed the amplifier’s limits and failure may result. When using VCC = ±5 V, there is generally not a heat problem, even
with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited in the amount of heat it can
dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD
devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it
is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier
package (THS4052), the sum of the RMS output currents and voltages should be used to choose the proper package. The
graphs shown assume that both amplifier outputs are identical.
Figure 54
Package With
θJA < = 120°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ± 5 V
Tj = 150°C
TA = 50°C
100
80
40
0012 3
− Maximum RMS Output Current − mA
140
180
200
45
160
120
60
20
| VO | − RMS Output Voltage − V
IO
||
Maximum Output
Current Limit Line
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMIT
S
Safe Operating
Area
Figure 55
100
10 0369
1000
12 15
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
SO-8 Package
θJA = 98°C/W
High-K Test PCB
TJ = 150°C
TA = 50°C
| VO | − RMS Output Voltage − V
− Maximum RMS Output Current − mA
IO
||
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating
Area
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
24
APPLICATION INFORMATION
GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED)
Figure 56
Package With
θJA ≤ 60°C/W
SO-8 Package
θJA = 98°C/W
High-K Test PCB
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
100
80
40
0012 3
− Maximum RMS Output Current − mA
140
180
200
45
160
120
60
20
| VO | − RMS Output Voltage − V
IO
||
Maximum Output
Current Limit Line
THS4052
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMIT
S
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating Area
Figure 57
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
| VO | − RMS Output Voltage − V
− Maximum RMS Output Current − mA
IO
||
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
THS4052
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
DGN Package
θJA = 58.4°C/W
Safe Operating Area
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SLOS238D − MAY 1999 − REVISED AUGUST 2008
www.ti.com
25
APPLICATION INFORMATION
EVALUATION BOARD
An evaluation board is available for the THS4051 (literature number SLOP220) and THS4052 (literature number
SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full performance of
the amplifier. A schematic of the evaluation board is shown in Figure 58. The circuitry has been designed so that the
amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the
THS4051 EVM User’s Guide or the THS4052 EVM User’s Guide. To order the evaluation board, contact your local TI sales
office or distributor.
_
+
THS4051
VCC−
VCC+
C1
6.8 µF
C4
0.1 µF
C2
6.8 µF
C5
0.1 µF
R4
2 kΩ
R2
2 kΩ
R3
49.9 Ω
R5
49.9 Ω
R1
49.9 Ω
IN−
IN+
NULL
OUT
NULL
+
+
Figure 58. THS4051 Evaluation Board Schematic
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4051CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4051IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Power
PAD no Sb/Br)
THS4052CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4052IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4051 :
•Military: THS4051M
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4051CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4051IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4051IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4052CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4052CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4052IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4052IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4051CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4051CDR SOIC D 8 2500 367.0 367.0 35.0
THS4051IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4051IDR SOIC D 8 2500 367.0 367.0 35.0
THS4052CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4052CDR SOIC D 8 2500 367.0 367.0 35.0
THS4052IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4052IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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