SLOS238D - MAY 1999 - REVISED AUGUST 2008 THS4051 D, DGN, AND JG PACKAGES (TOP VIEW) FEATURES D High Speed: - 70 MHz Bandwidth (G = 1, -3 dB) - 240 V/s Slew Rate - 60-ns Settling Time (0.1%) NULL IN- IN+ VCC- D High Output Drive, IO = 100 mA (typ) D Excellent Video Performance: 1OUT 1IN- 1IN+ -VCC 1 8 2 7 3 6 4 5 VCC+ 2OUT 2IN- 2IN+ Cross Section View Showing PowerPAD Option (DGN) This device is in the Product Preview stage of development. Please contact your local TI sales office for availability. 290-MHz Low Distortion High-Speed Amplifiers 100-MHz Low Noise High-Speed Amplifiers 175-MHz Low Power High-Speed Amplifiers NULL 1 20 19 NC NC 2 4 18 NC IN- 5 17 VCC+ NC 6 16 NC IN+ 7 15 OUT NC 8 14 NC 9 10 11 12 13 NC DESCRIPTION 3 NC NC RELATED DEVICES THS4051 FK PACKAGE (TOP VIEW) NULL The THS4051 and THS4052 are general-purpose, single/dual, high-speed voltage feedback amplifiers ideal for a wide range of applications including video, communication, and imaging. The devices offer very good ac performance with 70-MHz bandwidth, 240-V/s slew rate, and 60-ns settling time (0.1%). The THS4051/2 are stable at all gains for both inverting and noninverting configurations. These amplifiers have a high output drive capability of 100 mA and draw only 8.5-mA supply current per channel. Excellent professional video results can be obtained with the low differential gain/phase errors of 0.01%/ 0.01 and wide 0.1-dB flatness to 30 MHz. For applications requiring low distortion, the THS4051/2 is ideally suited with total harmonic distortion of -82 dBc at 1 MHz. THS4011/2 THS4031/2 THS4081/2 5 THS4052 D AND DGN PACKAGES (TOP VIEW) DESCRIPTION DEVICE 6 4 VCC- NC D 3 NULL VCC+ OUT NC NC D 7 NC D 8 2 NC - No internal connection - 0.1 dB Bandwidth of 30 MHz (G = 1) - 0.01% Differential Gain - 0.01 Differential Phase Very Low Distortion: - THD = -82 dBc (f = 1 MHz, RL = 150 ) - THD = -89 dBc (f = 1 MHz, RL = 1 k) Wide Range of Power Supplies: - VCC = 5 V to 15 V Available in Standard SOIC, MSOP PowerPAD, JG, or FK Packages Evaluation Module Available D 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. SMBus is a trademark of Intel Corp. All other trademarks are the property of their respective owners. Copyright 1999-2008, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ www.ti.com www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)(1) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . 300C Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE D DGN JG JA (C/W) 167 JC (C/W) TA = 25 25C C POWER RATING 38.3 740 mW 58.4 4.7 2.14 W 119 28 1050 mW FK 87.7 20 1375 mW This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K test PCB, the JA is 95C/W with a power rating at TA = 25C of 1.32 W. This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. x 3 in. PC. For further information, refer to Application Information section of this data sheet. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC+ and VCC- Operating free-air temperature, TA 2 NOM MAX Dual supply 4.5 16 Single supply 9 32 C-suffix 0 70 I-suffix -40 85 M-suffix -55 125 UNIT V C C www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 AVAILABLE OPTIONS(1) PACKAGED DEVICES NUMBER OF CHANNELS TA 1 0C to 70C -40C to 85C PLASTIC MSOP (DGN) PLASTIC SMALL OUTLINE (D) THS4051CD CERAMIC DIP (JG) CHIP CARRIER (FK) EVALUATION MODULE DEVICE SYMBOL ACQ -- -- THS4051EVM 2 THS4052CD THS4051CDGN THS4052CDGN ACE -- -- THS4052EVM 1 THS4051ID THS4051IDGN ACR -- -- -- THS4052ID THS4052IDGN ACF -- -- -- 2 -55C to 125C 1 -- -- -- THS4051MJG THS4051MFK -- (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4051CDGN). This device is in the Product Preview stage of development. Please contact your local TI sales office for availability. FUNCTIONAL BLOCK DIAGRAM VCC 1IN- 1OUT 1IN+ Null 2IN- IN- IN+ 2 2OUT 1 2IN+ 8 6 OUT 3 -VCC Figure 2. THS4052 - Dual Channel Figure 1. THS4051 - Single Channel T THD - Total Harmonic Distortion - dBc -40 -50 HARMONIC DISTORTION vs FREQUENCY VCC = 15 V Gain = 2 VO(PP) = 2 V -60 RL = 150 -70 -80 RL = 1 k -90 -100 100k 1M f - Frequency - Hz 10M 20M 3 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS AT TA = 25C, VCC = 15 V, RL = 150 (unless otherwise noted) dynamic performance MIN TYP VCC = 15 V VCC = 5 V Gain = 1 VCC = 15 V VCC = 5 V Gain = 2 Bandwidth for 0.1 dB flatness VCC = 15 V VCC = 5 V Gain = 1 Full power bandwidth VO(pp) = 20 V, VO(pp) = 5 V, VCC = 15 V VCC = 5 V Slew rate VCC = 15 V, VCC = 5 V, 20-V step, Gain = 5 240 5-V step Gain = -1 200 VCC = 15 V, VCC = 5 V, 5-V step Settling time to 0.1% Settling time to 0.01% VCC = 15 V, VCC = 5 V, 5-V step Dynamic performance small-signal bandwidth (-3 dB) BW SR THS405xC, THS405xI TEST CONDITIONS PARAMETER ts MAX UNIT 70 MHz 70 38 MHz 38 30 2-V step 2-V step MHz 30 3.8 MHz 12.7 V/ s V/s 60 Gain = -1 ns 60 130 Gain = -1 ns 140 Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix Slew rate is measured from an output level range of 25% to 75%. Full power bandwidth = slew rate/2 VO(Peak). noise/distortion performance THD Vn In Total harmonic distortion VO(pp) = 2 V, f = 1 MHz, Gain = 2 VCC = 5 V or 15 V, VCC = 5 V or 15 V, Input voltage noise Input current noise MIN RL = 150 RL = 1 k -82 VCC = 5 V RL = 150 RL = 1 k -78 f = 10 kHz f = 10 kHz Differential gain error Gain = 2, 40 IRE modulation, NTSC, 100 IRE ramp Differential phase error Gain = 2, 40 IRE modulation, NTSC, 100 IRE ramp VCC = 15 V VCC = 5 V VCC = 5 V or 15 V, f = 1 MHz crosstalk Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix. TYP VCC = 15 V VCC = 15 V VCC = 5 V Channel-to-channel (THS4052 only) 4 THS405xC, THS405xI TEST CONDITIONS PARAMETER MAX UNIT -89 dBc -87 14 nV/Hz 0.9 pA/Hz 0.01% 0.01 0.01% 0.03 -57 dB www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 electrical characteristics at TA = 25C, VCC = 15 V, RL = 150 (unless otherwise noted) (continued) dc performance PARAMETER THS405xC, THS405xI TEST CONDITIONS TYP 9 VCC = 15 V, RL = 1 k VO = 10 V TA = 25C TA = full range 5 VCC = 5 V, RL = 250 VO = 2.5 V TA = 25C TA = full range 2.5 Open loop gain Input offset voltage VCC = 5 V or 15 V Offset voltage drift VCC = 5 V or 15 V IIB Input bias current VCC = 5 V or 15 V IOS Input offset current VCC = 5 V or 15 V VOS MIN MAX V/mV 3 6 V/mV 2 TA = 25C TA = full range 2.5 TA = full range TA = 25C 15 10 12 2.5 TA = full range TA = 25C 35 TA = full range mV V/C 6 8 A A 250 400 Offset current drift TA = full range Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix UNIT 0.3 nA nA/C input characteristics PARAMETER TEST CONDITIONS VICR Common-mode input voltage range VCC = 15 V VCC = 5 V CMRR Common mode rejection ratio VCC = 15 V, VCC = 5 V, VICR = 12 V VICR = 2.5 V THS405xC, THS405xI TA = full range MIN TYP 13.8 14.3 3.8 4.3 70 100 70 100 ri Input resistance Ci Input capacitance Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix MAX UNIT V dB 1 M 1.5 pF output characteristics PARAMETER VO Output voltage swing TEST CONDITIONS VCC = 15 V VCC = 5 V RL = 250 RL = 150 VCC = 15 V VCC = 5 V RL = 1 k RL = 20 IO Output current VCC = 15 V VCC = 5 V ISC Short-circuit current VCC = 15 V THS405xC, THS405xI MIN TYP 11.5 13 3.2 3.5 13 13.6 3.5 3.8 80 100 50 75 150 MAX UNIT V V mA mA RO Output resistance Open loop 13 W Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. 5 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 electrical characteristics at TA = 25C, VCC = 15 V, RL = 150 (unless otherwise noted) (continued) power supply PARAMETER VCC ICC PSRR Supply voltage operating range THS405xC, THS405xI TEST CONDITIONS MIN MAX Dual supply 4.5 16.5 Single supply 9 33 VCC = 15 V TA = 25C TA = full range 8.5 VCC = 5 V TA = 25C TA = full range 7.5 VCC = 5 V or 15 V TA = 25C TA = full range Supply current (per amplifier) Power supply rejection ratio TYP UNIT V 10.5 11.5 9.5 mA 10.5 70 84 dB 68 Full range = 0C to 70C for C suffix and - 40C to 85C for I suffix ELECTRICAL CHARACTERISTICS AT TA = FULL RANGE, VCC = 15 V, RL = 1 K (UNLESS OTHERWISE NOTED) dynamic performance PARAMETER Unity gain bandwidth Dynamic performance small-signal bandwidth (-3 dB) BW Bandwidth for 0.1 dB flatness Full power bandwidth SR Slew rate Settling time to 0.1% ts Settling time to 0.01% Full range = -55C to 125C for the THS4051M. Full power bandwidth = slew rate/2 VO(Peak). This parameter is not tested. 6 THS4051M TEST CONDITIONS VCC = 15 V, VCC = 15 V Closed loop Gain = 1 70 MAX UNIT MHz 70 38 Gain = 2 VCC = 5 V VCC = 15 V VO(pp) = 5 V, VCC = 15 V, TYP 70 VCC = 5 V VCC = 15 V VCC = 5 V VO(pp) = 20 V, RL = 1 k MIN 50 MHz 38 30 Gain = 1 30 VCC = 15 V VCC = 5 V VCC = 5 V, VCC = 15 V, 5-V step VCC = 5 V, VCC = 15 V, 2-V step VCC = 5 V, 2-V step 3.8 12.7 RL = 1 k Gain = -1 5-V step 5-V step MHz 240 MHz 300 200 V/ s V/s 60 Gain = -1 Gain = -1 60 130 140 ns ns www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 electrical characteristics at TA = full range, VCC = 15 V, RL = 1 k (unless otherwise noted) noise/distortion performance PARAMETER TEST CONDITIONS THD VO(pp) = 2 V, f = 1 MHz, Gain = 2, TA = 25C Total harmonic distortion THS4051M MIN TYP VCC = 15 V RL = 150 RL = 1 k -82 VCC = 5 V RL = 150 RL = 1 k -78 MAX UNIT -89 dBc -87 Vn Input voltage noise VCC = 5 V or 15 V, TA = 25C f = 10 kHz, RL = 150 14 nV/Hz In Input current noise VCC = 5 V or 15 V, TA = 25C f = 10 kHz, RL = 150 0.9 pA/Hz Gain = 2, 40 IRE modulation, TA = 25C, NTSC, 100 IRE ramp, RL = 150 VCC = 15 V 0.01% Differential gain error VCC = 5 V 0.01% Gain = 2, 40 IRE modulation, TA = 25C, Full range = -55C to 125C for the THS4051M. NTSC, 100 IRE ramp, RL = 150 VCC = 15 V 0.01 VCC = 5 V 0.03 Differential phase error dc performance PARAMETER THS4051M TEST CONDITIONS TYP 9 VCC = 15 V, VO = 10 V TA = 25C TA = full range 5 VCC = 5 V, VO = 2.5 V TA = 25C TA = full range 2.5 VCC = 5 V or 15 V TA = 25C TA = full range 2.5 Input offset voltage Offset voltage drift VCC = 5 V or 15 V TA = full range TA = 25C 15 Open loop gain VIO MIN IIB Input bias current VCC = 5 V or 15 V IIO Input offset current VCC = 5 V or 15 V MAX V/mV 3 6 V/mV 2 10 13 2.5 TA = full range TA = 25C 35 TA = full range mV V/C 6 8 A A 250 400 Offset current drift TA = full range Full range = -55C to 125C for the THS4051M. UNIT 0.3 nA nA/C input characteristics PARAMETER TEST CONDITIONS VICR Common-mode input voltage range VCC = 15 V VCC = 5 V CMRR Common mode rejection ratio VCC = 15 V, VCC = 5 V, ri Input resistance Ci Input capacitance Full range = -55C to 125C for the THS4051M. VICR = 12 V VICR = 2.5 V THS4051M TA = full range MIN TYP 13.8 14.3 3.8 4.3 70 100 70 100 MAX UNIT V dB 1 M 1.5 pF 7 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 electrical characteristics at TA = full range, VCC = 15 V, RL = 1 k (unless otherwise noted) (continued) output characteristics TEST CONDITIONS PARAMETER VO Output voltage swing VCC = 15 V VCC = 5 V RL = 250 RL = 150 VCC = 15 V VCC = 5 V RL = 1 k VCC = 15 V, TA = 25C IO Output current ISC Short-circuit current VCC = 15 V, TA = full range RL = 20 VCC = 5 V VCC = 15 V THS4051M MIN TYP 12 13 3.2 3.5 13 13.6 3.5 3.8 80 100 MAX V V mA 70 50 UNIT 75 150 mA RO Output resistance Open loop 13 W Full range = -55C to 125C for the THS4051M. Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or shorted. See the absolute maximum ratings section of this data sheet for more information. power supply PARAMETER VCC ICC Supply voltage operating range 8 MIN TYP MAX Dual supply 4.5 16.5 Single supply 9 33 VCC = 15 V TA = 25C TA = full range 8.5 VCC = 5 V TA = 25C TA = full range 7.5 VCC = 5 V or 15 V TA = full range Supply current (per amplifier) PSRR Power supply rejection ratio Full range = -55C to 125C for the THS4051M. THS4051M TEST CONDITIONS UNIT V 10.5 11.5 9.5 mA 10.5 70 84 dB www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs FREE-AIR TEMPERATURE IB Input Bias Current - A 2.7 I 2.3 VCC = 5 V -1.5 -2.0 -2.5 VCC = 15 V -3.0 -3.5 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - C 2.6 2.5 2.4 7 9 11 13 VCC - Supply Voltage - V 15 Figure 5 SUPPLY CURRENT vs SUPPLY VOLTAGE 11 13.5 11 9 7 10 13 VCC = 15 V RL = 250 VCC = 15 V RL = 1 k 12.5 12 4.5 VCC = 5 V RL = 1 k 4 3.5 VCC = 5 V RL = 150 5 3 2.5 -40 3 7 9 11 13 VCC - Supply Voltage - V 15 VN 10 IN 100k PSRR - Power Supply Rejection Ratio - dB 100 Figure 9 TA=25C 7 TA=-40C 6 5 -20 0 20 40 60 80 100 5 7 9 11 13 VCC - Supply Voltage - V 0 CMRR vs FREQUENCY VCC = 15 V & 5 V -10 -20 -VCC -30 +VCC -40 -50 -60 -70 -80 -90 100k 1M 10M f - Frequency - Hz Figure 10 15 Figure 8 POWER-SUPPLY REJECTION RATIO vs FREQUENCY VCC = 15 V and 5V TA = 25C 1k 10k f - Frequency - Hz 8 Figure 7 VOLTAGE & CURRENT NOISE vs FREQUENCY 100 TA=85C 9 TA - Free-Air Temperature - _C Figure 6 1000 I CC - Supply Current - mA VO - Output Voltage - V 13 CMRR - Common-Mode Rejection Ratio - dB V V ICR - Common-Mode Input Voltage - 5 14 TA=25C V n - Voltage Noise - nV/ Hz I n - Current Noise - pA/ Hz 100 OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 15 0.10 10 RL = 150 6 Figure 4 COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE 1 8 2 -20 0 20 40 60 80 TA - Free-Air Temperature - C Figure 3 5 RL = 1 k 10 4 2.2 -40 100 TA=25C 12 V -0.5 14 VCC = 5 V & 15 V VO - Output Voltage - 2.8 V IO - Input Offset Voltage - mV 0.0 -1.0 OUTPUT VOLTAGE vs SUPPLY VOLTAGE INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE 100M -20 VCC = 15 V or 5 V RF = 1 k VI(PP) = 2 V -30 -40 -50 -60 -70 -80 -90 -100 10k 100k 1M 10M 100M f - Frequency - Hz Figure 11 9 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY OPEN LOOP GAIN AND PHASE RESPONSE vs FREQUENCY -20 30 VCC = 5 V & 15 V 80 -40 Open Loop Gain - dB Crosstalk - dB 100 -50 -60 -70 0 Gain 60 -30 40 Gain -60 20 -90 Phase 0 -80 100k 1M 10M 100M -120 -20 f - Frequency - Hz 1k Figure 12 Phase VCC = 15 V Gain = 2 RF = 3.6 k RL = 150 -30 10k 100k 1M f - Frequency - Hz 10M -150 100M Figure 13 -50 -50 VCC = 15 V Gain = 2 VO(PP) = 2 V -70 RL = 150 -50 VCC = 15 V RL = 1 k G=5 f = 1 MHz -55 -60 DISTORTION vs OUTPUT VOLTAGE DISTORTION vs OUTPUT VOLTAGE Distortion - dBc THD - Total Harmonic Distortion - dBc -40 HARMONIC DISTORTION vs FREQUENCY -60 -66 -70 VCC = 15 V RL = 150 G=5 f = 1 MHz -55 Distortion - dBc T 2nd Harmonic -75 -60 -66 2nd Harmonic -70 -75 -80 3rd Harmonic 3rd Harmonic -90 -85 -85 -90 -90 1M f - Frequency - Hz 10M 0 20M 5 15 0 20 5 VO - Output Voltage - V Figure 14 -40 VCC = 15 V RL = 1 k -50 G = 2 VO(PP) = 2 V Distortion - dBc -50 -60 -70 2nd Harmonic -40 VCC = 5 V RL = 1 k G=2 VO(PP) = 2 V -50 -70 2nd Harmonic -80 -90 -90 20 DISTORTION vs FREQUENCY -60 -80 15 Figure 16 DISTORTION vs FREQUENCY -40 10 VO - Output Voltage - V Figure 15 DISTORTION vs FREQUENCY Distortion - dBc 10 Distortion - dBc -100 100k -80 -80 RL = 1 k VCC = 15 V RL = 150 G=2 VO(PP) = 2 V -60 -70 2nd Harmonic -80 3rd Harmonic 3rd Harmonic -90 3rd Harmonic -100 -100 100k 10 1M 10M 100M -100 100k 1M 10M 100M 100k 1M 10M f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 17 Figure 18 Figure 19 100M www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY DISTORTION vs FREQUENCY -70 2nd Harmonic -80 3rd Harmonic 0 -1 -3 RF = 0 -90 -5 -100 10M VCC = 15 V Gain = 1 RL = 150 VO(PP) = 62 mV -6 100k 100M f - Frequency - Hz Figure 20 0.2 0.3 RF = 750 Output Amplitude - dB Output Amplitude - dB 0.3 0.1 -0.0 -0.1 RF = 620 -0.2 RF = 0 -0.3 -0.4 100k 0.2 6.3 RF = 3.6 k Output Amplitude - dB Output Amplitude - dB 6.4 6 5 RF = 2.7 k 4 RF = 1 k VCC = 5 V Gain = 2 RL = 150 VO(PP) = 125 mV 1M 10M f - Frequency - Hz Figure 26 RF = 3.6 k RF = 620 5 3 RF = 1 k 2 1 RF = 0 1M 10M f - Frequency - Hz RF = 2.7 k 4 VCC = 15 V Gain = 2 RL = 150 VO(PP) = 125 mV 0 100k 100M 6.2 VCC = 15 V Gain = 2 RL = 150 VO(PP) = 125 mV 6.3 5.9 RF = 2.7 k 5.7 100M 6.4 RF = 3.6 k 6.0 5.6 100k 100M OUTPUT AMPLITUDE vs FREQUENCY 6.1 5.8 1M 10M f - Frequency - Hz Figure 25 OUTPUT AMPLITUDE vs FREQUENCY 7 100M 6 Figure 24 8 0 100k 7 RF = 750 -0.1 -0.4 100k 100M 1M 10M f - Frequency - Hz OUTPUT AMPLITUDE vs FREQUENCY 0.1 -0.2 RF = 0 VCC = 5 V Gain = 1 RL = 150 VO(PP) = 62 mV Figure 22 -0.0 OUTPUT AMPLITUDE vs FREQUENCY 1 -4 8 VCC = 5 V Gain = -1 RL = 150 VO(PP) = 62 mV Figure 23 2 -3 -6 100k 100M -0.3 1M 10M f - Frequency - Hz 3 RF = 620 -2 OUTPUT AMPLITUDE vs FREQUENCY 0.4 VCC = 15 V Gain = 1 RL = 150 VO(PP) = 62 mV -1 Figure 21 OUTPUT AMPLITUDE vs FREQUENCY 0.4 1M 10M f - Frequency - Hz RF = 750 0 -5 Output Amplitude - dB 1M RF = 620 -2 -4 1 RF = 750 Output Amplitude - dB -60 100k 2 1 Output Amplitude - dB -50 Distortion - dBc 2 VCC = 5 V RL = 150 G=2 VO(PP) = 2 V Output Amplitude - dB -40 OUTPUT AMPLITUDE vs FREQUENCY 6.2 VCC = 5 V Gain = 2 RL = 150 VO(PP) = 125 mV 6.1 RF = 3.6 k 6.0 5.9 RF = 2.7 k 5.8 5.7 RF = 1 k 1M 10M f - Frequency - Hz Figure 27 100M 5.6 100k RF = 1 k 1M 10M f - Frequency - Hz 100M Figure 28 11 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS OUTPUT AMPLITUDE vs FREQUENCY OUTPUT AMPLITUDE vs FREQUENCY 2 CL= 10 pF 1 6 Output Amplitude - dB 5 RL = 1 k 4 RL = 150 3 2 VCC = 15 V Gain = 2 RL = 2.7 k VO(PP) = 125 mV 1 0 100k 0 -1 RF = 3.9 k -2 RF = 1 k -3 VCC = 15 V Gain = -1 RL = 150 VO(PP) = 62 mV -4 -5 1M 10M f - Frequency - Hz -6 100k 100M Figure 29 VO(PP)=0.4 V -10 -20 VCC = 15 V Gain = 2 RF = 2.7 k RL = 150 -25 VCC = 5 V 0.01% 100 VCC = 15 V 0.1% 80 VCC = 5 V 0.1% 0.04 RF = 360 1M 10M f - Frequency - Hz 1 100M 2 3 4 VO - Output Step Voltage - V Differential Phase VCC = 5 V 0 0.6 Number of 150- Loads Figure 35 4 Gain = 2 40 IRE-PAL Modulation Worst Case 100 IRE Ramp 0.5 0.3 VCC = 15 V 0.2 VCC = 5 V 0.4 VCC = 15 V 0.3 VCC = 5 V 0.2 0.1 0 3 4 DIFFERENTIAL PHASE vs NUMBER OF 150- LOADS 0.1 0.04 3 Figure 34 Gain = 2 RF = 1 k 40 IRE-NTSC Modulation Worst Case 100 IRE Ramp 0.4 0.08 2 Number of 150- Loads 0.5 VCC = 15 V 2 1 DIFFERENTIAL PHASE vs NUMBER OF 150- LOADS 0.12 VCC = 5 V 0 5 Figure 33 Gain = 2 40 IRE-PAL Modulation Worst Case 100 IRE Ramp 1 VCC = 15 V 0.06 0.02 20 DIFFERENTIAL GAIN vs NUMBER OF 150- LOADS 0.16 0.08 60 40 100M Gain = 2 40 IRE-NTSC Modulation Worst Case 100 IRE Ramp 0.10 VCC = 15 V 0.01% 120 1M 10M f - Frequency - Hz DIFFERENTIAL GAIN vs NUMBER OF 150- LOADS 0.12 Figure 32 0.2 VCC = 5 V Gain = -1 RL = 150 VO(PP) = 62 mV -4 Figure 31 140 VO(PP)=125 mV RF = 1 k -3 -6 100k 100M Differential Gain - % 0 -30 100k Differential Gain - % 1M 10M f - Frequency - Hz 160 Settling Time - ns V O(PP) - Output Voltage - dBV VO(PP)=2.25 V -15 RF = 3.9 k -2 -5 180 -5 -1 SETTING TIME vs OUTPUT STEP 10 5 RF = 5.6 k 0 Figure 30 OUTPUT AMPLITUDE vs FREQUENCY 12 1 RF = 5.6 k Differential Phase Output Amplitude - dB 7 2 Output Amplitude - dB 8 OUTPUT AMPLITUDE vs FREQUENCY 0 1 2 3 4 1 2 3 Number of 150- Loads Number of 150- Loads Figure 36 Figure 37 4 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 TYPICAL CHARACTERISTICS 1-V STEP RESPONSE 5-V STEP RESPONSE -0.0 -0.2 -0.4 0.6 2 0.4 1 0 -1 VCC = 5 V Gain = -1 RF = 3.9 k RL = 150 -2 -0.6 50 100 150 200 250 300 350 400 t - Time - ns VCC = 15 V Gain = 2 RF = 2.7 k RL = 150 0.2 -0.0 -0.2 -0.4 -3 0 -0.6 0 50 100 150 200 250 300 350 400 t - Time - ns Figure 38 Figure 39 0 50 100 150 200 250 300 350 400 t - Time - ns Figure 40 20-V STEP RESPONSE 15 VCC = 15 V Gain = 5 RF = 2.7 k RL = 150 & 1 k 10 V O - Output Voltage - V V O - Output Voltage - V 0.2 1-V STEP RESPONSE 3 V O - Output Voltage - V VCC = 5 V Gain = 2 RF = 2.7 k RL = 150 0.4 V O - Output Voltage - V 0.6 5 0 -5 -10 -15 0 100 200 300 t - Time - ns 400 500 Figure 41 13 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION THEORY OF OPERATION bipolar process with NPN and PNP transistors possessing fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 42. The THS405x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary (7) VCC + (6) OUT IN - (2) IN + (3) (4) VCC - NULL (1) NULL (8) Figure 42. THS405x Simplified Schematic NOISE CALCULATIONS AND NOISE FIGURE Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ratio (SNR) is very important. The noise model for the THS405x is shown in Figure 43. This model includes all of the noise sources as follows: * * * * 14 en = Amplifier internal voltage noise (nV/Hz) IN+ = Noninverting current noise (pA/Hz) IN- = Inverting current noise (pA/Hz) eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx ) www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) RS eRs en eni IN+ IN- Figure 43. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + en ) IN ) 2 R S 2 ) IN- R F o R G 2 ) 4 kTRs ) 4 kT R o R F G Where: k = Boltzmann's constant = 1.380658 x 10-23 T = Temperature in degrees Kelvin (273 +C) RF || RG = Parallel resistance of RF and RG To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + e ni A V + e ni 1 ) RF (noninverting case) RG As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier to calculate. For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier Circuits Applications Report (literature number SLVA043). 15 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION NOISE CALCULATIONS AND NOISE FIGURE (CONTINUED) This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is typically 50 in RF applications. NF + e 2 10log ni 2 eRs Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage, we can approximate noise figure as: NF + 2 en ) IN ) 10log1 ) 4 kTR S S 2 R Figure 44 shows the noise figure graph for the THS405x. NOISE FIGURE vs SOURCE RESISTANCE 40 f = 10 kHz TA = 25C 35 Noise Figure (dB) 30 25 20 15 10 5 0 10 100 1k 10k Source Resistance - 100k Figure 44. Noise Figure vs Source Resistance 16 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION DRIVING A CAPACITIVE LOAD Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 45. A minimum value of 20 should work well for most applications. For example, in 75- transmission systems, setting the series resistor value to 75 both isolates any capacitance loading and provides the proper line impedance matching at the source end. 1 k 1 k Input _ 20 Output THS405x + CLOAD Figure 45. Driving a Capacitive Load OFFSET NULLING The THS405x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4051. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This is shown in Figure 46. VCC+ 0.1 F + THS4051 _ 10 k 0.1 F VCC - Figure 46. Offset Nulling Schematic 17 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION OFFSET VOLTAGE The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF RG +IIB- - - +IIB+ V OO +V IO 1) R R VO + RS F G "I IB) R + VIO S 1) R R F G "I IB* R F Figure 47. Output Offset Voltage Model OPTIMIZING UNITY GAIN RESPONSE Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. This is because a minimum phase margin is maintained for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 620 should be used as shown in Figure 48. Additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. Input + THS405x Output _ 620 Figure 48. Noninverting, Unity Gain Schematic 18 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL CONFIGURATIONS When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 49). RG RF - + VI R1 C1 f -3dB + Figure 49. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C VI R1 R2 C2 RG Figure 50. 2-Pole Low-Pass Sallen-Key Filter 19 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION CIRCUIT LAYOUT CONSIDERATIONS To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high frequency design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation board is available to use as a guide for layout or for evaluating the device performance. D Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling - Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets - Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements - Optimum high frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components - Using surface-mount passive components is recommended for high frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. GENERAL POWERPAD DESIGN CONSIDERATIONS The THS405x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 51(a) and Figure 51(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 51(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking. 20 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) DIE Side View (a) Thermal Pad DIE End View (b) NOTE A: Bottom View (c) The thermal pad is electrically isolated from all terminals in the package. Figure 51. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink this device, the following steps illustrate the recommended approach. Thermal pad area (68 mils x 70 mils) with 5 vias (Via diameter = 13 mils) Figure 52. PowerPAD PCB Etch and Via Pattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS405xDGN IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS405xDGN package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the THS405xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. 21 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches x 3 inches (or 76.2 mm x 76.2 mm), then the expected thermal coefficient, JA, is about 58.4C/W. For comparison, the non-PowerPAD version of the THS405x IC (SOIC) is shown. For a given JA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula: P Where: D + T -T MAX A q JA PD = Maximum power dissipation of THS405x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 3.5 DGN Package JA = 58.4C/W 2 oz. Trace And Copper Pad With Solder Maximum Power Dissipation - W 3 2.5 SOIC Package High-K Test PCB JA = 98C/W 2 DGN Package JA = 158C/W 2 oz. Trace And Copper Pad Without Solder 1.5 1 0.5 SOIC Package Low-K Test PCB JA = 167C/W 0 -40 NOTE A: TJ = 150C -20 0 20 40 60 80 TA - Free-Air Temperature - C 100 Results are with no air flow and PCB size = 3"x 3" Figure 53. Maximum Power Dissipation vs Free-Air Temperature More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. 22 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially devices with multiple amplifiers. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 54 to Figure 57 show this effect, along with the quiescent heat, with an ambient air temperature of 50C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier's limits and failure may result. When using VCC = 5 V, there is generally not a heat problem, even with SOIC packages. But, when using VCC = 15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4052), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier outputs are identical. THS4051 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS VCC = 5 V Tj = 150C TA = 50C 180 1000 Maximum Output Current Limit Line | IO | - Maximum RMS Output Current - mA | IO | - Maximum RMS Output Current - mA 200 160 140 Package With JA < = 120C/W 120 100 SO-8 Package JA = 167C/W Low-K Test PCB 80 60 40 Safe Operating Area 20 1 2 3 4 | VO | - RMS Output Voltage - V Figure 54 TJ = 150C TA = 50C VCC = 15 V Maximum Output Current Limit Line DGN Package JA = 58.4C/W 100 SO-8 Package JA = 98C/W High-K Test PCB SO-8 Package JA = 167C/W Low-K Test PCB Safe Operating Area 10 0 0 THS4051 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 5 0 3 6 9 12 15 | VO | - RMS Output Voltage - V Figure 55 23 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION GENERAL POWERPAD DESIGN CONSIDERATIONS (CONTINUED) THS4052 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 160 140 120 100 SO-8 Package JA = 167C/W Low-K Test PCB 80 60 Safe Operating Area 40 SO-8 Package JA = 98C/W High-K Test PCB 20 0 0 VCC = 5 V TJ = 150C TA = 50C Both Channels 1 2 3 4 | VO | - RMS Output Voltage - V Figure 56 24 1000 Maximum Output Current Limit Line Package With JA 60C/W | IO | - Maximum RMS Output Current - mA | IO | - Maximum RMS Output Current - mA 200 THS4052 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS VCC = 15 V TJ = 150C TA = 50C Both Channels Maximum Output Current Limit Line 100 SO-8 Package JA = 98C/W High-K Test PCB 10 DGN Package JA = 58.4C/W Safe Operating Area 5 1 0 SO-8 Package JA = 167C/W Low-K Test PCB 3 6 9 12 | VO | - RMS Output Voltage - V Figure 57 15 www.ti.com SLOS238D - MAY 1999 - REVISED AUGUST 2008 APPLICATION INFORMATION EVALUATION BOARD An evaluation board is available for the THS4051 (literature number SLOP220) and THS4052 (literature number SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the evaluation board is shown in Figure 58. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, please refer to the THS4051 EVM User's Guide or the THS4052 EVM User's Guide. To order the evaluation board, contact your local TI sales office or distributor. VCC+ + C5 0.1 F R4 2 k IN + C2 6.8 F NULL R5 49.9 + R3 49.9 OUT THS4051 _ NULL R2 2 k + C4 0.1 F C1 6.8 F IN - R1 49.9 VCC - Figure 58. THS4051 Evaluation Board Schematic 25 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS4051CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4051IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDGNR ACTIVE MSOP- DGN 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Sep-2008 Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Power PAD Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) THS4052CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4052IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4051 : * Military: THS4051M NOTE: Qualified Version Definitions: * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS4051CDGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4051CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4051IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4051IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4052CDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4052CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4052IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4052IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4051CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4051CDR SOIC D 8 2500 367.0 367.0 35.0 THS4051IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4051IDR SOIC D 8 2500 367.0 367.0 35.0 THS4052CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4052CDR SOIC D 8 2500 367.0 367.0 35.0 THS4052IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 THS4052IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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