VNQ5027AK-E Quad channel high side driver with analog current sense for automotive applications Features Max supply voltage VCC 41V Operating voltage range VCC 4.5 to 36 V Max on-state resistance (per ch.) RON 27 m Current limitation (typ) ILIMH 42 A Off-state supply current IS 2 A(1) PowerSSO-24 Applications 1. Typical value with all loads connected. All types of resistive, inductive and capacitive loads Output current: 42A Suitable as LED driver 3.0 V CMOS compatible input Current sense disable Proportional load current sense Undervoltage shut-down Overvoltage clamp Thermal shutdown Current and power limitation Very low standby current Protection against loss of ground and loss of VCC Very low electromagnetic susceptibility Optimized electromagnetic emission Reverse battery protection (see Application schematic on page 20) In compliance with the 2002/95/EC European directive Package: ECOPACK(R) Table 1. Description The VNQ5027AK-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog Current Sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Device summary Order codes Package PowerSSO-24 July 2009 Tube Tape and reel VNQ5027AK-E VNQ5027AKTR-E Doc ID 12730 Rev 6 1/31 www.st.com 1 Contents VNQ5027AK-E Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 6 2/31 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 PowerSSO-24TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 12730 Rev 6 VNQ5027AK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V; Tj= 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current Sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 12730 Rev 6 3/31 List of figures VNQ5027AK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 4/31 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of output current and rising edge of Current Sense (CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24 PowerSSO-24TM thermal impedance junction ambient single pulse (one channel on). . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-24TM . . . . . . . . . . . . . . . . . 25 PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-24TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 12730 Rev 6 VNQ5027AK-E 1 Block diagram and pin configuration Block diagram and pin configuration Figure 1. Block diagram VCC UNDERVOLTAGE VCC CLAMP OUTPUT1 PwCLAMP 1 GND DRIVER 1 ILIM 1 INPUT1 VDSLIM 1 LOGIC INPUT2 INPUT2 VCC Control & Protection CURRENT Equivalent to SENSE2 channel1 OVERTEMP. 1 INPUT3 INPUT3 IOUT1 K1 INPUT4 PwrLIM 1 CS_DIS Table 2. CURRENT SENSE1 OUTPUT2 VCC CURRENT SENSE2 Control & Protection to CURRENT Equivalent SENSE3 channel1 INPUT4 Control & Protection to CURRENT Equivalent SENSE4 channel1 OUTPUT3 VCC CURRENT SENSE3 OUTPUT4 CURRENT SENSE4 Pin functions Name VCC OUTPUTn GND INPUTn CURRENT SENSEn CS_DIS Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current. Active high CMOS compatible pin to disable the current sense pin. Doc ID 12730 Rev 6 5/31 Block diagram and pin configuration Figure 2. VNQ5027AK-E Configuration diagram (top view) VCC OUTPUT1 GND OUTPUT1 INPUT1 OUTPUT1 CURRENT SENSE1 OUTPUT2 INPUT2 OUTPUT2 CURRENT SENSE2 OUTPUT2 INPUT3 OUTPUT3 CURRENT SENSE3 OUTPUT3 INPUT4 OUTPUT3 CURRENT SENSE4 OUTPUT4 CS_DIS. OUTPUT4 VCC OUTPUT4 TAB = VCC Table 3. Suggested connections for unused and not connected pins Connection / pin Current Sense N.C. Output Input CS_DIS Floating N.R.(1) X X X X To ground Through 1 k resistor X N.R. Through 10 k resistor Through 10 k resistor 1. Not recommended. 6/31 Doc ID 12730 Rev 6 VNQ5027AK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC OUTPUTn CS_DIS VOUTn ISENSEn IINn VINn VCC IOUTn ICSD VCSD VFn CURRENT SENSEn INPUTn VSENSEn GND IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the "Absolute maximum ratings" tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage 0.3 V - IGND DC reverse ground pin current 200 mA Internally limited A 24 A DC Input current -1 to 10 mA DC Current Sense disable Input current -1 to 10 mA 200 mA VCC-41 +VCC V V 140 mJ IOUT - IOUT IIN ICSD DC output current Reverse DC output current -ICSENSE DC Reverse CS pin current VCSENSE Current Sense maximum voltage EMAX Maximum switching energy (single pulse) (L=0.8 mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.)) Doc ID 12730 Rev 6 7/31 Electrical specifications Table 4. Absolute maximum ratings (continued) Symbol Value Unit VESD Electrostatic discharge (human body model: R=1.5K; C=100pF) - Input - Current sense - CS_DIS - Output - VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature - 40 to 150 C Storage temperature - 55 to 150 C Tj Tstg 2.2 Parameter Thermal data Table 5. Symbol 8/31 VNQ5027AK-E Thermal data Parameter Rthj-case Thermal resistance junction-case (with one channel ON) Rthj-amb Thermal resistance junction-ambient Doc ID 12730 Rev 6 Max value Unit 1.35 C/W See Figure 29. C/W VNQ5027AK-E 2.3 Electrical specifications Electrical characteristics Values specified in this section are for 8 V<VCC<36 V, -40 C< Tj <150 C, unless otherwise stated. Table 6. Power section Symbol Parameter VCC Operating supply voltage VUSD VUSDhyst RON Vclamp Test conditions Min. Typ. Max. Unit 4.5 13 36 V Undervoltage shutdown 3.5 4.5 V Undervoltage shut-down hysteresis 0.5 On-state resistance IOUT= 3A; Tj= 25C IOUT= 3A; Tj= 150C IOUT= 3A; VCC=5V; Tj= 25C Clamp voltage IS= 20 mA 41 Off-state; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V IS VF 27 54 37 m m m 46 52 V 2(1) 5( 1) A 8 14 mA 0.01 3 Supply current On-state; VCC=13V; VIN=5V; IOUT=0A IL(off) V VIN=VOUT=0V; VCC=13V; T j=25C Off-state output current(2) VIN=VOUT=0V; VCC=13V; Tj=125C Output - VCC diode voltage(2) 0 0 A 5 -IOUT=3A; Tj=150C 0.7 V 1. PowerMOS leakage included. 2. For each channel. Table 7. Symbol Switching (VCC=13V; Tj= 25C) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL= 4.3 (see Figure 6.) 40 s td(off) Turn-off delay time RL= 4.3 (see Figure 6.) 40 s (dVOUT/dt)on Turn-on voltage slope RL= 4.3 See Figure 19. V/s (dVOUT/dt)off Turn-off voltage slope RL= 4.3 See Figure 21. V/s WON Switching energy losses during twon RL= 4.3 (see Figure 6.) 0.2 mJ WOFF Switching energy losses during twoff RL= 4.3 (see Figure 6.) 0.3 mJ Doc ID 12730 Rev 6 9/31 Electrical specifications Table 8. Current Sense (8V<VCC<16V) Symbol K0 dK0/K0(1) K1 dK1/K1 (1) K2 dK2/K2(1) K3 dK3/K3(1) ISENSE0 IOL VSENSE 10/31 VNQ5027AK-E Parameter Test conditions Min. Typ. Max. 2910 4120 IOUT/ISENSE IOUT= 0.5A; VSENSE= 0.5 V; VCSD=0 V; Tj= -40C...150C 1680 Current sense ratio drift IOUT= 0.5A; VSENSE= 0.5V; VCSD= 0V; TJ= -40 C to 150 C -12 IOUT/ISENSE IOUT= 2A; VSENSE= 4 V; VCSD=0 V; Tj= -40C...150C Tj= 25C...150C Current sense ratio drift IOUT= 2A; VSENSE= 4V; VCSD= 0V; TJ= -40 C to 150 C IOUT/ISENSE IOUT= 3A; VSENSE= 4 V; VCSD=0 V; Tj= -40C...150C Tj= 25C...150C Current sense ratio drift IOUT= 3A; VSENSE= 4V; VCSD= 0V; TJ= -40 C to 150 C IOUT / ISENSE IOUT= 10A; VSENSE= 4 V; VCSD= 0 V; Tj= -40C...150C Tj= 25C...150C Current sense ratio drift IOUT= 10A; VSENSE= 4 V; VCSD= 0V; TJ= -40 C to 150 C 2050 2190 12 2700 2700 -10 2260 2350 -7 2490 2590 % 3160 3030 7 2700 2700 % 3410 3210 10 2690 2690 Unit % 2870 2800 -4 4 % IOUT= 0A; VSENSE= 0V; VCSD= 5V; VIN= 0V; Tj= -40C...150C 0 1 A VCSD= 0V; VIN= 5V; Tj= -40C...150C 0 2 A IOUT= 2A; VSENSE= 0V; VCSD= 5V; VIN= 5V; Tj= -40C...150C 0 1 A open load on-state current detection threshold VIN = 5V, ISENSE= 5 A 5 30 mA Max analog sense output voltage IOUT= 3A; VCSD= 0V 5 Analog sense leakage current Doc ID 12730 Rev 6 V VNQ5027AK-E Table 8. Electrical specifications Current Sense (8V<VCC<16V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VSENSEH Analog sense output voltage in VCC= 13V; RSENSE= 3.9K over temperature condition 9 V ISENSEH Analog sense output current in VCC= 13V; VSENSE= 5V over temperature condition 8 mA tDSENSE1H Delay response time from falling edge of CS_DIS pin VSENSE<4V, 0.5A<Iout<10A ISENSE= 90% of ISENSE max (see Figure 4.) 50 100 s tDSENSE1L Delay response time from rising edge of CS_DIS pin VSENSE<4V, 0.5A<Iout<10A ISENSE=10% of ISENSE max (see Figure 4.) 5 20 s tDSENSE2H Delay response time from rising edge of INPUT pin VSENSE<4V, 0.5A<Iout<10A ISENSE=90% of ISENSE max (see Figure 4.) 70 300 s tDSENSE2H Delay response time between rising edge of output current and rising edge of current sense VSENSE < 4V, ISENSE = 90% of ISENSEMAX, IOUT = 90% of IOUTMAX IOUTMAX=2A (see Figure 5) tDSENSE2L Delay response time from falling edge of input pin VSENSE<4V, 0.5A<Iout<10A ISENSE=10% of ISENSE max (see Figure 4.) 200 s 100 250 s Min. Typ. Max. Unit 29 42 59 59 A A 1. Parameter guaranteed by design; it is not tested. Table 9. Protection(1) Symbol Parameter IlimH DC short circuit current VCC=13V 5V<VCC<36V IlimL Short circuit current during thermal cycling VCC=13V; TR<Tj<TTSD TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of STATUS THYST VDEMAG VON Test conditions 16 150 175 A 200 TRS + 1 TRS + 5 135 Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp IOUT= 2A; VIN=0; L=6mH Output voltage drop limitation IOUT=0.2A; Tj=-40C...150C (see Figure 9.) C C C 7 C VCC-41 VCC-46 VCC-52 V 25 mV 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Doc ID 12730 Rev 6 11/31 Electrical specifications Table 10. VNQ5027AK-E Logic input Symbol Parameter Test conditions VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN= 0.9V ICSDL Low level CS_DIS current VCSDH CS_DIS high level voltage ICSDH High level CS_DIS current VCSD=0.9V Figure 4. Unit 0.9 V 1 A 2.1 V 10 5.5 7 V V 0.9 V -0.7 1 A 2.1 V 10 0.25 ICSD= 1mA ICSD= -1mA CS_DIS clamp voltage 5.5 7 -0.7 INPUT CS_DIS LOAD CURRENT SENSE CURRENT 12/31 tDSENSE1L Doc ID 12730 Rev 6 tDSENSE1H A V Current sense delay characteristics tDSENSE2H A V VCSD=2.1V VCSD(hyst) CS_DIS hysteresis voltage VCSCL Max. 0.25 IIN= 1mA IIN= -1mA CS_DIS low level voltage Typ. VIN= 2.1V Input clamp voltage VCSDL Min. tDSENSE2L V V VNQ5027AK-E Electrical specifications Figure 5. Delay response time between rising edge of output current and rising edge of Current Sense (CS enabled) VIN tDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t Figure 6. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t Doc ID 12730 Rev 6 13/31 Electrical specifications Figure 7. VNQ5027AK-E IOUT/ISENSE vs IOUT Iout / Isense 4500 4000 3500 max Tj = -40 C to 150 C 3000 max Tj = 25 C to 150 C typical value 2500 min Tj = 25 C to 150 C min Tj = -40 C to 150 C 2000 1500 1000 2 Figure 8. 4 6 8 IOUT (A) 10 Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 2 3 4 5 6 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 14/31 Doc ID 12730 Rev 6 7 8 9 10 VNQ5027AK-E Electrical specifications Table 11. Truth table Input Output Sense (VCSD=0V)(1) Normal operation L H L H 0 Nominal Overtemperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Short circuit to GND (Rsc 10 m) L H H L L L 0 0 if Tj < TTSD VSENSEH if Tj > TTSD Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Conditions 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. Figure 9. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) Table 12. Electrical transient requirements (part 1/3) ISO 7637-2: 2004(E) Test levels test pulse III IV Number of pulses or test times 1 -75 V -100 V 5000 pulses 0.5 s 5s 2 ms, 10 2a +37 V +50 V 5000 pulses 0.2 s 5s 50 s, 2 3a -100 V -150 V 1h 90 ms 100 ms 0.1 s, 50 3b +75 V +100 V 1h 90 ms 100 ms 0.1 s, 50 Doc ID 12730 Rev 6 Burst cycle/pulse repetition time Delays and Impedance 15/31 Electrical specifications Table 12. VNQ5027AK-E Electrical transient requirements (part 1/3) (continued) ISO 7637-2: 2004(E) Test levels test pulse III IV Number of pulses or test times 4 -6 V -7 V 1 pulse 100 ms, 0.01 +65 V +87 V 1 pulse 400 ms, 2 5b (2) Table 13. Burst cycle/pulse repetition time Delays and Impedance Electrical transient requirements (part 2/3) Test level results(1) ISO 7637-2: 2004(E) test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b (2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 14. 16/31 Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 12730 Rev 6 VNQ5027AK-E 2.4 Electrical specifications Electrical characteristics curves Figure 10. Off-state output current Figure 11. High level input current Iih (A) Iloff (nA) 1000 5 900 4,5 Vin=2.1V 800 4 Off State Vcc=13V 700 3,5 600 3 500 2,5 400 2 300 1,5 200 1 100 0,5 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 12. Input clamp voltage Figure 13. Input low level Vil (V) Vicl (V) 2 8 1,8 lin=1mA 7,5 1,6 1,4 7 1,2 1 6,5 0,8 6 0,6 0,4 5,5 0,2 0 5 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 14. Input high level Figure 15. Input hysteresis voltage Vih (V) Vihyst (V) 4 1 0,9 3,5 0,8 3 0,7 2,5 0,6 2 0,5 0,4 1,5 0,3 1 0,2 0,5 0,1 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) -50 -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 12730 Rev 6 17/31 Electrical specifications VNQ5027AK-E Figure 16. On-state resistance vs Tcase Figure 17. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 100 60 50 80 Iout= 3A Vcc=13V Tc=150C 40 60 Tc=125C 30 Tc=25C 40 20 Tc=-40C 20 10 0 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 Tc (C) 20 25 30 35 40 Vcc (V) Figure 18. Undervoltage shutdown Figure 19. Turn-on voltage slope Vusd (V) (dVout/dt )On (V/ms) 8 1000 900 7 Vcc=13V RI=4.3 Ohm 800 6 700 5 600 4 500 400 3 300 2 200 1 100 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 20. ILIMH vs Tcase Figure 21. Turn-off voltage slope Ilimh (A) (dVout/dt )Off (V/ms) 60 600 550 55 Vcc=13V RI= 4.3 Ohm 500 Vcc=13V 450 50 400 45 350 300 40 250 35 200 150 30 100 25 50 0 20 -50 -25 0 25 50 75 100 125 150 175 18/31 -50 -25 0 25 50 75 Tc (C) Tc (C) Doc ID 12730 Rev 6 100 125 150 175 VNQ5027AK-E Electrical specifications Figure 22. CS_DIS high level voltage Figure 23. CS_DIS clamp voltage Vcsdh (V) Vcsdcl(V) 4 10 9 3,5 Icsd = 1 mA 8 3 7 2,5 6 2 5 4 1,5 3 1 2 0,5 1 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) -50 -25 0 25 50 75 100 125 150 175 Tc (C) Figure 24. CS_DIS low level voltage Vcsdl (V) 3 2,5 2 1,5 1 0,5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 12730 Rev 6 19/31 Application information 3 VNQ5027AK-E Application information Figure 25. Application schematic +5V VCC Rprot CS_DIS Dld C Rprot IINPUT OUTPUT Rprot CURRENT SENSE GND RSENSE Cext VGND RGND DGND Note: Channel 2, 3, 4 have the same internal circuit as channel 1. 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND 600mV / (IS(on)max). 2. RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 20/31 Doc ID 12730 Rev 6 VNQ5027AK-E 3.1.2 Application information Solution 2: a diode (DGND) in the ground line A resistor (RGND= 1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. 3.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k. Recommended values: Rprot = 10k, CEXT= 10nF. Doc ID 12730 Rev 6 21/31 Application information VNQ5027AK-E Figure 26. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TR TTSD TRS INPUT CS_DIS ILIMH ILIML LOAD CURRENT VSENSEH SENSE CURRENT thermal cycling current power limitation limitation SHORTED LOAD 22/31 Doc ID 12730 Rev 6 NORMAL LOAD VNQ5027AK-E 3.4 Application information Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn-off current versus inductance (for each channel) 100 A B 10 I (A) C 1 0,1 1 L (mH) 10 100 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 12730 Rev 6 23/31 Package and PC board thermal data VNQ5027AK-E 4 Package and PC board thermal data 4.1 PowerSSO-24TM thermal data Figure 28. PowerSSO-24TM PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) RTHj_amb( C/ W) 55 50 45 40 35 30 0 2 4 6 PCB Cu heat sink area ( cm^ 2) 24/31 Doc ID 12730 Rev 6 8 10 VNQ5027AK-E Package and PC board thermal data Figure 30. PowerSSO-24TM thermal impedance junction ambient single pulse (one channel on) ZTH (C/W) 1000 100 Footprint 2 cm2 8 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24TM (a) a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 12730 Rev 6 25/31 Package and PC board thermal data VNQ5027AK-E Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Table 15. Thermal parameters Area/island (cm2) 26/31 Footprint R1=R7=R9=R11 (C/W) 0.28 R2=R8=R10=R12 (C/W) 0.9 2 8 R3 (C/W) 6 R4 (C/W) 7.7 R5 (C/W) 9 9 8 R6 (C/W) 28 17 10 C1=C7=C9=C11 (W.s/C) 0.001 C2=C8=C10=C12 (W.s/C) 0.003 C3 (W.s/C) 0.025 C4 (W.s/C) 0.75 C5 (W.s/C) 1 4 9 C6 (W.s/C) 2.2 5 17 Doc ID 12730 Rev 6 VNQ5027AK-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-24TM mechanical data Figure 32. PowerSSO-24TM package dimensions Doc ID 12730 Rev 6 27/31 Package and packing information Table 16. VNQ5027AK-E PowerSSO-24TM mechanical data Millimeters Symbol Min Typ A 2.45 A2 2.15 2.35 a1 0 0.1 b 0.33 0.51 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.8 e3 8.8 F 2.3 G H 0.1 10.1 10.5 h 0.4 k 0 8 L 0.55 0.85 O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 N 28/31 Max 10 X 4.1 4.7 Y 6.5 7.1 Doc ID 12730 Rev 6 VNQ5027AK-E 5.3 Package and packing information Packing information Figure 33. PowerSSO-24TM tube shipment (no suffix) C Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 34. PowerSSO-24TM tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets saled with cover tape. User direction of feed Doc ID 12730 Rev 6 29/31 Revision history 6 VNQ5027AK-E Revision history Table 17. Document revision history Date Revision 17-Nov-2006 1 Initial release. 18-Dec-2007 2 Table 4: Absolute maximum ratings: EMAX max value changed from 82 to 140 mJ. Updated Table 8: Current Sense (8V<VCC<16V): - added dK0/K0 parameter - added K1 parameter - added dK1/K1 parameter - added dK2/K2 parameter - added dK3/K3 parameter - added tDSENSE2H parameter - added IOL parameter Added Figure 5: Delay response time between rising edge of output current and rising edge of Current Sense (CS enabled). Added Figure 7: IOUT/ISENSE vs IOUT Added Figure 8: Maximum current sense ratio drift vs load current. Added Section 2.4: Electrical characteristics curves. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). Figure 31: Thermal fitting model of a double channel HSD in PowerSSO-24TM: added note. Added ECOPACK(R) packages information. Update Section 5.2: PowerSSO-24TM mechanical data. 12-Feb-2008 3 Corrected typing error in Table 8: Current Sense (8V<VCC<16V): changed IOL test condition from VIN = 0V to VIN = 5V. 10-Apr-2008 4 Corrected Figure 27: Maximum turn-off current versus inductance (for each channel). 5 Table 16: PowerSSO-24TM mechanical data: - Deleted A (min) value - Changed A (max) value from 2.47 to 2.45 - Changed A2 (max) value from 2.40 to 2.35 - Changed a1 (max) value from 0.075 to 0.1 - Added F row - Updated k row 6 Updated Figure 32: PowerSSO-24TM package dimensions. Updated Table 16: PowerSSO-24TM mechanical data: - Deleted G1 row - Added O, Q, S, T and U rows 19-Jun-2009 22-Jul-2009 30/31 Changes Doc ID 12730 Rev 6 VNQ5027AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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