July 2009 Doc ID 12730 Rev 6 1/31
1
VNQ5027AK-E
Quad channel high side driver with analog current sense
for automotive applications
Features
■Output current: 42A
■3.0 V CMOS compatible input
■Current sense disable
■Proportional load current sense
■Undervoltage shut-down
■Overvoltage clamp
■Thermal shutdown
■Current and power limitation
■Very low standby current
■Protection against loss of ground and loss of
VCC
■Very low electromagnetic susceptibility
■Optimized electromagnetic emission
■Reverse battery protection (see Application
schematic on page 20)
■In compliance with the 2002/95/EC European
directive
■Package: ECOPACK®
Applications
■All types of resistive, inductive and capacitive
loads
■Suitable as LED driver
Description
The VNQ5027AK-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog Current Sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open. When CS_DIS
is driven high, the CURRENT SENSE pin is in a
high impedance condition. Output current
limitation protects the device in overload
condition. In case of long overload duration, the
device limits the dissipated power to safe level up
to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Max supply voltage VCC 41V
Operating voltage range VCC 4.5 to 36 V
Max on-state resistance (per ch.) RON 27 mΩ
Current limitation (typ) ILIMH 42 A
Off-state supply current IS2 µA(1)
1. Typical value with all loads connected.
PowerSSO-24
Table 1. Device summary
Package
Order codes
Tube Tape and reel
PowerSSO-24 VNQ5027AK-E VNQ5027AKTR-E
www.st.com
Contents VNQ5027AK-E
2/31 Doc ID 12730 Rev 6
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VNQ5027AK-E List of tables
Doc ID 12730 Rev 6 3/31
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Switching (VCC=13V; Tj= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Current Sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures VNQ5027AK-E
4/31 Doc ID 12730 Rev 6
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Delay response time between rising edge of output current and rising edge of Current Sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 24. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24
Figure 30. PowerSSO-24™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. PowerSSO-24™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VNQ5027AK-E Block diagram and pin configuration
Doc ID 12730 Rev 6 5/31
1 Block diagram and pin configuration
Figure 1. Block diagram
Table 2. Pin functions
Name Function
VCC Battery connection.
OUTPUTnPower output.
GND Ground connection. Must be reverse battery protected by an external
diode / resistor network.
INPUTn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CURRENT
SENSEn
Analog current sense pin, delivers a current proportional to the load current.
CS_DIS Active high CMOS compatible pin to disable the current sense pin.
LOGIC
UNDERVOLTAGE
OVERTEMP. 1
I
LIM
1
PwCLAMP 1
I
OUT1
GND
INPUT1
V
CC
OUTPUT1
CURRENT
SENSE1
DRIVER 1
V
CC
CLAMP
V
DSLIM
1OUTPUT2
CURRENT
SENSE2
CS_DIS
INPUT3
K 1
Pwr
LIM
1
INPUT2
INPUT4
Control & Protection
Equivalent to
channel1
INPUT2
CURRENT
V
CC
OUTPUT3
INPUT3
CURRENT
V
CC
OUTPUT4
INPUT4
CURRENT
V
CC
CURRENT
SENSE3
CURRENT
SENSE4
SENSE2
SENSE3
SENSE4
Control & Protection
Equivalent to
channel1
Control & Protection
Equivalent to
channel1
Block diagram and pin configuration VNQ5027AK-E
6/31 Doc ID 12730 Rev 6
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and not connected pins
Connection / pin Current Sense N.C. Output Input CS_DIS
Floating N.R.(1)
1. Not recommended.
XX X X
To ground Through 1 kΩ
resistor XN.R.
Through 10 kΩ
resistor
Through 10 kΩ
resistor
INPUT2
CURRENT SENSE2
GND
V
CC
INPUT1
CURRENT SENSE1
CS_DIS.
V
CC
CURRENT SENSE3
INPUT3
INPUT4
CURRENT SENSE4
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT4
OUTPUT4
OUTPUT3
OUTPUT3
OUTPUT3
OUTPUT4
TA B = V
CC
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 7/31
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
VFn
I
S
I
GND
V
CC
V
CC
OUTPUTn
INPUTn
V
INn
V
SENSEn
GND
CS_DIS
I
CSD
V
CSD
I
INn
CURRENT
S
ENSEn
V
OUTn
IOUTn
ISENSEn
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current 24 A
IIN DC Input current -1 to 10 mA
ICSD DC Current Sense disable Input current -1 to 10 mA
-ICSENSE DC Reverse CS pin current 200 mA
VCSENSE Current Sense maximum voltage VCC-41
+VCC
V
V
EMAX
Maximum switching energy (single pulse)
(L=0.8 mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.)) 140 mJ
Electrical specifications VNQ5027AK-E
8/31 Doc ID 12730 Rev 6
2.2 Thermal data
VESD
Electrostatic discharge
(human body model: R=1.5KΩ; C=100pF)
– Input
– Current sense
–CS_DIS
– Output
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
TjJunction operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Max value Unit
Rthj-case Thermal resistance junction-case (with one channel ON) 1.35 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 29. °C/W
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 9/31
2.3 Electrical characteristics
Values specified in this section are for 8 V<VCC<36 V, -40 °C< Tj <150 °C, unless otherwise
stated.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 4.5 13 36 V
VUSD Undervoltage shutdown 3.5 4.5 V
VUSDhyst
Undervoltage shut-down
hysteresis 0.5 V
RON On-state resistance
IOUT= 3A; Tj= 25°C
IOUT= 3A; Tj= 150°C
IOUT= 3A; VCC=5V; Tj= 25°C
27
54
37
mΩ
mΩ
mΩ
Vclamp Clamp voltage IS= 20 mA 41 46 52 V
ISSupply current
Off-state; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On-state; VCC=13V; VIN=5V;
IOUT=0A
2(1)
8
1. PowerMOS leakage included.
5(1)
14
µA
mA
IL(off) Off-state output current(2)
2. For each channel.
VIN=VOUT=0V; VCC=13V;
Tj=25°C
VIN=VOUT=0V; VCC=13V;
Tj=125°C
0
0
0.01 3
5
µA
VF
Output - VCC diode
voltage(2) -IOUT=3A; Tj=150°C 0.7 V
Table 7. Switching (VCC=13V; Tj= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL= 4.3Ω (see Figure 6.)40 µs
td(off) Turn-off delay time RL= 4.3Ω (see Figure 6.)40 µs
(dVOUT/dt)on Turn-on voltage slope RL= 4.3ΩSee
Figure 19. V/µs
(dVOUT/dt)off Turn-off voltage slope RL= 4.3ΩSee
Figure 21. V/µs
WON
Switching energy
losses during twon
RL= 4.3Ω (see Figure 6.)0.2 mJ
WOFF
Switching energy
losses during twoff
RL= 4.3Ω (see Figure 6.)0.3 mJ
Electrical specifications VNQ5027AK-E
10/31 Doc ID 12730 Rev 6
Table 8. Current Sense (8V<VCC<16V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K0IOUT/ISENSE
IOUT= 0.5A;
VSENSE= 0.5 V; VCSD=0 V;
Tj= -40°C...150°C
1680 2910 4120
dK0/K0(1) Current sense ratio drift
IOUT= 0.5A; VSENSE= 0.5V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-12 12 %
K1IOUT/ISENSE
IOUT= 2A;
VSENSE= 4 V; VCSD=0 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2050
2190
2700
2700
3410
3210
dK1/K1(1) Current sense ratio drift
IOUT= 2A; VSENSE= 4V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-10 10 %
K2IOUT/ISENSE
IOUT= 3A;
VSENSE= 4 V; VCSD=0 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2260
2350
2690
2690
3160
3030
dK2/K2(1) Current sense ratio drift
IOUT= 3A; VSENSE= 4V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-7 7 %
K3IOUT / ISENSE
IOUT= 10A;
VSENSE= 4 V; VCSD= 0 V;
Tj= -40°C...150°C
Tj= 25°C...150°C
2490
2590
2700
2700
2870
2800
dK3/K3(1) Current sense ratio drift
IOUT= 10A; VSENSE= 4 V;
VCSD= 0V;
TJ= -40 °C to 150 °C
-4 4 %
ISENSE0 Analog sense leakage current
IOUT= 0A; VSENSE= 0V;
VCSD= 5V; VIN= 0V;
Tj= -40°C...150°C
VCSD= 0V; VIN= 5V;
Tj= -40°C...150°C
IOUT= 2A; VSENSE= 0V;
VCSD= 5V; VIN= 5V;
Tj= -40°C...150°C
0
0
0
1
2
1
µA
µA
µA
IOL
open load on-state current
detection threshold VIN = 5V, ISENSE= 5 µA 5 30 mA
VSENSE
Max analog sense
output voltage IOUT= 3A; VCSD= 0V 5 V
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 11/31
VSENSEH
Analog sense output voltage in
over temperature condition VCC= 13V; RSENSE= 3.9KΩ9V
ISENSEH
Analog sense output current in
over temperature condition VCC= 13V; VSENSE= 5V 8 mA
tDSENSE1H
Delay response time from
falling edge of CS_DIS pin
VSENSE<4V, 0.5A<Iout<10A
ISENSE= 90% of ISENSE max
(see Figure 4.)
50 100 µs
tDSENSE1L
Delay response time from
rising edge of CS_DIS pin
VSENSE<4V, 0.5A<Iout<10A
ISENSE=10% of ISENSE max
(see Figure 4.)
520µs
tDSENSE2H
Delay response time from
rising edge of INPUT pin
VSENSE<4V, 0.5A<Iout<10A
ISENSE=90% of ISENSE max
(see Figure 4.)
70 300 µs
Δ
t
DSENSE2H
Delay response time between
rising edge of output current
and rising edge of current
sense
VSENSE <4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=2A (see Figure 5)
200 µs
tDSENSE2L
Delay response time from
falling edge of input pin
VSENSE<4V, 0.5A<Iout<10A
ISENSE=10% of ISENSE max
(see Figure 4.)
100 250 µs
1. Parameter guaranteed by design; it is not tested.
Table 8. Current Sense (8V<VCC<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 9. Protection(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
IlimH DC short circuit current VCC=13V
5V<VCC<36V
29 42 59
59
A
A
IlimL
Short circuit current
during thermal cycling VCC=13V; TR<Tj<TTSD 16 A
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature TRS + 1 TRS + 5 °C
TRS
Thermal reset of
STATUS 135 °C
THYST
Thermal hysteresis
(TTSD-TR)7°C
VDEMAG
Turn-off output voltage
clamp IOUT= 2A; VIN=0; L=6mH VCC-41 VCC-46 VCC-52 V
VON
Output voltage drop
limitation
IOUT=0.2A; Tj=-40°C...150°C
(see Figure 9.)25 mV
Electrical specifications VNQ5027AK-E
12/31 Doc ID 12730 Rev 6
Figure 4. Current sense delay characteristics
Table 10. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
IIL Low level input current VIN= 0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN= 2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
VICL Input clamp voltage IIN= 1mA
IIN= -1mA
5.5
-0.7
7V
V
VCSDL CS_DIS low level voltage 0.9 V
ICSDL Low level CS_DIS current VCSD=0.9V 1 µA
VCSDH CS_DIS high level voltage 2.1 V
ICSDH High level CS_DIS current VCSD=2.1V 10 µA
VCSD(hyst) CS_DIS hysteresis voltage 0.25 V
VCSCL CS_DIS clamp voltage ICSD= 1mA
ICSD= -1mA
5.5
-0.7
7V
V
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
tDSENSE2H tDSENSE2L
tDSENSE1L tDSENSE1H
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 13/31
Figure 5. Delay response time between rising edge of output current and rising
edge of Current Sense (CS enabled)
Figure 6. Switching characteristics
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
Electrical specifications VNQ5027AK-E
14/31 Doc ID 12730 Rev 6
Figure 7. IOUT/ISENSE vs IOUT
Figure 8. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
1000
1500
2000
2500
3000
3500
4000
4500
246810
IOUT (A)
Iout / Isense
max Tj = -40 °C to 150 °C
max Tj = 25 °C to 150 °C
min Tj = 25 °C to 150 °C
min Tj = -40 °C to 150 °C
typical value
-15
-10
-5
0
5
10
15
2345678910
IOUT (A)
dk/k(%)
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 15/31
Figure 9. Output voltage drop limitation
Table 11. Truth table
Conditions Input Output Sense (VCSD=0V)(1)
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Overtemperature L
H
L
L
0
VSENSEH
Undervoltage L
H
L
L
0
0
Short circuit to GND
(Rsc ≤ 10 mΩ)
L
H
H
L
L
L
0
0 if Tj < TTSD
VSENSEH if Tj > TTSD
Short circuit to VCC
L
H
H
H
0
< Nominal
Negative output voltage
clamp LL 0
Table 12. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test pulse
Test levels Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
III IV
1 -75 V -100 V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
Von
Iout
Vcc-Vout
Tj=150
o
CTj=25
o
C
Tj=-40
o
C
Von/Ron(T)
Electrical specifications VNQ5027AK-E
16/31 Doc ID 12730 Rev 6
4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω
5b(2) +65 V +87 V 1 pulse 400 ms, 2 Ω
Table 13. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E)
test pulse
Test level results(1)
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b (2) CC
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 14. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
device.
Table 12. Electrical transient requirements (part 1/3) (continued)
ISO 7637-2:
2004(E)
test pulse
Test levels Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
III IV
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 17/31
2.4 Electrical characteristics curves
Figure 10. Off-state output current Figure 11. High level input current
Figure 12. Input clamp voltage Figure 13. Input low level
Figure 14. Input high level Figure 15. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
Iloff (nA)
Off State
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
Iih (µA)
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5,5
6
6,5
7
7,5
8
Vicl (V)
lin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
Vihyst (V)
Electrical specifications VNQ5027AK-E
18/31 Doc ID 12730 Rev 6
Figure 16. On-state resistance vs Tcase Figure 17. On-state resistance vs VCC
Figure 18. Undervoltage shutdown Figure 19. Turn-on voltage slope
Figure 20. ILIMH vs Tcase Figure 21. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
20
40
60
80
100
Ron (mOhm)
Iout= 3A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
10
20
30
40
50
60
Ron (mOhm)
Tc=-40°C
Tc=25°C
Tc=125°C
Tc=150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt )On (V/ms)
Vcc=13V
RI=4.3 Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
20
25
30
35
40
45
50
55
60
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
600
(dVout/dt )Off (V/ms)
Vcc=13V
RI= 4.3 Ohm
VNQ5027AK-E Electrical specifications
Doc ID 12730 Rev 6 19/31
Figure 22. CS_DIS high level voltage Figure 23. CS_DIS clamp voltage
Figure 24. CS_DIS low level voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
3,5
4
Vcsdh (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Vcsdcl(V)
Icsd = 1 mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0,5
1
1,5
2
2,5
3
Vcsdl (V)
Application information VNQ5027AK-E
20/31 Doc ID 12730 Rev 6
3 Application information
Figure 25. Application schematic
Note: Channel 2, 3, 4 have the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max).
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
μ
C
+5V
V
GND
CS_DIS
IINPUT
R
prot
R
prot
CURRENT SENSE
R
prot
R
SENSE
Cext
VNQ5027AK-E Application information
Doc ID 12730 Rev 6 21/31
3.1.2 Solution 2: a diode (DGND) in the ground line
A resistor (RGND= 1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO T/R 7637/1 table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot = 10kΩ, CEXT= 10nF.
Application information VNQ5027AK-E
22/31 Doc ID 12730 Rev 6
Figure 26. Waveforms
SENSE CURRENT
INPUT
NORMAL OPERATION
UNDERVOLTAGE
VCC VUSD
VUSDhyst
INPUT
SENSE CURRENT
LOAD CURRENT
LOAD CURRENT
OVERLOAD OPERATION
INPUT
SENSE CURRENT
TTSD
TR
Tj
LOAD CURRENT
INPUT
LOAD VOLTAGE
SENSE CURRENT
LOAD CURRENT
<Nominal <Nominal
SHORT TO VCC
CS_DIS
CS_DIS
CS_DIS
CS_DIS
TRS
ILIMH
ILIML
VSENSEH
thermal cycling
power
limitation
current
limitation
SHORTED LOAD NORMAL LOAD
VNQ5027AK-E Application information
Doc ID 12730 Rev 6 23/31
3.4 Maximum demagnetization energy (VCC =13.5V)
Figure 27. Maximum turn-off current versus inductance (for each channel)
Note: Values are generated with RL=0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
1
10
100
0,1 1 10 100L (mH)
I (A)
Demagnetization Demagnetization Demagnetization
t
VIN, IL
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
A
B
C
Package and PC board thermal data VNQ5027AK-E
24/31 Doc ID 12730 Rev 6
4 Package and PC board thermal data
4.1 PowerSSO-24™ thermal data
Figure 28. PowerSSO-24™ PC board
Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 29.
R
thj-amb
vs PCB copper area in open box free air condition (one channel ON)
30
35
40
45
50
55
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^ 2)
VNQ5027AK-E Package and PC board thermal data
Doc ID 12730 Rev 6 25/31
Figure 30.
PowerSSO-24
™
thermal impedance junction ambient single pulse (one channel
on)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™ (a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
0.1
1
10
100
1000
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
ZTH (°C/W)
Footprint
8 cm2
2 cm2
Package and PC board thermal data VNQ5027AK-E
26/31 Doc ID 12730 Rev 6
Equation 1: pulse calculation formula
Table 15. Thermal parameters
Area/island (cm2)Footprint28
R1=R7=R9=R11 (°C/W) 0.28
R2=R8=R10=R12 (°C/W) 0.9
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7=C9=C11 (W.s/°C) 0.001
C2=C8=C10=C12 (W.s/°C) 0.003
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
VNQ5027AK-E Package and packing information
Doc ID 12730 Rev 6 27/31
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2 PowerSSO-24™ mechanical data
Figure 32. PowerSSO-24™ package dimensions
Package and packing information VNQ5027AK-E
28/31 Doc ID 12730 Rev 6
Table 16. PowerSSO-24™ mechanical data
Symbol
Millimeters
Min Typ Max
A2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G0.1
H 10.1 10.5
h0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N10°
X4.1 4.7
Y6.5 7.1
VNQ5027AK-E Package and packing information
Doc ID 12730 Rev 6 29/31
5.3 Packing information
Figure 33. PowerSSO-24™ tube shipment (no suffix)
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”)
A
CB
All dimensions are in mm.
Base Q.ty 49
Bulk Q.ty 1225
Tube length (± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Revision history VNQ5027AK-E
30/31 Doc ID 12730 Rev 6
6 Revision history
Table 17. Document revision history
Date Revision Changes
17-Nov-2006 1 Initial release.
18-Dec-2007 2
Table 4: Absolute maximum ratings: EMAX max value changed from
82 to 140 mJ.
Updated Table 8: Current Sense (8V<VCC<16V):
– added dK0/K0 parameter
– added K1 parameter
– added dK1/K1 parameter
– added dK2/K2 parameter
– added dK3/K3 parameter
– added
Δ
t
DSENSE2H
parameter
– added IOL parameter
Added Figure 5: Delay response time between rising edge of output
current and rising edge of Current Sense (CS enabled).
Added Figure 7: IOUT/ISENSE vs IOUT
Added Figure 8: Maximum current sense ratio drift vs load current.
Added Section 2.4: Electrical characteristics curves.
Added Section 3.4: Maximum demagnetization energy
(VCC = 13.5V).
Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-24™: added note.
Added ECOPACK® packages information.
Update Section 5.2: PowerSSO-24™ mechanical data.
12-Feb-2008 3 Corrected typing error in Table 8: Current Sense (8V<VCC<16V):
changed IOL test condition from VIN = 0V to VIN = 5V.
10-Apr-2008 4 Corrected Figure 27: Maximum turn-off current versus inductance
(for each channel).
19-Jun-2009 5
Table 16: PowerSSO-24™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F row
– Updated k row
22-Jul-2009 6
Updated Figure 32: PowerSSO-24™ package dimensions.
Updated Table 16: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T and U rows
VNQ5027AK-E
Doc ID 12730 Rev 6 31/31
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
