FEATURES High Power Density Power Module 10A Maximum Load Input Voltage Range from 1.0V to 15.0V PVCC Voltage Range from 4.5V to 14.4V Output Voltage Range from 0.6V to 5.5V Excellent Thermal Performance 96% Peak Efficiency Enable Function Protections (OCP, Non-latching) Internal Soft Start with Pre-bias Output Start-Up QFN- Package 15mm*15mm*3.5mm Low Profile and Compact Size Pb-free Available (RoHS compliant) MSL 3, 245C Reflow The MCM15S0A0Q10FA is a high frequency, high power density and complete DC/DC power module. The PWM controller, power MOSFETs and most of support components are integrated in one hybrid package. The features of MCM15S0A0Q10FA include voltage mode control with high phase margin compensation, internal soft-start, OCP and pre-biased output start-up capability. Besides, MCM15S0A0Q10FA is an easy to use POL module, only input capacitors and output capacitors need to design for all kinds of applications. The low profile package enables utilization of unused space on the bottom of PC boards for highly density point of load regulation. The MCM15S0A0Q10FA is packaged in a thermally enhanced, compact (15mmx15mm x 3.5mm) and low profile QFN package suitable for automated assembly by standard surface mount equipments. The MCM15S0A0Q10FA is Pb-free and RoHS compliance. OPTIONS Positive on/off logic SMD pin APPLICATIONS General Buck DC/DC Conversion Distributed Power Supply Datacom, and Telecom Power Supplies Server/Desktop Power Supplies TYPICAL APPLICATION CIRCUIT & PACKAGE SIZE: RISEN Setting OCP VIN (+5V / +12V) PVCC ISEN RFB Setting Output Voltage FB VIN RISEN Setting OCP VOUT (0.6V~5.5V) VOSEN PVCC ISEN FB VOSEN VIN VOUT MCM15S0A0Q10FA Power Module C IN VIN (+5V / +12V) C OUT RFB Setting Output Voltage MCM15S0A0Q10FA Power Module CIN VOUT (0.6V~5.5V) VOUT COUT PGND PGND TABLE 1: OUPUT VOLTAGE SETTING Vout 1.05V 1.2V 1.5V 1.8V 2.5V 3.3V 5V RFB (Ohm) 13k 9.76k 6.49k 4.87k 3.09k 2.16k 1.33k ORDER INFORMATION: Part Number Ambient Temp. Range Package (C) (Pb-Free) -40 ~ +85 QFN 15Ld. MCM15S0A0Q10FA MSL Note Level 3 - Order Code Packing Quantity MCM15S0A0Q10FA Tray 96 MCM15S0A0Q10FA -T Tape and reel 500 DS_MCM15S0A0Q10FA_05052011 2 SIMPLIFIED INTERNAL BLOCK DIAGRAM: PGND 2 PGND 3 PGND 4 PGND PVCC BOOT 1 5 6 Sample and Hold POR and Soft-Start - 21.5uA 8 FB + 0.4V + PWM - Gate Control Logic VOSEN 11 PGND PVCC ISEN Oscillator 14 13 Vout DIS - COMP/EN 12 Inhibit + + 15 Vin LDO ISEN 0.6V 9 RSEN-IN RFB-TI 7 10 ISEN PHASE FIG.1 INTERNAL BLOCK DIAGRAM (2) PGND (3) PGND (4) PGND (5) PVCC (6) BOOT (7) ISEN (8) PGND PIN CONFIGURATION: (1) PGND (15) FB VIN (9) (14) COMP/EN TPD 9 (13) VOSEN PHASE (10) TPD 12 TPD 10 (12) VOUT TPD 11 PGND (11) Top View DS_MCM15S0A0Q10FA_05052011 3 PIN DESCRIPTION: Symbol PGND Pin No. 1, 2, 3, 4, 8 PVCC 5 BOOT 6 ISEN 7 VIN (TPD 9) PHASE (TPD 10) PGND (TPD 11) VOUT (TPD 12) 9 10 11 12 VOSEN 13 COMP/EN 14 FB 15 DS_MCM15S0A0Q10FA_05052011 Description Power ground pin for signal, input, and output return path. This pin needs to connect one or more ground plane directly. Supply voltage pin for internal bias supply and MOSFETs gate drivers. It needs to connect 2.2uF ceramic capacitor to ground plane directly and place this capacitor as closely as possible to this pin. Node of internal bootstrap capacitor and diode. Caution of the operation voltage can not exceed the absolute maximum rating. The ISEN pin is over current protection setting. It compares the RDS(ON) of low-side MOSFET to configure the over current protection trip current. The MCM15S0A0Q10FA. has initial current setting to limit the surge current impact. It has an integrated internal 4.99k resistor (RSEN-IN) between ISEN and PGND pin. One can also connect external resistor (RSEN-EX) between this pin and PGND pin to reduce the over current trip point. The recommendation of this external resistor (RSEN-EX) is 20k for general application limit .Place this resistor as closely as possible to this pin. Power input pin. It needs to connect input rail and using for heat transferring to heat dissipation layer by Vias connection. Place the input ceramic type capacitor as closely as possible to this pin. Phase node pin. Node of high-side and low-side MOSFETs and output inductor connection. Using for heat transferring to heat dissipation layer by Vias connection. For electrically, if voltage spike stress and EMI considered, the snubber circuit can be as closely as possible connected to this pin that will absorb the spike and ringing well. Power ground pin and used for both PGND pin (1, 2, 3, and 4). It needs to connect one or more ground plane directly and using for heat transferring to heat dissipation layer by Vias connection. Place the input ceramic type and output capacitors as closely as possible to this pin. If voltage spike stress and EMI considered, the snubber circuit can be as closely as possible connected to this pin that will absorb the spike and ringing. Power output pin. Connect to output and using for heat transferring to heat dissipation layer by Vias connection. Place the output capacitors as closely as possible to this pin. Output voltage sensing pin. Connect to output loading point. It can eliminate the positive voltage droop on the trace and keep the regulation at loading point. CAUTION: Do not leave this pin open. This is multi-function pin for MCM15S0A0Q10FA. Compensation and enable. Feedback input. Connect resistor between this pin and ground for adjusting output voltage. Place this resistor as closely as possible to this pin. 4 ELECTRICAL SPECIFICATIONS: CAUTION: Don not operate at or near absolute maximum rating listed for extended periods of time. This stress may adversely impact product reliability and result in failures not covered by warranty. Parameter Min. Typ. Max. Unit PVCC to PGND PGND-0.3 - +15 V ISEN to PGND PGND-0.3 - PVCC+0.3 V BOOT to PGND PGND-0.3 - +36 V BOOT to PVCC - - +24 V Absolute Maximum Ratings VIN to PHASE Note 1 -1.2 - +30 V PHASE to PGND Note 1 -1.2 - +30 V VOSEN to PGND PGND-0.3 - +6 V COMP/EN to PGND PGND-0.3 - +6 V FB to PGND PGND-0.3 - +6 V Tc - - +110 C Tj -40 - +125 C Tstg -40 - +125 C Human Body Model (HBM) - - 2k V Machine Model (MM) - - 100 V Charge Device Model (CDM) - - 1k V +1 - +15 V Output Voltage +0.6 - +5.5 V Fixed Supply Voltage for 5V +4.5 +5 +5.5 V Fixed Supply Voltage for 12V +9.6 +12 +14.4 V Wide Range Supply Voltage +6.5 - +14.4 V -40 - +85 C - 12.92 - C/W ESD Rating Recommendation Operating Ratings VIN VOUT PVCC Ta Description Input Supply Voltage Ambient Temperature Thermal Information Rth(j-a) Thermal resistance from junction to ambient. (Note 2) NOTES: 1. VDS (Drain to Source) specification for internal high-side and low-side MOSFETs. 2. Rth(j-a) is measured with the component mounted on an effective thermal conductivity test board on 0 LFM condition. The test board size is 80mmx80mmx1.6mm with 4 layers, 1oz. The test condition is complied with JEDECE EIJ/JESD 51 Standards. DS_MCM15S0A0Q10FA_05052011 5 ELECTRICAL SPECIFICATIONS: (Cont.) Conditions: TA = 25 C, unless otherwise specified. Vin=12V, Vout=1.5V, Cin=220uFx1, 10uF/Ceramicx2, Cout=330uF/POS-CAPx1, 22uF/Ceramicx3 Symbol Parameter Conditions Min. Typ. Max. Unit - 10 - mA Vin = 12V, Vout = 1.5V PVCC = 12V - 1.43 - A Vin=12V, Vout=1.5V 0 - 10 A - 0.1 - % - 0.5 - % - 30 - mVp-p - 75 - mVp-p - 75 - mVp-p - mA Input Characteristics IQ(VIN) Input supply bias current IS(VIN) Input supply current Iout = 0A Vin = 12V, Vout = 1.5V PVCC = 12V Iout = 10A Output Characteristics IOUT(DC) Output continuous current range VOUT/VIN VOUT/IOUT VOUT(AC) Line regulation accuracy Load regulation accuracy Output ripple voltage Vout = 1.5V, Iout = 10A PVCC = 12V Iout = 0A to 10A Vin = 12V, Vout = 1.5V PVCC = 12V Iout = 10A Vin = 12V, Vout = 1.5V PVCC = 12V Dynamic Characteristics VOUT-DP Voltage change for positive load step VOUT-DN Voltage change for negative load step Vin = 3.3V to 15V Vout = 1.5V, Iout = 0A Iout = 0A to 5A Current slew rate = 2.5A/uS Vin = 12V, Vout = 1.5V PVCC = 12V Iout = 5A to 0A Current slew rate = 2.5A/uS Vin = 12V, Vout = 1.5V PVCC = 12V Control Characteristics IPVCC PVCC operating current VPORR Rising PVCC threshold Iout = 10A Vin = 12V, Vout = 1.5V 5V supply - 12V supply VPORH PVCC Power-On-Reset threshold 20 40 Note 3 3.9 4.1 4.3 V Note 3 0.30 0.35 0.40 mV hysteresis DS_MCM15S0A0Q10FA_05052011 6 ELECTRICAL SPECIFICATIONS: (Cont.) Conditions: TA = 25 C, unless otherwise specified. Vin=12V, Vout=1.5V, Cin=220uFx1, 10uF/Ceramicx2, Cout=330uF/POS-CAPx1, 22uF/Ceramicx3 Symbol Conditions Min. Typ. Max. Unit Note 3 0.591 0.6 0.609 V Note 3 510 600 660 kHz 9.66 9.76 9.85 k 0.375 0.4 0.425 V 4.94 4.99 5.04 k 18.0 21.5 23.5 uA Control Characteristics VREF FOSC RFB-TI VENDIS Parameter Referance voltage Oscillator frequency Internal resistor between VOUT and FB pins Disable threshold voltage (COMP/EN) Note 3 Fault Protection RSEN-IN ISEN Internal resistor between ISEN and PGND pins ISEN current source Note 3 NOTES: 3. Parameters guaranteed by PWM IC vendor design and test prior to module assembly. DS_MCM15S0A0Q10FA_05052011 7 TYPICAL PERFORMANCE CHARACTERISTICS: (Efficiency) Conditions: TA = 25 C, unless otherwise specified. Cin=10uF/Ceramicx5, Cout=330uF/POS-CAP(ESR=10m)x1, 22uF/Ceramicx3, Test Board Information: 80mmx80mmx1.6mm, 4 layers, 1oz. NOTES: POUT VOUT x IOUT = 4. The efficiency measurement is P + P (V x I ) + (V x I ) PVCC OUT OUT PVCC PVCC 100% 95% 95% 90% 90% 85% 85% EFFICIENCY (%) EFFICIENCY (%) IN 100% 80% 75% 70% 5.0Vout 3.3Vout 2.5Vout 1.8Vout 1.5Vout 1.2Vout 65% 60% 55% 80% 75% 70% 5.0Vout 3.3Vout 2.5Vout 1.8Vout 1.5Vout 1.2Vout 65% 60% 55% 50% 50% 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 LOAD CURRENT (A) 5 6 7 8 9 100% 100% 95% 95% 90% 90% 85% 85% EFFICIENCY (%) FIG.3 EFFICIENCY V.S. LOAD CURRENT (12VIN,5PVCC) EFFICIENCY (%) FIG.2 EFFICIENCY V.S. LOAD CURRENT (12VIN,12PVCC) 80% 75% 70% 65% 3.3Vout 2.5Vout 1.8Vout 1.5Vout 1.2Vout 60% 55% 1 2 3 4 5 6 7 8 80% 75% 70% 3.3Vout 2.5Vout 1.8Vout 1.5Vout 1.2Vout 65% 60% 55% 50% 50% 0 9 0 10 1 2 3 LOAD CURRENT (A) 95% 90% 90% 85% 85% EFFICIENCY (%) EFFICIENCY (%) 100% 95% 80% 75% 70% 1.8Vout 55% 1 2 3 4 5 6 9 FIG.6 EFFICIENCY V.S. LOAD CURRENT (3.3VIN,12PVCC) DS_MCM15S0A0Q10FA_05052011 9 10 65% 55% 8 8 70% 1.2Vout 7 7 75% 60% LOAD CURRENT (A) 6 80% 1.5Vout 50% 0 5 FIG.5 EFFICIENCY V.S. LOAD CURRENT (5VIN,5PVCC) 100% 60% 4 LOAD CURRENT (A) FIG.4 EFFICIENCY V.S. LOAD CURRENT (5VIN,12PVCC) 65% 10 LOAD CURRENT (A) 10 1.8Vout 1.5Vout 1.2Vout 50% 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A) FIG.7 EFFICIENCY V.S. LOAD CURRENT (3.3VIN,5PVCC) 8 TYPICAL PERFORMANCE CHARACTERISTICS: (Output Ripple) Conditions: TA = 25 C, unless otherwise specified. Vin=12V, PVCC=12V, Cin=10uF/Ceramicx5, Cout=330uF/POS-CAP(ESR=10m)x1, 22uF/Ceramicx3 NOTES: 5. The output ripple measurement is short loop probing and 20MegHz bandwidth limited. VOUT FIG.8 1.5VOUT OUTPUT RIPPLE, at 0A LOAD CURRENT VOUT FIG.10 2.5VOUT OUTPUT RIPPLE, at 0A CURRENT LOAD VOUT FIG.12 3.3VOUT OUTPUT RIPPLE, at 0A LOAD CURRENT DS_MCM15S0A0Q10FA_05052011 VOUT FIG.9 1.5VOUT OUTPUT RIPPLE, at 10A LOAD CURRENT VOUT FIG.11 2.5VOUT OUTPUT RIPPLE, at 10A LOAD CURRENT VOUT FIG.13 3.3VOUT OUTPUT RIPPLE, at 10A LOAD CURRENT 9 TYPICAL PERFORMANCE CHARACTERISTICS: (Transient Response) Conditions: TA = 25 C, unless otherwise specified. Vin=12V, PVCC=12V, Cin=10uF/Ceramicx5, Cout=330uF/POS-CAP(ESR=10m)x1, 22uF/Ceramicx3, Current Slew Rate=2.5A/uS VIN=12V VOUT=1.5V IOUT=0A to 5A VIN=12V VOUT=1.2V IOUT=0A to 5A VOUT VOUT IOUT IOUT FIG.14 1.2VOUT TRANSIENT RESPONSE, at 0A to 5A LOAD CURRENT FIG.15 1.5VOUT TRANSIENT RESPONSE, at 0A to 5A LOAD CURRENT VIN=12V VOUT=2.5V IOUT=0A to 5A VIN=12V VOUT=1.8V IOUT=0A to 5A VOUT VOUT IOUT IOUT FIG.16 1.8VOUT TRANSIENT RESPONSE, at 0A to 5A LOAD CURRENT FIG.17 2.5VOUT TRANSIENT RESPONSE, at 0A to 5A LOAD CURRENT VIN=12V VOUT=3.3V IOUT=0A to 5A VOUT IOUT FIG.18 3.3VOUT TRANSIENT RESPONSE, at 0A to 5A LOAD CURRENT DS_MCM15S0A0Q10FA_05052011 10 APPLICATIONS INFORMATION: REFERENCE CIRCUIT FOR GERNERAL APPLICATION: The Figure 19 shows the MCM15S0A0Q10FA. application schematics for input voltage +5V or +12V. The PVCC pin can connect to input supply directly. R(PVCC)/4.7 1 PGND 2 PGND PGND 4 PGND PVC C B OOT 5 6 8 7 ISEN PGND 3 C(PVCC)/2.2uF R(SEN-EX)/20k +12Vin / +5Vin FB R(FB) 15 1.5Vout setting VIN See Table 1 for Vout setting 9 HM1010 7B MCM15S0A0Q10FA VIN C OMP /EN VOS EN 14 Enable / Disable 13 PHASE VOUT 11 C(IN) PGND VOUT 10 C(IN)- ceramic 12 C(OUT) PGND PGND FIG.19 TYPOCAL APPLICATION WITH SINGLE POWER SUPPLY The Figure 20 shows the MCM15S0A0Q10FA application schematics for wide input voltage from +1V to +15V. The PVCC supply can source +5V / +12V or +6.5V to +14.4V. Please refer to input voltage consideration in application information. PVCC +5V / +12V +6.5V ~14.4V R(PVCC)/4.7 +1.0Vin ~ +15Vin 1 PGND 2 PGND 3 PGND 5 PGND B OOT PVC C 7 6 ISEN 8 PGND 4 C(PVCC)2.2uF R(SEN-EX)/20k FB 15 R(FB)/6.49k 1.5Vout setting See Table 1 for Vout settin VIN 9 VIN HM1010 7B C OMP /EN 14 MCM15S0A0Q10FA VOS EN Enable / Disable 13 PGND C(IN)- ceramic 11 C(IN) PHASE PGND VOUT 10 VOUT 12 C(OUT) PGND FIG.20 TYPICAL APPLICATION WITH SEPARATED POWER SUPPLY DS_MCM15S0A0Q10FA_05052011 11 APPLICATIONS INFORMATION: (Cont.) PROGRAMMING OUTPUT VOLTAGE: The MCM15S0A0Q10FA has an internal 0.6V1.5% reference voltage. It only programs the dividing resistance RFB which respects to FB pin and PGND. The output voltage can be calculated as shown in Equation 1 and the resistance according to typical output voltage is shown in TABLE 1. 9.76k VOUT = 0.6 x 1 + R FB (EQ.1) ON/OFF CONTROL: Figure 21 shows a remote ON/OFF control of MCM15S0A0Q10FA by using COMP/EN pin. Pulling COMP/EN low than threshold voltage (VENDIS=0.4 typ.) will be disabled the MCM15S0A0Q10FA. The external pull-down device (open drain or open collector devices) will initially need to overcome maximum of 5mA of COMP/EN output current. However, once the MCM15S0A0Q10FA is disabled and still PVCC voltage bias applied, the 20uA current source will continue to draw current from COMP/EN. The turn-on waveforms with remote ON/OFF control are shown in Figure 22 and 23 for 1.5Vout applications. While the ON/OFF control was not used, leave COMP/EN pin open, the MCM15S0A0Q10FA will be following PVCC threshold voltage (VPORR=4.1V typ.) to turn-on. FIG.21 REMOTE ON/OFF CONFIGURATION DS_MCM15S0A0Q10FA_05052011 12 APPLICATIONS INFORMATION: (Cont.) Low Active Low Active ON/OFF ON/OFF VOUT VOUT FIG.22 TURN-ON DELAY TIME at 12VIN, 12PVCC, 1.5VOUT, 10A LOAD CURRENT FIG.23 TURN-ON DELAY TIME at 5VIN, 5PVCC, 1.5VOUT, 10A LOAD CURRENT SOFT-START AND PRE-BIASED OUTPUTS: The soft-start internally ramps the reference on the non-inverting terminal of the error amp from 0V to 0.6V in a nominal 6.8mS. The output voltage will follow this ramp, from zero to final regulation value for set point. This mechanism provides output voltage soft rise and no inrush current charges the output capacitors. The entire start-up sequence from Power-on-rest typically takes up to 17mS; up to 10.2mS for delay and OCP sample and 6.8mS for the soft-start ramp. If the output is pre-biased to a voltage less than the expected value, as shown Figure 24, the MCM15S0A0Q10FA will detect that condition. Neither internal MOSFET will turn on until the soft-start ramp voltage exceeds the output; VOUT starts seamlessly ramping from there. If the output is pre-biased to a voltage above the expected value shows as Figure 25. Neither MOSFET will turn on until the end of the soft-start, at which time it will pull the output voltage down to the final value. 0.6V Pre-biased start-up 2.0V Pre-biased start-up VOUT VOUT FIG.24 0.6V PRE-BIASED at 12VIN, 12PVCC, 1.5VOUT DS_MCM15S0A0Q10FA_05052011 FIG.25 2.0V PRE-BIASES at 12VIN, 12PVCC, 1.5VOUT 13 APPLICATIONS INFORMATION: (Cont.) OVER CURRENT PROTECTION: The over-current function protects the converter from a shorted output by using the low side MOSFET on-resistance, RDS(ON), to monitor the current. A resistor (RSEN) programs the over-current trip level. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. If over-current is detected, the output immediately shuts off, it cycles the soft-start function in a hiccup mode (2 dummy soft-start time-outs, then up to one real one) to provide fault protection. If the shorted condition is not removed, this cycle will continue indefinitely. The over-current function will trip at a peak inductor current (IPEAK) determined by Equation 2. IPEAK = Where: 2 x I SEN x R SEN R DS(ON) (EQ.2) RDS(ON) is typically 8m including internal parasitic resistance. (at PVCC=VGS=10V, IDS=30A) RDS(ON) is typically 10m including internal parasitic resistance. (at PVCC=VGS=5.0V, IDS=30A) ISEN is the internal current source (21.5uA typ.). RSEN is equivalent resistance between ISEN and PGND pins. The MCM15S0A0Q10FA has integrated 4.99k resistance (RSEN-IN). Therefore, the equivalent resistance of RSEN can be expressed in Equation 3. R SEN = R SEN-EX x R SEN-IN R SEN-EX + R SEN-IN (EQ.3) The relationships between the external RSEN-EX values and typical over current protection trip level of MCM15S0A0Q10FA are shown as TABLE 2. TABLE 2 RECOMMENDATION OCP TRIP FOR RSEN-EX VALUES RSEN-EX OPEN OCP Trip Level (Typ.) (Note 6) OCP Trip Level (Typ.) (Note 6) VIN=12V, PVCC=12V, VOUT=1.5V VIN=12V, PVCC=5V, VOUT=1.5V CAUTION: Do not leave ISEN pin open 20A 20k 20A 16A 13k 18A 14A 9.3k 16A 12A 6.8k 14A 10A NOTES: 6. The trip values are tested at TA = 25 C, Cin=10uF/Ceramicx5, Cout=330uF/POS-CAP (ESR=10m) x1, 22uF/Ceramicx3. Test Board Information: 80mmx80mmx1.6mm, 4 layers, 1oz. DS_MCM15S0A0Q10FA_05052011 14 APPLICATIONS INFORMATION: (Cont.) INPUT AND OUTPUT CAPACITORS: Place the decoupled ceramic capacitors to control the high frequency voltage overshoot and bulk capacitor to supply the current needed each time module turns-on. The important parameters for bulk capacitor are voltage rating and the RMS current rating. For reliable operation, the bulk capacitor selects the voltage and current rating above maximum input voltage and highest RMS current required. The bulk output capacitors COUT is chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 330uF and decupled ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. PVCC BIAS AND POWER-UP SEQUENCE CONSIDERATIONS: The PVCC bias is either 5V (10%) or 12V (20%) and anywhere from 6.5V up to the 14.4V maximum. However, the range between 5.5V and 6.5V is not allowed for long-term reliability reasons, but transitions through it to voltages above 6.5V are acceptable. If the transition is slow (not a step change), the disturbance should be minimal. So while the recommendation doesn't have the output enabled during the transition through this region, it may be acceptable. The user should monitor the output for their application to see if there is any problem. If PVCC powers up first and the VIN is not present by the time the initialization is done, then the soft-start will not be able to ramp the output, and the output will later follow part of the VIN ramp when it is applied. If this is not desired, then change the sequencing of the supplies, or use the COMP/EN pin to disable VOUT until both supplies are ready. Figure 26 shows a simple sequencer for this situation. FIG.26 SEQUENCE CONFIGURATION (IF PVCC BIAS POWER-UP FIRST) DS_MCM15S0A0Q10FA_05052011 15 APPLICATIONS INFORMATION: (Cont.) RECOMMENDATION LAYOUT GUIDE: In order to achieve stable, low losses, less noise or spike, and good thermal performance some layout considerations are necessary. The recommendation layout is shown as Figure 27 and 28. 1. The ground connection between pin 11 and pin 1 to 4 and 8 should be a solid ground plane under the module. It can be connected one or more ground plane by using several Vias. 2. Place high frequency ceramic capacitors between pin 9 (VIN) and pin 11 (PGND), pin 5 (PVCC) and pin 1 to 4 (PGND) as close to module as possible to minimize high frequency noise. 3. Keep the RSEN-EX and RFB connection trace to the module pin 7 (ISEN) and pin 15 (FB) short. 4. The VOSEN pin can have remote trace layout to the local point sensing for output. It can eliminate the positive voltage droop on the trace to keep local regulation well. CAUTION: Do not leave VOSEN pin open. 5. Use large copper area for power path (VIN, VOUT, and PGND) to minimize the conduction loss and enhance heat transferring. Also, use multiple Vias to connect power planes in different layer. 6. Avoid layout any sensitive signal traces near the pin 10 (PHASE). FIG.27 RECOMMENDATION LAYOUT (Top) DS_MCM15S0A0Q10FA_05052011 16 APPLICATIONS INFORMATION: (Cont.) Cin Cout FIG.28 RECOMMENDATION LAYOUT (Bottom) THERMAL CONSIDERATIONS: All of thermal testing condition is complied with JEDECE EIJ/JESD 51 Standards. Therefore, the test board size is 80mmx80mmx1.6mm with 4 layers, 1oz. The case temperature of module sensing point is shown as Figure 29. Then Rth(j-a) is measured with the component mounted on a effective thermal conductivity test board on 0 LFM condition. The output current ability is function of input/ output voltage and ambient temperature factor etc. The MCM15S0A0Q10FA module is designed for using when the case temperature is below 110C. In Figure 30 and 31, the power loss curves can be used in coordination with each load current. The load current in different input voltage are shown in Figure 32 to 35. It would be convenient for user to confirm and estimate modular's approximate performance according to actual operating conditions in beginning of design. FIG.29 CASE TEMPERATURE SENSING POINT DS_MCM15S0A0Q10FA_05052011 17 4 4 3 3 POWER LOSS (W) POWER LOSS (W) APPLICATIONS INFORMATION: (Cont.) 2 1 2 1 12Vin 5Vin 0 0 1 2 3 4 5 6 7 8 12Vin 5Vin 9 0 10 0 1 2 LOAD CURRENT (A) 12 10 10 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 5 6 8 8 9 10 6 0 LFM 100LFM 200LFM 8 6 0 4 0 LFM 2 100LFM 0 35 45 55 65 75 85 35 45 55 65 o 85 AMBIENT TEMPERATURE ( C) FIG.32 DE-RATING CURVE at 12VIN, 1.5VOUT, 12PVCC FIG.33 DE-RATING CURVE at 5VIN, 1.5VOUT, 12PVCC 12 10 10 MAXIMUM LOAD CURRENT(A) 12 8 6 4 75 o AMBIENT TEMPERATURE ( C) MAXIMUM LOAD CURRENT(A) 7 FIG.31 3.3VOUT POWER LOSS at 12PVCC 12 2 4 LOAD CURRENT (A) FIG.30 1.5VOUT POWER LOSS at 12PVCC 4 3 0 LFM 100LFM 2 200LFM 0 8 6 4 0 LFM 100LFM 2 200LFM 0 35 45 55 65 75 85 o AMBIENT TEMPERATURE ( C) FIG.34 DE-RATING CURVE at 12VIN, 3.3VOUT, 12PVCC DS_MCM15S0A0Q10FA_05052011 35 45 55 65 75 85 o AMBIENT TEMPERATURE ( C) FIG.35 DE-RATING CURVE at 5VIN, 3.3VOUT, 12PVCC 18 PACKAGE OUTLINE DRAWING: Unit: mm DS_MCM15S0A0Q10FA_05052011 19 LAND PATTERN REFERENCE: Unit: mm TYPICAL RECOMMENDED LAND PATTERN STENCIL PATTERN WITH SQUIRE PADS-1 DS_MCM15S0A0Q10FA_05052011 STENCIL PATTERN WITH SQUIRE PADS-2 20 REFLOW PARAMETERS: Lead-free soldering process is a standard of making electronic products. Many solder alloys like Sn/Ag, Sn/Ag/Cu, Sn/Ag/Bi and so on are used extensively to replace traditional Sn/Pb alloy. Here the Sn/Ag/Cu alloy (SAC) are recommended for process. In the SAC alloy series, SAC305 is a very popular solder alloy which contains 3% Ag and 0.5% Cu. It is easy to get it. Figure 36 shows an example of reflow profile diagram. Typically, the profile has three stages. During the initial stage from 70C to 90C, the ramp rate of temperature should be not more than 1.5C/sec. The soak zone then occurs from 100C to 180C and should last for 90 to 120 seconds. Finally the temperature rises to 230C to 245C and cover 220C in 30 seconds to melt the solder. It is noted that the time of peak temperature should depend on the mass of the PCB board. The reflow profile is usually supported by the solder vendor and user could switch to optimize the profile according to various solder type and various manufactures' formula. FIG.36 RECOMMENDATION REFLOW PROFILE DS_MCM15S0A0Q10FA_05052011 21 STORAGE AND HANDLING: MOISTURE BARRIER BAG: Although POL module is a kind of package devices and its inner components are all protected by the package compounds, it is still probably damaged during soldering process if moisture is absorbed into package. The modules firstly are packed in a reel, and then an aluminum moisture barrier bag is used to pack the reel in order to prevent moisture absorption. Silica gel is put into the aluminum moisture barrier bag as absorbent material. STORAGE: The POL module pack storage follows the JEDEC J-STD-033B01 and J-STD-020C standards. Table 3 is the floor life and moisture sensitive level defined by JEDEC. POL module is classified into level 3. The floor life starts to estimate while the aluminum moisture barrier bag is opened. Under the storage situation of 30C/60% RH, the device can keep 168 hours floor life after the pack opened. If there are unused POL modules remained, they should be resealed in original moisture barrier bag as soon as possible. However, in case of the modules' floor life exceeding the defined time period, baking process will be necessary to dehumidify. The method is to bake the module in an oven at 125C/1% RH (e.g. hot nitrogen gas atmosphere) for 48 hours. HANDLING AND OTHERS: To protect the POL module and to make sure its normal use, something should be noticed as below. 1. Please handle the POL module carefully to avoid unnecessary mechanism stress on it. Improperly external stress may cause unexpected damage. 2. The ESD wrist strap, ESD shoe strap or anti-electrostatic gloves are recommended to be used whenever handling POL module. 3. If cleaning the module is necessary, please use alcohol or IPA solution to clean it under normal room temperature. Avoid the use of unspecified solvent. DS_MCM15S0A0Q10FA_05052011 22 STORAGE AND HANDLING: (Cont.) TABLE 3 MOISTURE CLASSIFICATION LEVEL AND FLOOR LIFE Level Floor Life (out of bag) at factory ambient 30C/60% RH or as stated 1 Unlimited at 30C/85% RH 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label. DS_MCM15S0A0Q10FA_05052011 23 PACKING INFORMATION: Unit: mm Tape and Reel Packing Sprocket hole 15,0 7,5 Pin 1 7,5 15,0 PACKAGE IN TAPE LOADING ORIENTATION t P2 P1 Sprocket hold 1.75 0.1 D0 F W B0 A0 K0 Carrier cavity P0 Pulling direction TAPE DIMENSION A0 16.20 0.10 t 0.30 0.05 B0 16.20 0.10 K0 3.70 0.10 F 11.5 0.10 P0 20.00 0.10 W 24.00 0.30 P1 2.00 0.10 D0 1.55 0.05 P2 4.00 0.10 DS_MCM15S0A0Q10FA_05052011 24 PACKING INFORMATION: (Cont.) Unit: mm W1=24.8 +0.6/-0.4 W2=30.2(MAX) REEL DIMENSION Peel Strength of Top Cover Tape The peel speed shall be about 300mm/min. The peel force of top cover tape shall between 0.1N to 0.7N Top Cover Tape 0.1N~0.7N 165~180 DS_MCM15S0A0Q10FA_05052011 25 PACKING INFORMATION: (Cont.) Unit: mm Tray Packing MODULE PIN 1 MODULE BEVEL Tray BEVEL PACKAGE IN TRAY LOADING ORIENTATION TRAY DIMENSION DS_MCM15S0A0Q10FA_05052011 26 PART NUMBERING SYSTEM MCM 15 S 0A0 Q 10 Product Input Voltage Number of Outputs Output Package Type Output Current 15 - 1.0V~15V S- Single Q - QFN 10 -10A Series MCM Series Voltage 0A0 - F A Option Code F- RoHS 6/6 (Lead Free) programmable A - Standard Functions MODEL LIST MODEL NAME INPUT MCM15S0A0Q10FA 1.0V~15V OUTPUT 0.6V~5.5V EFF @ 100% LOAD 10A 96% CONTACT: www.delta.com.tw/dcdc USA: Telephone: East Coast: (888) 335 8201 West Coast: (888) 335 8208 Fax: (978) 656 3964 Email: DCDC@delta-corp.com Europe: Telephone: +41 31 998 53 11 Fax: +41 31 998 53 53 Email: DCDC@delta-es.tw Asia & the rest of world: Telephone: +886 3 4526107 Ext.6220~6224 Fax: +886 3 4513485 Email: DCDC@delta.com.tw WARRANTY Delta offers a two (2) year limited warranty. Complete warranty information is listed on our web site or is available upon request from Delta. Information furnished by Delta is believed to be accurate and reliable. However, no responsibility is assumed by Delta for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Delta. Delta reserves the right to revise these specifications at any time, without notice. DS_MCM15S0A0Q10FA_05052011 27