74HC/HCT30 SSI 8-INPUT NAND GATE FEATURES TYPICAL Output capability: standard SYMBOL PARAMETER CONDITIONS UNIT Icc category: SSI HC HCT tpHt/ Propagation delay CL = 15 pF GENERAL DESCRIPTION tPLH A,B,C, D,E,F,G,HtoY| Vec=5V 12 12 ns The 74HC/HCT30 are high-speed . . Si-gate CMOS devices and are pin cy input capacitance 3.5 3.5 pF compatible with low power Schottky oe TTL (LSTTL}. They are specified in Cpp power dissipation notestand2 [15 | 15 | pF compliance with JEDEC standard no. 7A. capacitance per gate The 74HC/HCT30 provide the 8-input GND = 0 V: Tamb = 25 C: ty = te = ns NAWD function. Notes 1. CPp is used to determine the dynamic power dissipation (Pp in wW): Pp =Cpp x Vcc? x fi+ = (CL x Vcc? x fo) where: fj = input frequency in MHz CL = output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V (CL x Voc? x fy) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is V| = GND to Vcc 1.5 V PACKAGE OUTLINES 14-lead DIL; plastic (SOT27). 14-lead mini-pack; plastic (S014; SOT108A), PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 A data input 2 B data input 3 Cc data input 4 D data input 5 E data input 6 F data input 7 GND ground {0 V) 8 Y data output 9,10, 13 n.c. not connected 11 G data input 12 H data input 14 Vee positive supply voltage ali U 14] Voc tla a & a [2] 13} nc. 2\6 s c [3 | 12] H ac 4 alo off] 30 fils : | pe E [ej 10] ne, 6yF 4 11 F [] Ell nc. N46 RY eno [7 | ra]y 4H 7293815 7293814 7293817 Fig. 1 Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. December 1990 165 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT30 SSI 7293816 7293817 Fig. 4 Functional diagram; Y = ABCDEFGH. Fig. 5 Logic diagram, FUNCTION TABLE INPUTS OUTPUT o xx MM | Mm x=c KKK KRM RM YT = KO KK KKK | < KKK KKK | Iztir rirrle = KK KK KKM | x xXx MK RM KOK | x KK tc KKK MK MO KK |] OO Ic uMMKM Om KKX H x= x= a H = HIGH voltage level L = LOW voltage level X = don't care 166 January 1986 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.8-input NAND gate 74HC/HCT30 SSI DC CHARACTERISTICS FOR 74 HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard loc category: SSI AC CHARACTERISTICS FOR 74HC GND = OV; t,; = t=6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vec | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min, | typ. | max. | min. | max. | min. | max. tpHL/ propagation delay 1 ae s. ie ns ze Fic. 6 t . ig. PLH A,B,C, D, E, F, G, H to 12 22 28 33 60 tTHL! 19 #175 95 110 2.0 tT L output transition time 7 15 19 22 ns 45 Fig. 6 LH 6 |13 16 19 6.0 DC CHARACTERISTICS FOR 74HCT For the DG characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard Icc category: SSI Note to HCT types The value of additional quiescent suppty current (Alcqc) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT A,B, C, D, E, F,G,H 0.60 AC CHARACTERISTICS FOR 74HCT GND = 0 V; t, = tg = 6 ns; C, = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Vcc | WAVEFORMS +25 40 to +85 | 40to +125 Vv min.} typ. | max. | min.| max. | min. | max. tpHL/ propagation delay . tPLH A,B, C, 0, E, F,G, Hto Y 16 | 28 35 42 [ns 45 | Fig. 6 tTHL/ output transition time 7 15 19 22 ns 4.5 Fig. 6 TTLH March 1988 167 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT30 SSI AC WAVEFORMS A,B,C,0,E,F,G,H INPUT Y OUTPUT 77293819 Fig. 6 Waveforms showing the input (A, B, C, D, E, F, G, H) to output (Y) propagation delays and the output Note to AC waveforms transition times. Gy) HC : Vm = 50%; Vv =GND to Vee. HCT: Vy = 1.3V: Vy =GND to 3 V. 168 January 1986 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.