   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Controls Boost Preregulator to Near-Unity
Power Factor
Limits Line Distortion
World Wide Line Operation
Over-Voltage Protection
Accurate Power Limiting
Average Current Mode Control
Improved Noise Immunity
Improved Feed-Forward Line Regulation
Leading Edge Modulation
150-µA Typical Start-Up Current
Low-Power BiCMOS Operation
12-V to 17-V Operation
description
The UCCx817/18 family provides all the functions necessary for active power factor corrected preregulators.
The controller achieves near unity power factor by shaping the ac input line current waveform to correspond
to that of the ac input line voltage. Average current mode control maintains stable, low distortion sinusoidal line
current.
block diagram
UDG-98182
VREF9
2
16
1
15
10
5
4
DRVOUT
GND
CAI
VCC
OVP/EN
VAOUT
1.9 V
PKLMT
7.5 V
REFERENCE
UVLO
16 V/10 V (UCC2817)
10.5 V/10 V (UCC2818) VCC
3
OSCILLATOR
12
RT
14
CT
SQ
R
PWM
LATCH
+
PWM
CAOUT
+
+
+
SS
VOLTAGE
ERROR AMP 8.0 V
13
7
11VSENSE
VFF 8
IAC 6
MOUT
MIRROR
2:1
X2
+
7.5 V
ENABLE
OVP
÷
X
XMULT
OSC
CLK
CLK
CURRENT
AMP
16 V (FOR UCC2817 ONLY)
+
0.33 V ZERO POWER
R
+
Copyright 2000, Texas Instruments Incorporated
        
         
       
   
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D, DW, and N PACKAGES
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PKLMT
CAOUT
CAI
MOUT
IAC
VAOUT
VFF
DRVOUT
VCC
CT
SS
RT
VSENSE
OVP/EN
VREF
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
Designed in Texas Instrument’ s BiCMOS process, the UCC2817/UCC2818 offers new features such as lower
start-up current, lower power dissipation, overvoltage protection, a shunt UVLO detect circuitry, a leading-edge
modulation technique to reduce ripple current in the bulk capacitor and an improved, low-offset (±2 mV) current
amplifier to reduce distortion at light load conditions.
UCC2817 offers an on-chip shunt regulator with low start-up current, suitable for applications utilizing a
bootstrap supply. UCC2818 is intended for applications with a fixed supply (VCC).
Available in the 16-pin D, DW, and N packages.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage VCC 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate drive current, continuous 0.2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate drive current 1.2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, CAI, MOUT, SS 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, PKLMT 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VSENSE, OVP/EN 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, RT, IAC, PKLMT 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum negative voltage, DRVOUT, PKLMT, MOUT –0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AVAILABLE OPTIONS
PACKAGE DEVICES
D PACKAGE DW PACKAGE N PACKAGE
TJON-CHIP
SHUNT
REGULATOR
FIXED
SUPPLY (VCC) ON-CHIP
SHUNT
REGULATOR
FIXED
SUPPLY (VCC) ON-CHIP
SHUNT
REGULATOR
FIXED
SUPPLY (VCC)
–40°C to 85°C UCC2817D UCC2818D UCC2817DW UCC2818DW UCC2817N UCC2818N
0°C to 70°C UCC3817D UCC3818D UCC3817DW UCC3818DW UCC3817N UCC3818N
electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA
= TJ, VCC = 12 V, RT = 22 k, CT = 330 pF, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Supply Current Section
Supply current, off VCC = (VCC turn-on threshold –0.3 V) 150 300 µA
Supply current, on VCC = 12 V, No load on DRVOUT 2 4 6 mA
UVLO Section
VCC turn-on threshold (UCCx817) 15.4 16 16.6 V
UVLO hysteresis (UCCx817) 5.8 6.3 V
Maximum shunt voltage (UCCx817) IVCC = 10 mA 15.4 17 17.5 V
VCC turn-on threshold (UCCx818) 9.7 10.2 10.8 V
VCC turn-off threshold (UCCx818) 9.4 9.7 V
UVLO hysteresis (UCCx818) 0.3 0.5 V
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA
= TJ, VCC = 12 V, RT = 22 k, CT = 330 pF, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Voltage Amplifier Section
Input voltage
TA = 0°C to 70°C 7.387 7.5 7.613 V
Input voltage TA = –40°C to 85°C 7.369 7.5 7.631 V
VSENSE bias current VSENSE = VREF, VAOUT = 2.5 V 50 200 nA
Open loop gain VAOUT = 2 V to 5 V 50 90 dB
High-level output voltage IL = –150 µA 5.3 5.5 5.6 V
Low-level output voltage IL = 150 µA 0 50 150 mV
Over Voltage Protection and Enable Section
Over voltage reference VREF
+0.48 VREF
+0.50 VREF
+0.52 V
Hysteresis 300 500 600 mV
Enable threshold 1.7 1.9 2.1 V
Enable hysteresis 0.1 0.2 0.3 V
Current Amplifier Section
Input offset voltage VCM = 0 V, VCAOUT = 3 V –2 0 2 mV
Input bias current VCM = 0 V, VCAOUT = 3 V –50 –100 nA
Input offset current VCM = 0 V, VCAOUT = 3 V 25 100 nA
Open loop gain VCM = 0 V, VCAOUT = 2 V to 5 V 90 dB
Common-mode rejection ratio VCM = 0 V to 1.5 V, VCAOUT = 3 V 60 80 dB
High-level output voltage IL = –120 µA 5.6 6.5 6.8 V
Low-level output voltage IL = 1 mA 0.1 0.2 0.5 V
Gain bandwidth product See Note 1 2.5 MHz
Voltage Reference Section
Input voltage
TA = 0°C to 70°C 7.387 7.5 7.613 V
Input voltage TA = –40°C to 85°C 7.369 7.5 7.631 V
Load regulation IREF = 1 mA to 2 mA 0 10 mV
Line regulation VCC = 10.8 V to 15 V, See Note 2 0 10 mV
Short-circuit current VREF = 0 V –20 –25 –50 mA
Oscillator Section
Initial accuracy TA = 25°C 85 100 115 kHz
Voltage stability VCC = 10.8 V to 15 V –1 1 %
Total variation Line, temp 80 120 kHz
Ramp peak voltage 4.5 5 5.5 V
Ramp amplitude voltage
(peak to peak) 3.5 4 4.5 V
Peak Current Limit Section
PKLMT reference voltage –15 15 mV
PKLMT propagation delay 150 350 500 ns
NOTES: 1. Ensured by design, 100% production tested.
2. Reference variation for VCC < 10.8 V is shown in Figure 8.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics, TA = 0°C to 70°C for the UCC3817 and TA = –40°C to 85°C for the UCC2817, TA
= TJ, VCC = 12 V, RT = 22 k, CT = 330 pF, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Multiplier Section
High line, low power IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.25 V 0 –6 –20 µA
High line, high power IAC = 500 µA, VFF = 4.7 V, VAOUT = 5 V –75 –90 –110 µA
Low line, low power IAC = 150 µA, VFF = 1.4 V, VAOUT = 1.25 V –10 –19 –50 µA
Low line, high power IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V –260 –300 –360 µA
IAC limited IAC = 150 µA, VFF = 1.3 V, VAOUT = 5 V –250 –300 –400 µA
Gain constant (K) IAC = 300 µA, VFF = 3 V, VAOUT = 2.5 V 0.5 1 1.5 1/V
IAC = 150 µA, VFF = 1.4 V, VAOUT = 0.25 V 0 –2 µA
Zero current IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.25 V 0 –2 µA
Zero
current
IAC = 500 µA, VFF = 4.7 V, VAOUT = 0.5 V 0 –3 µA
Power limit IAC = 150 µA, VFF = 1.4 V, VAOUT = 5 V –360 –420 –500 µW
Feed-Forward Section
VFF output current IAC = 300 µA –140 –150 –160 µA
Soft Start Section
SS charge current –6 –10 –16 µA
Gate Driver Section
Pullup resistance IO = –100 mA 5 12
Pulldown resistance IO = 100 mA 2 10
Output rise time CL = 1 nF, RL = 10 25 50 ns
Output fall time CL = 1 nF, RL = 10 10 50 ns
Maximum duty cycle 93 95 100 %
Zero Power Section
Zero power comparator threshold Measured on VAOUT 0.20 0.33 0.50 V
pin descriptions
CAI: (current amplifier non-inverting input) This input and the inverting input (MOUT) remain functional down
to and below GND.
CAOUT: (current amplifier output) This is the output of a wide bandwidth operational amplifier that senses line
current and commands the PFC pulse-width modulator (PWM) to force the correct current.
CT: (oscillator timing capacitor) A capacitor from CT to GND sets the PWM oscillator frequency according to:
f0.725
RT CT
The lead from the oscillator timing capacitor to GND should be as short and direct as possible.
DRVOUT: (gate drive) The output drive for the PFC stage is a totem-pole MOSFET gate driver on DRVOUT.
Use a series gate resistor to prevent interaction between the gate impedance and the output driver that might
cause the DRVOUT to overshoot excessively. See characteristic curve (Figure 13) to determine minimum
required gate resister value. Some overshoot of the DRVOUT output is always expected when driving a
capacitive load.
GND: (ground) All voltages measured with respect to ground. VCC and REF should be bypassed directly to
GND with a 0.1-µF or larger ceramic capacitor.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin descriptions (continued)
IAC: (input ac current) This input to the analog multiplier is a current. The multiplier is tailored for very low
distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is 500 µA.
MOUT: (multiplier output and current amplifier inverting input) The output of the analog multiplier and the
inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this
is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration
improves noise immunity and allows for the leading-edge modulation operation. The multiplier is limited to
2IIAC. The multiplier output current is given by the equation:
IMOUT IIAC (VVAOUT 1)
VVFF2K
Where K 1
V is the multiplier gain constant.
OVP/EN: (over-voltage/enable) A window comparator input that disables the output driver if the boost output
is a programmed level above nominal or disables both the PFC output driver and resets SS if pulled below 1.9
V (typ).
PKLMT: (PFC peak current limit) The threshold for peak limit is 0 V. Use a resistor divider from the negative side
of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense
resistor and the peak current limit. Peak current limit is reached when PKLMT voltage falls below 0 V.
RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A
resistor between 10 k and 100 k is recommended.
SS: (soft-start) VSS is at ground for VVCC low conditions. When enabled, SS charges an external capacitor with
a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle
to increase slowly. I n the event of a VVCC dropout the OVP/EN is forced below 1.9 V (typ), SS quickly discharges
to disable the PWM.
Note: In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. Please see the
application section for details.
VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage.
The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.
VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 10 V and 17 V for normal
operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET
gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VVCC
exceeds the upper under-voltage lockout voltage threshold and remains above the lower threshold.
VFF: (feed-forward signal) RMS signal generated at this pin by mirroring IIAC into a single pole external filter.
RVFF
VVFF(max)
IIAC(max)
22
0.9
VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the
boost converter output through a divider network.
VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled
and remains at 0 V when VVCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger
ceramic capacitor for best stability. Please refer to Figures 8 and 9 for VREF line and load regulation
characteristics.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
The UCC3817 is a BiCMOS average current mode boost controller for high power factor, high efficiency
preregulator power supplies. Figure 1 shows the UCC3817 in a 250-W PFC preregulator circuit. Off-line
switching power converters normally have an input current that is not sinusoidal. The input current waveform
has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform.
An active power factor correction circuit programs the input current to follow the line voltage, forcing the
converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current
and voltage waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal
waveforms of the same frequency:
PF cos
Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD
(total harmonic distortion) less than 3% are possible with a well-designed circuit. Following guidelines are
provided to design PFC boost converters using the UCC3817.
UDG-98183
1
11
7
16GND DRVOUT
R17
20
15
C3
1µF CER
VCC
C2
100µF AI EI
14
C1
560pF
13 C4 0.01µF
12 R1 12k
R3 20k R2
499k
R4
249k
R5
10k
C5 1µF
9
4
10
VREF
VCC
CT
SS
RT
VSENSE
OVP/EN
VREF
VAOUT
3
8
2
VFF
C6 2.2µF
C7 150nF
R7 100k
6
5
R9
4.02k
C8 270pF
R8 12k
D6
R10
4.02k
D5
R11
10k
R12
2k
R14
0.25
5W
C13
0.47µF
600V
C14
1.5µF
400V
R13
383k
IAC R18
24k
R15
24k
R16
100
VCC
C10
1µFC11
1µF
D7 D8
L1
1mH
D2
6A, 600V
D1
8A, 600V
C12
220µF
450V
VOUT
385V–DC
+
PKLIMIT
CAOUT
CAI
MOUT
IAC
VO
UCC3817
VLINE
85–270 V
AC
VREF
C9 1.2nF
R6 30k
6A 600V
D3 Q1
F1
VO
D4
R19
499k
R20 274k
R21
383k
AC2
AC1
C15 2.2µF
IRFP450
Figure 1. Typical Application Circuit
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
power stage
LBOOST : The boost inductor value is determined by:
LBOOST VIN(min) D
(Ifs)
Where D is the duty cycle, I is the inductor ripple current and fS is the switching frequency. For the example
circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688 and a
minimum input voltage of 85 VRMS gives us a boost inductor value of about 1 mH. The values used in this
equation are at the peak of low line, where the inductor current and its ripple are at a maximum.
COUT : Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor.
The value of capacitance is determined by the hold-up time required for supporting the load after input ac voltage
is removed. Hold-up is the amount of time that the output stays in regulation after the input has been removed.
For this circuit, the desired hold-up time is approximately 16 ms. Expressing the capacitor value in terms of
output power, output voltage, and hold-up time gives the equation:
COUT 2POUT t
VOUT2VOUT(min)2
In practice, the calculated minimum capacitor value may be inadequate because output ripple voltage
specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often
necessitates the use of a much larger capacitor value than calculated. The amount of output capacitor ESR
allowed can be determined by dividing the maximum specified output ripple voltage by the inductor ripple
current. In this design hold-up time was the dominant determining factor and a 220-µF, 450-V capacitor was
chosen for the output voltage level of 385 VDC at 250 W.
power switch selection
As in any power supply design, tradeoffs between performance, cost and size have to be made. When selecting
a power switch, it can be useful to calculate the total power dissipation in the switch for several different devices
at the switching frequencies being considered for the converter . Total power dissipation in the switch is the sum
of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, COSS loss
and turn-on and turn-off losses:
PGATE QGATE VGATE fs
PCOSS 1
2COSS V2OFF fs
PON POFF 1
2VOFF ILtON tOFFfs
where Q GATE is the total gate charge, VGATE is the gate drive voltage, fS is the clock frequency, C OSS is the drain
source capacitance of the MOSFET, t ON and tOFF are the switching times (estimated using device parameters
RGATE, Q GD and VTH) and VOFF is the voltage across the switch during the off time, in this case VOFF = VOUT.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
power switch selection (continued)
Conduction loss is calculated as the product of the RDS(on) of the switch (at the worst case junction temperature)
and the square of RMS current:
PCOND RDS(on) KI2RMS
where K is the temperature factor found in the manufacturer’s RDS(on) vs. junction temperature curves.
Calculating these losses and plotting against frequency gives a curve that enables the designer to determine
either which manufacturer’s device has the best performance at the desired switching frequency, or which
switching frequency has the least total loss for a particular power switch. For this design example an IRFP450
HEXFET from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. The IRFP450’s
RDS(on) of 40 m and the maximum VDSS of 500 V made it an ideal choice. An excellent review of this procedure
can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W,
[Multiple
Output High Density DC/DC Converter]
.
softstart
The softstart circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished
by bringing up the voltage amplifier’s output (VVAOUT) slowly which allows for the PWM duty cycle to increase
slowly. Please use the following equation to select a capacitor for the softstart pin.
In this example tDELAY is equal to 7.5 ms, which would yield a CSS of 10 nF.
CSS 10 AtDELAY
7.5 V
In an open-loop test circuit, shorting the softstart pin to ground does not ensured 0% duty cycle. This is due to
the current amplifiers input offset voltage, which could force the current amplifier output high or low depending
on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and
bias current to overcome the current amplifier’s offset voltage.
multiplier
The output of the multiplier of the UCC3817 is a signal representing the desired input line current. It is an input
to the current amplifier, which programs the current loop to control the input current to give high power factor
operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the
multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representation of the input rectified ac line
voltage, and an input voltage feedforward signal, VVFF. The output of the multiplier, IMOUT, can be expressed:
IMOUT IIAC VVAOUT 1
KVVFF2
where K is a constant typically equal to 1
V.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
multiplier (continued)
The IIAC signal is obtained through a high-value resistor connected between the rectified ac line and the IAC
pin of the UCC3817. This resistor is sized to give the maximum IIAC current at high line. For this device, the
maximum I IAC current is about 500 µA. A higher current than this can drive the multiplier out of its linear range.
A smaller current level is functional, but noise can become an issue, especially at low input line. Assuming a
universal line operation of 85 VAC to 265 VAC gives a resistor value of 750 k. Because of voltage rating
constraints of standard 1/4 W resistors, use a combination of lower value resistors connected in series to give
the 750 k value and distribute the high voltage across two or more resistors.
The current through the IIAC resistor is mirrored internally to the VFF pin where it is filtered to produce a voltage
feedforward signal proportional to line voltage and free of a 120-Hz ripple component. This second harmonic
ripple component at the VFF pin is one of the major contributors to harmonic distortion in the system, so
adequate filtering is crucial. Refer to Unitrode Power Supply Design Seminar, SEM-700 Topic 7,
[Optimizing
the Design of a High Power Factor Preregulator.]
Assuming that an allocation of 1.5% total harmonic distortion
from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount
of attenuation required by this filter is:
1.5%
66% or 0.022
A ripple frequency (fR) of 120 Hz and an attenuation of 0.022 gives us a single-pole filter with:
fp 120 Hz 0.022 2.6 Hz
The range of this input to the multiplier should be 0.5 V to 5.5 V over the line input range. Therefore the filter
resistor should be sized accordingly. Maximum IIAC current is 500 µA, mirrored 2:1 to VFF, becomes 250 µA.
The dc output is 90% of the RMS value of this half sine wave, or 159 µA. So the filter resistor should be equal
to the voltage swing of the input to the multiplier divided by the dc current or:
5V
159 A31.44 k
Select a 30 k resistor for a standard value. Solving for the capacitor value:
CVFF 1
2(30 k)(2.6 Hz)2.2 F
This results in a single-pole filter, which adequately attenuates the harmonic distortion and also meets the dc
requirement of the proper voltage swing across line conditions.
The R MOUT resistor is sized to match the maximum current through the sense resistor to the maximum multiplier
current. The maximum multiplier current, or IMOUT(max), can be determined by the equation:
IMOUT(max)
IIAC@VIN(min) VVAOUT(max) 1V
KVVFF2(min)
IMOUT(max) for this design is approximately 315 µA. The RMOUT resistor can then be determined by:
RMOUT VRSENSE
IMOUT(max)
In this example RMOUT is equal to 3.91 k.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
voltage loop
The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic
of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple
at the input to the multiplier. The voltage loop must be compensated not just for stability but also to attenuate
the contribution of this ripple to the total harmonic distortion of the system. (refer to Figure 2).
RIN
RD+
Rf
Cf
VREF
VOUT
CZ
Figure 2. Voltage Amplifier Configuration
The gain of the voltage amplifier, GVA, can be determined by first calculating the amount of ripple present on
the output capacitor. The peak value of the second harmonic voltage is given by the equation:
VOPK PIN
2fRCOUT VOUT
In this example VOPK is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from
the voltage loop to the total harmonic distortion budget we set the gain equal to:
GVA VVAOUT(0.015)
VOPK
where VVAOUT is the effective output voltage range of the error amplifier (5 V for the UCC3817). The network
needed to r e a l i z e th i s filter is comprised of an input resistor, R IN, and feedback components Cf, CZ, and Rf. The
value of RIN is already determined because of its function as one half of a resistor divider from VOUT feeding
back to the voltage amplifier for output voltage regulation. In this case the value was chosen to be 1 M. This
high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be
realized by the use of two 500-k resistors in series because of the voltage rating constraints of most standard
1/4-W resistors. The value of Cf is determined by the equation:
Cf1
2fRGVA RIN
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
voltage loop (continued)
In this example Cf equals 150 nF. Resistor Rf sets the dc gain of the error amplifier and thus determines the
frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop
equation to one and solving for the crossover frequency. The frequency, expressed in terms of input power , can
be calculated by the equation:
fVI2PIN
(2)2VVAOUT VOUT RIN COUT Cf
fVI for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design
Seminar SEM1000, Topic 1,
[A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage
Transitions]
.
Solving for Rf becomes:
Rf1
2fVI Cf
or Rf equals 100 k.
Due to the low output impedance of the voltage amplifier, capacitor CZ was added in series with RF to reduce
loading on the voltage divider. To ensure the voltage loop crossed over at fVI, CZ was selected to add a zero
at a 10th of fVI. For this design a 2.2-µF capacitor was chosen for CZ. The following equation can be used to
calculate CZ.
CZ1
2fVI
10 Rf
current loop
The gain of the power stage is:
GID(s) VOUT RSENSE
sLBOOST VP
RSENSE has been chosen to give the desired differential voltage for the current sense amplifier at the desired
current limit point. In this example, a current limit of 4 A and a reasonable dif ferential voltage to the current amp
of 1 V gives a RSENSE value of 0.25 . VP in this equation is the voltage swing of the oscillator ramp, 4 V for
the UCC3817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz,
requires a power stage gain at that frequency of 0.383. In order for the system to have a gain of 1 at the crossover
frequency, the current amplifier needs to have a gain of 1/GPS at that frequency. GEA, the current amplifier gain
is then:
GEA 1
GID 1
0.383 2.611
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
current loop (continued)
RI is the RMOUT resistor, previously calculated to be 3.9 k. (refer to Figure 3). The gain of the current amplifier
is Rf/RI, so multiplying RI by GEA gives the value of Rf, in this case approximately 12 k. Setting a zero at the
crossover frequency and a pole at half the switching frequency completes the current loop compensation.
CZ1
2RffC
CP1
2Rffs
2
RI
+
Rf
CP
CAOUT
CZ
Figure 3. Current Loop Compensation
The UCC3817 current amplifier has the input from the multiplier applied to the inverting input. This change in
architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier.
It also adds a phase inversion into the control loop. The UCC3817 takes advantage of this phase inversion to
implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc
controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and
cost and reducing EMI. This is explained in greater detail in a following section. The UCC3817 current amplifier
configuration is shown in Figure 4.
+
+
RSENSE +
MULT
ZfPWM
COMPARATOR
CA
QBOOST
LBOOST
VOUT
Figure 4. UCC3817 Current Amplifier Configuration
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
start up
The UCC3818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817
has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown in the typical
application circuit of Figure 1. The current drawn by the UCC3817 during undervoltage lockout, or start-up
current, is typically 150 µA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA
typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt
regulator during power up. Once the circuit is operational the bootstrap winding of the inductor provides the VCC
voltage. Sizing of the start-up resistor is determined by the start-up time requirement of the system design.
ICCV
t
RVRMS (0.9)
IC
Where I C is the charge current, C is the total capacitance at the VCC pin, V is the UVLO threshold and t is the
allowed start-up time.
Assuming a 1 second allowed start-up time, a 16-V UVLO threshold, and a total VCC capacitance of 100 µF,
a resistor value of 51 k is required at a low line input voltage of 85 VRMS. The IC start-up current is sufficiently
small as to be ignored in sizing the start-up resistor.
capacitor ripple reduction
For a power system where the PFC boost converter is followed by a dc-to-dc converter stage, there are benefits
to synchronizing the two converters. In addition to the usual advantages such as noise reduction and stability,
proper synchronization can significantly reduce the ripple currents in the boost circuit’s output capacitor.
Figure 5 helps illustrate the impact of proper synchronization by showing a PFC boost converter together with
the simplified input stage of a forward converter. The capacitor current during a single switching cycle depends
on the status of the switches Q1 and Q2 and is shown in Figure 6. It can be seen that with a synchronization
scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple
is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime
is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon
of Q2. This approach implies that the boost converter’s leading edge is pulse width modulated while the forward
converter is modulated with traditional trailing edge PWM. The UCC3817 is designed as a leading edge
modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 1 compares
the ICB(rms) for D1/Q2 synchronization as offered by UCC3817 vs. the ICB(rms) for the other extreme of
synchronizing the turnon of Q1 and Q2 for a 200-W power system with a VBST of 385 V.
UDG-97130-1
Figure 5. Simplified Representation of a 2-Stage PFC Power Supply
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitor ripple reduction (continued)
UDG-97131
Figure 6. Timing Waveforms for Synchronization Scheme
Table 1. Effects of Synchronization on Boost Capacitor Current
VIN = 85 V VIN = 120 V VIN = 240 V
D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2
0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A
0.45 1.432 A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A
Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 7 shows the suggested
technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximum ripple
reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its
choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs
where holdup time is not critical, this is a significant advantage.
An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the
turnon of Q 1 i s synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters, the synchronization is much more dif ficult to achieve and
the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitor ripple reduction (continued)
CT
RT
RT
CT
D2
D1
C1
Gate Drive
From Down
Stream PWM
UCC3817
Figure 7. Synchronizing the UCC3817 to a Down-Stream Converter
Figure 8
141210
7.45
7.50
7.55
7.60
7.40
VCC – Supply Voltage – V
13119
VREF – Reference Voltage – V
REFERENCE VOLTAGE
vs.
SUPPLY VOLTAGE
Figure 9
REFERENCE VOLTAGE
vs.
REFERENCE CURRENT
0 5 10 15 20 25
7.495
7.500
7.505
7.510
7.490
VREF – Reference Voltage – V
IVREF – Reference Current – mA
   
   
SLUS395C - FEBRUARY 2000 - REVISED AUGUST 2000
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 10
MULTIPLIER OUTPUT CURRENT
vs.
VOLTAGE ERROR AMPLIFIER OUTPUT
0.0 1.0 2.0 3.0 4.0 5.0
50
200
250
350
0
100
300
150
IAC = 150 µA
IAC = 300 µA
IAC = 500 µA
IMOUT - Multiplier Output Current µA
VAOUT – Voltage Error Amplifier Output – V
Figure 11
MULTIPLIER GAIN
vs.
VOLTAGE ERROR AMPLIFIER OUTPUT
1.0 2.0 3.0 4.0 5.0
0.7
1.1
1.3
1.5
0.5
0.9 IAC = 300 µA
IAC = 500 µA
IAC = 150 µA
Multiplier Gain – K
VAOUT – Voltage Error Amplifier Output – V
Figure 12
VFF – Feedforward Voltage – V
1.0 2.0 3.0 4.0 5.0
100
300
400
500
0
200
VAOUT = 3 V
VAOUT = 2 V
VAOUT = 4 V
VAOUT = 5 V
(VFF × IMOUT) – µW
MULTIPLIER CONSTANT POWER PERFORMANCE
0.0
Figure 13
10 12 14 16 20
10
14
15
17
8
12
18
9
11
13
16
RECOMMENDED MINIMUM GATE RESISTANCE
vs.
SUPPLY VOLTAGE
RGATE - Recommended Minimum Gate Resistance
VCC – Supply Voltage – V
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated